20 #ifndef FPGA_BILU0_HEADER_INCLUDED
21 #define FPGA_BILU0_HEADER_INCLUDED
25 #include <opm/simulators/linalg/bda/ILUReorder.hpp>
26 #include <opm/simulators/linalg/bda/BlockedMatrix.hpp>
37 template <
unsigned int block_size>
46 std::unique_ptr<BlockedMatrix<block_size> > LMat =
nullptr, UMat =
nullptr, LUMat =
nullptr;
47 std::shared_ptr<BlockedMatrix<block_size> > rMat =
nullptr;
48 double *invDiagVals =
nullptr;
49 std::vector<int> diagIndex;
50 std::vector<int> toOrder, fromOrder;
51 std::vector<int> rowsPerColor;
56 std::vector<std::vector<double> > nnzValues, LnnzValues, UnnzValues;
57 std::vector<short int> colIndices, LColIndices, UColIndices;
58 std::vector<unsigned char> NROffsets, LNROffsets, UNROffsets;
59 std::vector<int> PIndicesAddr, LPIndicesAddr, UPIndicesAddr;
60 std::vector<int> colorSizes, LColorSizes, UColorSizes;
61 std::vector<int> nnzValsSizes, LnnzValsSizes, UnnzValsSizes;
62 std::vector<std::vector<int> > colIndicesInColor, LColIndicesInColor, UColIndicesInColor;
65 int LRowSize, LValSize, LNumColors;
66 int URowSize, UValSize, UNumColors;
67 std::vector<double> blockDiag;
68 ILUReorder opencl_ilu_reorder;
69 bool level_scheduling =
false, graph_coloring =
false;
70 int numResultPointers = 21;
71 std::vector<void *> resultPointers;
72 int numResultSizes = 18;
73 std::vector<int> resultSizes;
74 int maxRowsPerColor, maxColsPerColor, maxNNZsPerRow, maxNumColors;
78 FPGABILU0(ILUReorder opencl_ilu_reorder,
int verbosity,
int maxRowsPerColor,
int maxColsPerColor,
int maxNNZsPerRow,
int maxNumColors);
90 return toOrder.data();
95 return fromOrder.data();
103 void **getResultPointers()
105 return resultPointers.data();
108 int *getResultSizes()
110 return resultSizes.data();
This struct resembles a blocked csr matrix, like Dune::BCRSMatrix.
Definition: BlockedMatrix.hpp:36
Definition: FPGABILU0.hpp:39