Schematic Editor

#regulators 'LP2985LV' 'Package_TO_SOT_SMD:SOT-23-5_HandSoldering' ```

==== Den aktuellen Footprint anzeigen

The Footprint Assignment Tool contains a footprint viewer. Clicking the image:images/icons/icon_footprint_browser_24.png[footprint viewer icon] button in the top toolbar launches the footprint viewer and shows the selected footprint.

image::images/de/footprint_view.png[scaledwidth="90%", alt="Den aktuellen Footprint anzeigen"]

The top toolbar contains the following commands:

[width="90%", cols="10%,90%"]
|=======================================================================
|image:images/icons/refresh_24.png[]
|Refresh view
|image:images/icons/zoom_in_24.png[]
|Zoom in

|image:images/icons/zoom_out_24.png[]
|Zoom out

|image:images/icons/zoom_fit_in_page_24.png[]
|Zoom to fit drawing in display area

|image:images/icons/shape_3d_24.png[]
|Show 3D viewer
|=======================================================================

The left toolbar contains the following commands:

[width="90%", cols="10%,90%"]
|=======================================================================
|image:images/icons/cursor_24.png[]
|Use the select tool

|image:images/icons/measurement_24.png[]
|Interactively measure between two points

|image:images/icons/grid_24.png[]
|Display grid dots or lines

|image:images/icons/polar_coord_24.png[]
|Switch between polar and cartesian coordinate systems

|image:images/icons/unit_inch_24.png[]
|Use inches

|image:images/icons/unit_mil_24.png[]
|Display coordinates in mils (1/1000 of an inch)

|image:images/icons/unit_mm_24.png[]
|Display coordinates in millimeters

|image:images/icons/cursor_shape_24.png[]
|Toggle display of full-window crosshairs

|image:images/icons/pad_number_24.png[]
|Toggle between drawing pads in sketch or normal mode

|image:images/icons/pad_sketch_24.png[]
|Toggle between drawing pads in normal mode or outline mode

|image:images/icons/text_sketch_24.png[]
|Toggle between drawing text in normal mode or outline mode

|image:images/icons/show_mod_edge_24.png[]
|Toggle between drawing graphic lines in normal mode or outline mode
|=======================================================================

===== Anzeige des aktuellen 3D-Modells
Clicking the image:images/icons/shape_3d_24.png[3D Viewer icon] button opens the footprint in the 3D model viewer.

NOTE: If a 3D model does not exist for the current footprint, only the footprint itself will be shown in the 3D Viewer.

image::images/de/3d_window.png[scaledwidth="90%", alt="3D-Modell Ansicht"]

The 3D Viewer is described in the xref:../pcbnew/pcbnew_inspecting.adoc#threed-viewer[PCB Editor manual].

:experimental:

[[erc]]
== Entwurfsprüfung mit ERC (Elektrische Regel Prüfung)

=== Einleitung

The Electrical Rules Check (ERC) tool performs an automatic check of your schematic. The ERC checks for any errors in your sheet, such as unconnected pins, unconnected hierarchical symbols, shorted outputs, etc. ERC output is reported as errors or warnings depending on the severity of the issue detected.

Naturally, an automatic check is not infallible, and it is not possible to detect all design errors. Such a check is still very useful, because it allows you to detect many oversights and small errors. All detected issues should be checked and addressed before proceeding.

The quality of the ERC is directly related to the care taken in declaring electrical pin properties during symbol library creation.

image::images/de/dialog_erc.png[alt="ERC Dialog", scaledwidth="70%"]

[[how-to-use-erc]]
=== ERC Benutzung

ERC can be started by clicking on the icon image:images/icons/erc_24.png[ERC icon].

Warnungen werden auf den Schaltplanelementen platziert, die einen ERC Fehler verursachen (z.B. Anschlüsse oder Label).

[NOTE]
====
* Im Dialogfenster können Sie durch anklicken der Fehlermeldung auf die zugehörige Markierung im Schaltplan springen.
* Und umgekehrt bewirkt ein Doppelklick mit der linken Maustaste auf einer Markierung im Schaltplan die Anzeige des zugehörigen Prüfergebnisses.
====

You can also delete error markers from the dialog and set specific ERC messages to be suppressed by using the right-click context menu.

image::images/erc_ignore_warning.png[alt="Ignore ERC warning", scaledwidth="70%"]

[[example-of-erc]]
=== Beispiel eines ERC mit Fehlern

image::images/de/erc_pointers.png[alt="ERC Markierungen", scaledwidth="70%"]

Hier sehen Sie vier Fehler:

* Zwei Ausgänge wurden fehlerhaft miteinander verbunden (roter Pfeil am Pin 6).
* Zwei Eingänge wurden offen gelassen (grüner Pfeil an den Pins 4 und 5).
* Es gibt einen Fehler an einem ausgeblendeten Spannungsanschluss, die Markierung der Spannungsversorgung fehlt (grüner Pfeil am Gatter U1B).

[[displaying-diagnostics]]
=== Prüfergebnisse anzeigen

Mit doppelten Linksklick oder bei mehrfachen Auswahlmöglichkeiten unter dem Cursor nach Auswahl der Fehlermarkierung bei einem Rechtsklick zeigt Ihnen das Pop-Up Menü das Prüfergebnis zur Markierung.

image::images/de/erc_pointers_info.png[alt="Anwahl ERC Markierung", scaledwidth="70%"]

Wenn Sie auf den Marker zur Fehlerinformation klicken, erhalten Sie eine Beschreibung des Fehlers.

image::images/de/erc_pointers_message.png[alt="ERC pointers message", scaledwidth="80%"]

[[power-pins-and-power-flags]]
=== Spannungsversorgungsanschlüsse und Markierungen von Spannungsversorgungen

It is common to have an error or a warning on power pins, as shown in the example above, even though all seems normal. This happens in designs where the power is provided through connectors or other components that are not marked as power sources (unlike a regulator output, which is represented by a Power Out pin). Therefore ERC won't detect any Power Out pin connected to the net and will determine it is not driven by a power source.

To avoid this warning, connect the net to `PWR_FLAG` symbol on such a power net as shown in the following example. The `PWR_FLAG` symbol is found in the `power` symbol library. Alternatively, connect any power output pin to the net; `PWR_FLAG` is simply a symbol with a single power output pin.

image::images/eeschema_power_pins_and_flags.png[alt="Power pins and flags", scaledwidth="70%"]

Die Fehlermarkierung wird dann verschwinden.

Ground nets often need a `PWR_FLAG` as well, because voltage regulators have outputs declared as power outputs, but their ground pins are typically marked as power inputs. Therefore grounds can appear unconnected to a source unless a `PWR_FLAG` symbol is used.

[[configuration]]
=== Konfiguration

The _Pin Conflicts Map_ panel in Schematic Setup allows you to configure connectivity rules to define electrical conditions for errors and warnings based on what types of pins are connected to each other

image::images/de/dialog_erc_opts.png[alt="Schematic ERC Pin Conflicts Map", scaledwidth="70%"]

Die Regeln können durch Klicken auf das gewünschte Kästchen in der Matrix geändert werden, es wird bei jedem Klick durch die Auswahl mit diesen Optionen fortlaufend iteriert: Normal, Warnung, Fehler.

image::images/eeschema_erc_severity.png[alt="Schematic ERC severity settings", scaledwidth="70%"]
The _Violation Severity_ panel in Schematic Setup lets you configure what types of ERC messages should be reported as Errors, Warnings or ignored.

[[erc-report-file]]
=== ERC Protokolldatei

Eine ERC Protokolldatei kann erstellt und abgespeichert werden indem die Option "ERC Protokolldatei erstellen" aktiviert wird. Die Dateiendung für eine ERC Protokolldatei ist .erc. Hier ist ein Beispiel einer ERC Protokolldatei:

----------------------------------------------------------------------
ERC control (4/1/1997-14:16:4)

***** Sheet 1 (INTERFACE UNIVERSAL)
ERC: Warning Pin input Unconnected @ 8.450, 2.350
ERC: Warning passive Pin Unconnected @ 8.450, 1.950
ERC: Warning: BiDir Pin connected to power Pin (Net 6) @ 10.100, 3.300
ERC: Warning: Power Pin connected to BiDir Pin (Net 6) @ 4.950, 1.400

>> Errors ERC: 4
----------------------------------------------------------------------

:experimental:

[[schematic-to-pcb]]
== Transfer Schematic to PCB

=== Überblick
Use the Update PCB from Schematic tool to sync design information from the Schematic Editor to the Board Editor. The tool can be accessed with **Tools** -> **Update PCB from Schematic** (kbd:[F8]) in both the schematic and board editors. You can also use the image:images/icons/update_pcb_from_sch_24.png[Update PCB from Schematic icon] icon in the top toolbar of the Board Editor.

NOTE: Update PCB from Schematic is the preferred way to transfer design information from the schematic to the PCB. In older versions of KiCad, the equivalent process was to export a netlist from the Schematic Editor and import it into the Board Editor. It is no longer necessary to use a netlist file.

image::images/update_pcb_from_schematic.png[alt="Update PCB from schematic", scaledwidth="70%"]

The tool adds the footprint for each symbol to the board and transfers updated schematic information to the board. In particular, the board's net connections are updated to match the schematic.

The changes that will be made to the PCB are listed in the _Changes To Be Applied_ pane. The PCB is not modified until you click the **Update PCB** button.

You can show or hide different types of messages using the checkboxes at the bottom of the window. A report of the changes can be saved to a file using the **Save...** button.

=== Options

The tool has several options to control its behavior.

[cols="1,2"]
|===
| Option | Description

| Re-link footprints to schematic symbols based on their reference designators
| Footprints are normally linked to schematic symbols via a unique identifier
created when the symbol is added to the schematic. A symbol's unique identifier
cannot be changed.

If checked, each footprint in the PCB will be re-linked to the symbol that has
the same reference designator as the footprint.

If unchecked, footprints and symbols will be linked by unique identifier as
usual, rather than by reference designator. Each footprint's reference
designator will be updated to match the reference designator of its linked
symbol.

This option should generally be left unchecked. It is useful for specific
workflows that rely on changing the links between schematic symbols and
footprints, such as refactoring a schematic for easier layout or replicating
layout between identical channels of a design.

| Delete footprints with no symbols
| If checked, any footprint in the PCB without a corresponding symbol in the
schematic will be deleted from the PCB. Footprints with the "Not in schematic"
attribute will be unaffected.

If unchecked, footprints without a corresponding symbol will not be deleted.

| Replace footprints with those specified in the schematic
| If checked, footprints in the PCB will be replaced with the footprint that is
specified in the corresponding schematic symbol.

If unchecked, footprints that are already in the PCB will not be changed, even
if the schematic symbol is updated to specify a different footprint.
|===

:experimental:

[[plot-and-print]]
== Plotten und Drucken

=== Einleitung

Sie können auf die Druck- und Plotbefehle über das Menü "Datei" zugreifen.

image::images/de/eeschema_file_menu_plot.png[alt="Auswahl der Befehle für Drucken und Plotten", scaledwidth="60%"]

The supported output formats are Postscript, PDF, SVG, DXF and HPGL. You can also directly print to your printer.

[[common-printing-commands]]
=== Übliche Druckbefehle:

Aktuelle Seite drucken:: Druckt eine Datei nur für das aktuelle Arbeitsblatt.

Alle Seiten drucken:: Erlaubt es Ihnen die ganze Hierarchie auszudrucken (für jedes Arbeitsblatt wird eine Druckdatei erzeugt).

[[plot-in-postscript]]
=== Ausgabe nach Postscript

Dieser Befehl erlaubt es Ihnen Postscriptdateien zu erzeugen.

image::images/de/eeschema_plot_postscript.png[alt="Druckdialog für Postscriptausgabe", scaledwidth="70%"]

Der Dateiname ist der des Schaltplans mit der Erweiterung .ps. Sie können die Option "Schaltplanumrahmung und -betitelung drucken" abwählen. Das ist hilfreich, wenn Sie eine gekapselte Postscriptdatei erzeugen wollen (Dateiformat .eps), wie es häufig verwendet wird um Diagramme in einer Textverarbeitungssoftware einzufügen. Das Benachrichtigungsfenster zeigt den Dateinamen der erzeugten Datei.

[[plot-in-pdf]]
=== Ausgabe nach PDF

image::images/de/eeschema_plot_pdf.png[alt="Druckdialog für PDF Ausgabe", scaledwidth="70%"]

Erlaubt es Ihnen Druckdateien im PDF Format zu erstellen. Der Dateiname ist der Schaltplanname mit der Erweiterung .pdf.

[[plot-in-svg]]
=== Ausgabe nach SVG

image::images/de/eeschema_plot_svg.png[alt="Druckdialog für SVG Ausgabe", scaledwidth="70%"]

Erlaubt es Ihnen Druckdateien im vektorisierten SVG Format zu erstellen. Der Dateiname ist der Blattname mit der Erweiterung .svg.

[[plot-in-dxf]]
=== Ausgabe nach DXF

image::images/de/eeschema_plot_dxf.png[alt="Druckdialog für DXF Ausgabe", scaledwidth="70%"]

Erlaubt es Ihnen Druckdateien im DXF Format zu erstellen. Der Dateiname ist der Blattname mit der Erweiterung .dxf.

[[plot-in-hpgl]]
=== Ausgabe nach HPGL

Dieser Befehl erlaubt es Ihnen eine HPGL Datei zu erstellen. In diesem Format können Sie festlegen:

* Blattgröße
* (Koordinaten-)Ursprung
* Stiftdicke in mm.

Das Dialogfenster der Plottereinstellungen sieht wie folgt aus:

image::images/de/eeschema_plot_hpgl.png[alt="Druckdialog für HPGL Ausgabe", scaledwidth="70%"]

Die Ausgabedatei wird den Schaltplannamen plus die Erweiterung .plt haben.

[[sheet-size-selection]]
==== Auswahl der Seitengröße

Die Seitengröße ist normalerweise auf die Schaltplangröße gesetzt. In diesem Fall wird die im Titelblock festgelegte Blattgröße verwendet und der gewählte Maßstab wird 1:1 sein. Wenn eine andere Blattgröße ausgewählt wird (A4 bis A0 oder A bis E) wird der Maßstab automatisch angepasst, um die Seite zu füllen.

[[offset-adjustments]]
==== Offset Anpassungen

Für alle Standardabmessungen können Sie den Offset anpassen, um die Zeichnung so präzise wie möglich zu zentrieren. Weil Plotter ihren (Koordinaten-)Ursprung in der Mitte oder in der unteren linken Ecke des Blattes haben, ist es notwendig einen Ursprung festzulegen, um korrekt drucken zu können.

Allgemein ausgedrückt:

* Für Plotter, die ihren Koordinatenursprung in der Mitte des Blattes haben, muss der Offset negativ sein und auf die Hälfte der Blattabmessungen gesetzt werden.
* Für Plotter die ihren Koordinatenursprung an der unteren linken Ecke haben muss der Offset auf 0 gesetzt werden.

Um einen Offset einzustellen:

* Wählen Sie die Blattgröße.
* Setzen Sie den Offset X und Offset Y.
* Klicken Sie auf Offset übernehmen.

[[print-on-paper]]
=== Drucken auf Papier

This command, available via the icon image:images/icons/print_button_24.png[Print icon], allows you to visualize and generate design files for the standard printer.

image::images/de/print_dialog.png[alt="Druckdialog für Druckerausgabe", scaledwidth="50%"]

Die Option "Drucke Schaltplanreferenz und Schaltplanbetitelung" schaltet Blattreferenzen und Titelblock ein oder aus.

Die Option "Drucke Schwarz-Weiß" setzt den einfarbigen Druckmodus. Diese Option wird allgemein benötigt wenn sie einen Schwarzweiß Laserdrucker verwenden, weil sonst Farben in Halbtönen ausgegeben werden und häufig nicht gut lesbar sind.

:experimental:

[[symbol-editor]]
== Symbol Editor

[[general-information-about-symbol-libraries]]
=== General Information About Symbol Libraries

A symbol is a schematic element which contains a graphical representation, electrical connections, and text fields describing the symbol. Symbols used in a schematic are stored in symbol libraries. KiCad provides a symbol editing tool that allows you to create libraries, add, delete or transfer symbols between libraries, export symbols to files, and import symbols from files. The symbol editing tool provides a simple way to manage symbols and symbol libraries.

[[symbol-library-overview]]
=== Symbol Library Overview

A symbol library is composed of one or more symbols. Generally the symbols are logically grouped by function, type, and/or manufacturer.

A symbol is composed of:

* Graphical items (lines, circles, arcs, text, etc.) that determine how symbol looks in a schematic.
* Pins which have both graphic properties (line, clock, inverted, low level active, etc.) and electrical properties (input, output, bidirectional, etc.) used by the Electrical Rules Check (ERC) tool.
* Feldern für die Referenz, den Wert, zugehörige Footprintnamen für Leiterplattenentwurf, usw.

Symbols can be derived from another symbol in the same library. Derived symbols share the base symbol's graphical shape and pin definitions, but can override the base symbol's property fields (value, footprint, footprint filters, datasheet, description, etc.). Derived symbols can be used to define symbols that are similar to a base part. For example, 74LS00, 74HC00, and 7437 symbols could all be derived from a 7400 symbol. In previous versions of KiCad, derived symbols were referred to as aliases.

Proper symbol designing requires:

* Defining if the symbol is made up of one or more units.
* Defining if the symbol has an alternate body style (also known as a De Morgan representation).
* Dem Entwerfen seiner grafischen Darstellung mit Linien, Rechtecken, Kreisen, Polygonen und Text.
* Das Hinzufügen von Anschlüssen (Pins) unter sorgfältiger Festlegung der grafischen Elemente jedes Anschlusses, des Namens, der Nummer und der elektrischen Eigenschaften (Eingang, Ausgang, Tri-State, Spannungsausgang, usw.).
* Determining if the symbol should be derived from another symbol with the same graphical design and pin definition.
* Das Ergänzen von optionalen Feldern, wie der Name des Footprints, der für den Leiterplattenentwurf verwendet werden soll, und/oder die Festlegung ihrer Sichtbarkeit (im Schaltplan).
* Documenting the symbol by adding a description string and links to data sheets, etc.
* Das Abspeichern des Bauteils in der gewünschten Bibliothek.

[[symbol-library-editor-overview]]
=== Symbol Library Editor Overview

The symbol library editor main window is shown below. It consists of three tool bars for quick access to common features and a symbol viewing/editing area. Not all commands are available on the tool bars but can be accessed using the menus.

image::images/de/libedit_main_window.png[alt="Symbol Editor main window", scaledwidth="95%"]

[[main-toolbar]]
==== Hauptwerkzeugleiste

The main tool bar is located at the top of the main window. It consists of the undo/redo commands, zoom commands, symbol properties dialogs, and unit/representation management controls.

image::images/de/toolbar_libedit.png[alt="Symbol Editor toolbar", scaledwidth="95%"]

[width="100%", cols="20%,80%"]
|=======================================================================
|image:images/icons/new_component_24.png[New symbol icon]
|Create a new symbol in the selected library.

|image:images/icons/save_24.png[Save icon]
|Save the currently selected library. All modified symbols in the library will
be saved.

|image:images/icons/undo_24.png[Undo icon]
|Undo last edit.

|image:images/icons/redo_24.png[Redo icon]
|Redo last undo.

|image:images/icons/refresh_24.png[Refresh icon]|Refresh display.

|image:images/icons/zoom_in_24.png[Zoom in icon]|Zoom in.

|image:images/icons/zoom_out_24.png[Zoom out icon]|Zoom out.

|image:images/icons/zoom_fit_in_page_24.png[Zoom to fit page icon]|Zoom to fit symbol in display.

|image:images/icons/zoom_selection_24.png[Zoom to selection icon]|Zoom to fit selection.

|image:images/icons/rotate_ccw_24.png[Rotate counterclockwise icon]|Rotate counter-clockwise.

|image:images/icons/rotate_cw_24.png[Rotate clockwise icon]|Rotate clockwise.

|image:images/icons/mirror_h_24.png[Mirror horizontally icon]|Mirror horizontally.

|image:images/icons/mirror_v_24.png[Mirror vertically icon]|Mirror vertically.

|image:images/icons/part_properties_24.png[Symbol properties icon]
|Edit the current symbol properties.

|image:images/icons/pin_table_24.png[Pin table icon]
|Edit the symbol's pins in a tablular interface.

|image:images/icons/datasheet_24.png[Datasheet icon]
|Open the symbol's datasheet. The button will be disabled if no datasheet is
defined for the current symbol.

|image:images/icons/erc_24.png[ERC icon]
|Test the current symbol for design errors.

|image:images/icons/morgan1_24.png[Normal body style icon]
|Select the normal body style. The button is disabled if the current
symbol does not have an alternate body style.

|image:images/icons/morgan2_24.png[Alternate body style icon]
|Select the alternate body style. The button is disabled if the current
symbol does not have an alternate body style.

|image:images/toolbar_libedit_part.png[alt="Unit dropdown",width="80%"]
|Select the unit to display. The drop down control will be disabled if
the current symbol is not derived from a symbol with multiple units.

|image:images/icons/pin2pin_24.png[Synchronized pin edit mode icon]
|Enable synchronized pins edit mode. When this mode is enabled, any pin
modifications are propagated to all other symbol units. Pin number changes are
not propagated. This mode is automatically enabled for symbols with multiple
interchangeable units and cannot be enabled for symbols with only one unit.

|image:images/icons/add_symbol_to_schematic_24.png[Add symbol to schematic icon]
Insert current symbol into schematic.

|=======================================================================

[[element-toolbar]]
==== Werkzeugleiste Elemente

The vertical toolbar located on the right hand side of the main window allows you to place all of the elements required to design a symbol.

[width="100%", cols="10%,90%"]
|=======================================================================
|image:images/icons/cursor_24.png[Cursor icon]
|Select tool. Right-clicking with the select tool opens the context menu
for the object under the cursor. Left-clicking with the select tool
displays the attributes of the object under the cursor in the message
panel at the bottom of the main window. Double-left-clicking with the
select tool will open the properties dialog for the object under the
cursor.

|image:images/icons/pin_24.png[Pin icon]
|Pin tool. Left-click to add a new pin.

|image:images/icons/text_24.png[Text icon]
|Graphical text tool. Left-click to add a new graphical text item.

|image:images/icons/add_rectangle_24.png[Add rectangle icon]
|Rectangle tool. Left-click to begin drawing the first corner of a
graphical rectangle. Left-click again to place the opposite corner of
the rectangle.

|image:images/icons/add_circle_24.png[Add circle icon]
|Circle tool. Left-click to begin drawing a new graphical circle from
the center. Left-click again to define the radius of the circle.

|image:images/icons/add_arc_24.png[Add arc icon]
|Arc tool. Left-click to begin drawing a new graphical arc item from the
first arc end point. Left-click again to define the second arc end point.
Adjust the radius by dragging the arc center point.

|image:images/icons/add_line_24.png[Add line icon]
|Connected line tool. Left-click to begin drawing a new graphical line item
in the current symbol. Left-click for each additional connected line.
Double-left-click to complete the line.

|image:images/icons/anchor_24.png[Anchor icon]
|Anchor tool. Left-click to set the anchor position of the symbol.

|image:images/icons/delete_cursor_24.png[Delete icon]
|Delete tool. Left-click to delete an object from the current symbol.
|=======================================================================

[[options-toolbar]]
==== Werkzeugleiste für Einstellungen

The vertical tool bar located on the left hand side of the main window allows you to set some of the editor drawing options.

[width="100%", cols="10%,90%"]
|=======================================================================
|image:images/icons/grid_24.png[Grid icon]
|Toggle grid visibility on and off.

|image:images/icons/unit_inch_24.png[Inch unit icon]
|Set units to inches.

|image:images/icons/unit_mil_24.png[Millimeter unit icon]
|Set units to mils (0.001 inch).

|image:images/icons/unit_mm_24.png[Millimeter unit icon]
|Set units to millimeters.

|image:images/icons/cursor_shape_24.png[Cursor shape icon]
|Toggle full screen cursor on and off.

|image:images/icons/pin_show_etype_24.png[Show pintype icon]
|Toggle display of pin electrical types.

|image:images/icons/search_tree_24.png[Symbol tree icon]
|Toggle display of libraries and symbols.
|=======================================================================

[[library-selection-and-maintenance]]
=== Bibliotheksauswahl und Bibliothekswartung

The selection of the current library is possible via the image:images/icons/search_tree_24.png[Symbol tree icon] icon which shows you all available libraries and allows you to select one. When a symbol is loaded or saved, it will be put in this library. The library name of a symbol is the contents of its `Value` field.

[[select-and-save-a-symbol]]
==== Select and Save a Symbol

[[symbol-selection]]
===== Symbol Selection

Clicking the image:images/icons/search_tree_24.png[Symbol tree icon] icon on the left tool bar toggles the treeview of libraries and symbols. Clicking on a symbol opens that symbol.

[NOTE]
Some symbols are derived from other symbols. Derived symbol names are displayed in __italics__ in the treeview. If a derived symbol is opened, its symbol graphics will not be editable. Its symbol fields will be editable as normal. To edit the graphics of a base symbol and all of its derived symbols, open the base symbol.

[[save-a-symbol]]
===== Save a Symbol

After modification, a symbol can be saved in the current library or a different library.

To save the modified symbol in the current library, click the image:images/icons/save_24.png[Save icon] icon. The modifications will be written to the existing symbol.

NOTE: Saving a modified symbol also saves all other modified symbols in the same library.

To save the symbol changes to a new symbol, click **File** -> **Save As...**. The symbol can be saved in the current library or a different library. A new name can be set for the symbol.

To create a new file containing only the current symbol, click **File** -> **Export** -> **Symbol...**. This file will be a standard library file which will contain only one symbol.

[[creating-library-symbols]]
=== Creating Library Symbols

[[create-a-new-symbol]]
==== Create a New Symbol

A new symbol can be created by clicking the image:images/icons/new_component_24.png[New symbol icon] icon. You will be asked for a number of symbol properties.

* A symbol name (this name is used as the default value for the `Value` field in the schematic editor)
* An optional base symbol to derive the new symbol from. The new symbol will use the base symbol's graphical shape and pin configuration, but other symbol information can be modified in the derived symbol. The base symbol must be in the same library as the new derived symbol.
* The reference designator prefix (`U`, `C`, `R`...).
* The number of units per package, and whether those units are interchangeable (for example a 7400 is made of 4 units per package).
* If an alternate body style (sometimes referred to as a "De Morgan equivalent") is desired.
* Whether the symbol is a power symbol. Power symbols appear in the "Add Power Port" dialog in the Schematic editor, their `Value` fields are not editable in the schematic, they cannot be assigned a footprint and they are not added to the PCB, and they are not included in the bill of materials.
* Whether the symbol should be excluded from the bill of materials.
* Whether the symbol should be excluded from the PCB.

There are also several graphical options.

* The offset between the end of each pin and its pin name.
* Whether the pin number and pin name should be displayed.
* Whether the pin names should be displayed alongside the pins or at the ends of the pins inside the symbol body.

These properties can also be changed later in the <<symbol-properties, Symbol Properties window>>.

image::images/eeschema_new_symbol_properties.png[alt="New symbol properties", scaledwidth="50%"]

A new symbol will be created using the properties above and will appear in the editor as shown below.

image::images/de/eeschema_libedit_new.png[alt="Newly created symbol", scaledwidth="95%"]

The blue cross in the center is the symbol anchor, which specifies the symbol origin i.e. the coordinates (0, 0). The anchor can be repositioned by selecting the image:images/icons/anchor_24.png[Anchor icon] icon and clicking on the new desired anchor position.

[[create-a-symbol-from-another-symbol]]
==== Create a Symbol from Another Symbol

Often, the symbol that you want to make is similar to one already in a symbol library. In this case it is easy to load and modify an existing symbol.

* Load the symbol which will be used as a starting point.
* Save a new copy of the symbol using **File** -> **Save As...**. The Save As dialog will prompt for a name for the new symbol and the library to save it in.
* Edit the new symbol as required.
* Save the modified symbol.

[[symbol-properties]]
==== Symbol Properties

Symbol properties are set when the symbol is created but they can be modified at any point. To change the symbol properties, click on the image:images/icons/part_properties_24.png[Symbol properties icon] icon to show the dialog below.

image::images/eeschema_properties_for_symbol.png[alt="Symbol Properties", scaledwidth="60%"]

It is important to correctly set the number of units per package and the alternate symbolic representation, if enabled, because when pins are edited or created the corresponding pins for each unit will be affected. If you change the number of units per package after pin creation and editing, there will be additional work to specify the pins and graphics for the new unit. Nevertheless, it is possible to modify these properties at any time.

The graphic options "Show pin number" and "Show pin name" define the visibility of the pin number and pin name text. The option "Place pin names inside" defines the pin name position relative to the pin body. The pin names will be displayed inside the symbol outline if the option is checked. In this case the "Pin Name Position Offset" property defines the shift of the text away from the body end of the pin. A value from 0.02 to 0.05 inches is usually reasonable.

The example below shows a symbol with the "Place pin name inside" option unchecked. Notice the position of the names and pin numbers.

image::images/de/eeschema_uncheck_pin_name_inside.png[alt="Place pin name inside unchecked", scaledwidth="95%"]

[[symbol-name-description-and-keywords]]
===== Symbol Name, Description, and Keywords

The symbol's name is the same as the `Value` field. When the symbol name is changed the value also changes, and vice versa. The symbol's name in the library also changes accordingly.

The symbol description should contain a brief description of the component, such as the component function, distinguishing features, and package options. The keywords should contain additional terms related to the component. Keywords are used primarily to assist in searching for the symbol.

image::images/eeschema_add_symbol_search_description.png[alt="Searching for a symbol in the add a symbol dialog", scaledwidth="65%"]

A symbol's name, description, and keywords are all used when searching for symbols in the Symbol Editor and Add a Symbol dialog. The description and keywords are displayed in the Symbol Library Browser and Add a Symbol dialog.

[[footprint-filters]]
===== Footprint Filters

The footprint filters tab is used to define which footprints are appropriate to use with the symbol. The filters can be applied in the Footprint Assignment tool so that only appropriate footprints are displayed for each symbol.

Multiple footprint filters can be defined. Footprints that match any of the filters will be displayed; if no filters are defined, then all footprints will be displayed.

Filters can use wildcards: `\*` matches any number of characters, including zero, and `?` matches zero or one characters. For example, `SOIC-*` would match the `SOIC-8_3.9x4.9mm_P1.27mm` footprint as well as any other footprint beginning with `SOIC-`. The filter `SOT?23` matches `SOT23` as well as `SOT-23`.

image::images/de/eeschema_libedit_footprint.png[alt="Footprint filters", scaledwidth="70%"]

[[symbols-with-alternate-symbolic-representation]]
==== Symbols with Alternate Symbolic Representation

If the symbol has an alternate body style defined, one body style must be selected for editing at a time. To edit the normal representation, click the image:images/icons/morgan1_24.png[Normal representation icon] icon.

To edit the alternate representation, click on the image:images/icons/morgan2_24.png[Alternate representation icon] icon. Use the image:images/toolbar_libedit_alias.png[images/toolbar_libedit_part.png] dropdown shown below to select the unit you wish to edit.

image::images/de/eeschema_libedit_select_unit.png[alt="Selecting a symbol unit", scaledwidth="80%"]

[[graphical-elements]]
=== Grafische Elemente

Graphical elements create the visual representation of a symbol and contain no electrical connection information. Graphical elements are created with the following tools:

* Linien und Polygone, die durch Anfangs- und Endpunkte definiert sind.
* Rechtecke, die durch zwei diagonale Ecken definiert sind.
* Kreise, die durch Zentrum und Radius definiert sind.
* Kreisbögen, die durch den Anfangs- und Endpunkt des Bogens und sein Zentrum definiert sind. Ein Kreisbogen geht von 0° bis 180°.

The vertical toolbar on the right hand side of the main window allows you to place all of the graphical elements required to design the representation of a symbol.

[[graphical-element-membership]]
==== Zugehörigkeit grafischer Elemente

Jedes grafische Element (Linie, Kreis Kreisbogen, usw.) kann als zugehörig zu allen Einheiten und/oder Bauform oder speziell für eine Einheit und/oder Bauform definiert werden. Elementeigenschaften können einfach und schnell über das Kontextmenü durch einen Rechtsklick auf das ausgewählte Element ausgewählt werden. Unten sehen Sie das Kontextmenü für ein Linienelement.

image::images/de/eeschema_libedit_context_menu.png[alt="Graphic line context menu", scaledwidth="80%"]

Sie können ebenfalls auf ein Element doppelklicken, um seine Eigenschaften zu bearbeiten. Unten ist der Eigenschaftendialog für die Eigenschaften eines Linienzuges zu sehen

image::images/de/eeschema_libedit_polyline_properties.png[alt="Graphic line properties", scaledwidth="50%"]

Die Eigenschaften eines grafischen Elementes sind:

* "Line width" defines the width of the element's line in the current drawing units.
* "Fill Style" determines if the shape defined by the graphical element is to be drawn unfilled, background filled, or foreground filled.
* "Common to all units in symbol" determines if the graphical element is drawn for each unit in symbol with more than one unit per package or if the graphical element is only drawn for the current unit.
* "Common to all body styles (De Morgan)" determines if the graphical element is drawn for each symbolic representation in symbols with an alternate body style or if the graphical element is only drawn for the current body style.

[[graphical-text-elements]]
==== Grafische Textelemente

The image:images/icons/text_24.png[Text icon] icon allows for the creation of graphical text. Graphical text is automatically oriented to be readable, even when the symbol is mirrored. Please note that graphical text items are not the same as symbol fields.

[[multiple-units-per-symbol-and-alternate-body-styles]]
=== Multiple Units per Symbol and Alternate Body Styles

Symbols can have up to two body styles (a standard symbol and an alternate symbol often referred to as a "De Morgan equivalent") and/or have more than one unit per package (logic gates for example). Some symbols can have more than one unit per package each with different symbols and pin configurations.

Consider for instance a relay with two switches, which can be designed as a symbol with three different units: a coil, switch 1, and switch 2. Designing a symbol with multiple units per package and/or alternate body styles is very flexible. A pin or a body symbol item can be common to all units or specific to a given unit or they can be common to both symbolic representation so are specific to a given symbol representation.

By default, pins are specific to a unit and body style. When a pin is common to all units or all body styles, it only needs to be created once. This is also the case for the body style graphic shapes and text, which may be common to each unit, but typically are specific to each body style).

[[example-of-a-symbol-with-multiple-noninterchangeable-units]]
==== Example of a Symbol With Multiple Noninterchangeable Units

For an example of a symbol with multiple units that are not interchangeable, consider a relay with 3 units per package: a coil, switch 1, and switch 2.

The three units are not all the same, so "All units are interchangeable" should be deselected in the Symbol Properties dialog. Alternatively, this option could have been specified when the symbol was initially created.

image::images/de/eeschema_libedit_not_interchangeable.png[alt="Uncheck all units are interchangeable", scaledwidth="60%"]

===== Unit A

image::images/eeschema_libedit_unit1.png[alt="Relay unit A", scaledwidth="45%"]

===== Unit B

image::images/eeschema_libedit_unit2.png[alt="Relay unit B", scaledwidth="45%"]

===== Unit C

image::images/eeschema_libedit_unit3.png[alt="Relay unit C", scaledwidth="45%"]

Unit A does not have the same symbol and pin layout as Units B and C, so the units are not interchangeable.

NOTE: "Synchronized Pins Edit Mode" can be enabled by clicking the image:images/icons/pin2pin_24.png[Synchronized pins edit mode icon] icon. In this mode, pin modifications are propagated between symbol units; changes made in one unit will be reflected in the other units as well. When this mode is disabled, pin changes made in one unit do not affect other units. This mode is enabled automatically when "All units are interchangeable" is checked, but it can be disabled. The mode cannot be enabled when "All units are interchangeable" is unchecked or when the symbol only has one unit.

[[graphical-symbolic-elements]]
===== Grafische Symbolelemente

Shown below are properties for a graphic body element. In the relay example above, the three units have different symbolic representations. Therefore, each unit was created separately and the graphical body elements have the "Common to all units in symbol" setting disabled.

image::images/de/eeschema_libedit_disable_common.png[alt="Disable common to all units in symbol", scaledwidth="70%"]

[[pin-creation-and-editing]]
=== Anschlusserstellung und Anschlussbearbeitung

You can click on the image:images/icons/pin_24.png[Pin icon] icon to create and insert a pin. The editing of all pin properties is done by double-clicking on the pin or right-clicking on the pin to open the pin context menu. Pins must be created carefully, because any error will have consequences on the PCB design. Any pin already placed can be edited, deleted, and/or moved.

[[pin-overview]]
==== Anschlussübersicht

A pin is defined by its graphical representation, its name and its number. The pin's name and number can contain letters, numbers, and symbols, but not spaces. For the Electrical Rules Check (ERC) tool to be useful, the pin's electrical type (input, output, tri-state...) must also be defined correctly. If this type is not defined properly, the schematic ERC check results may be invalid.

Wichtige Hinweise:

* Symbol pins are matched to footprint pads by number. The pin number in the symbol must match the corresponding pad number in the footprint.
* Do not use spaces in pin names and numbers. Spaces will be automatically replaced with underscores (`_`).
* To define a pin name with an inverted signal (overline) use the `~` (tilde) character followed by the text to invert in braces. For example `~{FO}O` would display [overline]#FO# O.
* If the pin name is empty, the pin is considered unnamed.
* Pin names can be repeated in a symbol.
* Pin numbers must be unique in a symbol.

[[pin-properties]]
==== Anschlusseigenschaften

image::images/de/eeschema_libedit_pin_properties.png[alt="Pin properties", scaledwidth="95%"]

Der Dialog der Anschlusseigenschaften erlaubt es Ihnen alle Eigenschaften eines Anschlusses, auch Pin genannt, zu bearbeiten. Dieser Dialog wird automatisch geöffnet, wenn Sie einen Anschluss erstellen oder auf einen vorhandenen Anschluss doppelklicken. Dieser Dialog erlaubt Ihnen diese Änderungen:

* The pin name and text size.
* The pin number and text size.
* The pin length.
* The pin electrical type and graphical style.
* Zugehörigkeit zu Einheit und alternativer Darstellung.
* Pin visibility.
* <<alternate-pin-definitions,Alternate pin definitions>>.

[[pin-graphic-styles]]
==== Pin Graphic Styles

Shown in the figure below are the different pin graphic styles. The choice of graphic style does not have any influence on the pin's electrical type.

image::images/de/eeschema_libedit_pin_properties_style.png[alt="Pin graphic styles", scaledwidth="95%"]

[[pin-electrical-types]]
==== Typen von Elektrischen Anschlüssen

Choosing the correct electrical type is important for the schematic ERC tool. ERC will check that pins are connected appropriately, for example ensuring that input pins are driven and power inputs receive power from an appropriate source.

[width="100%", cols="25%,75%"]
|=======================================================================
| Pin Type | Description
| Input | A pin which is exclusively an input.
| Output | A pin which is exclusively an output.
| Bidirectional | A pin that can be either an input or an output, such as a
microcontroller data bus pin.
| Tri-state | A three state output pin (high, low, or high impedance)
| Passive | A passive symbol pin: resistors, connectors, etc.
| Free | A pin that can be freely connected to any other pin without electrical
concerns.
| Unspecified | A pin for which the ERC check does not matter.
| Power input | A symbol's power pin. As a special case, power input pins that
are marked invisible are automatically connected to the net with the same name.
See the <<creating-power-ports, Power Ports section>> for more information.
| Power output | A pin that provides power to other pins, such as a regulator
output.
| Open collector | An open collector logic output.
| Open emitter | An open emitter logic output.
| Unconnected | A pin that should not be connected to anything.
|=======================================================================

[[pushing-pin-properties-to-other-pins]]
==== Pushing Pin Properties to Other Pins

You can apply the length, name size, or number size of a pin to the other pins in the symbol by right clicking the pin and selecting **Push Pin Length**, **Push Pin Name Size**, or **Push Pin Number Size**, respectively.

image::images/de/eeschema_libedit_pin_context_menu.png[alt="Pin context menu", scaledwidth="60%"]

[[defining-pins-for-multiple-units-and-alternate-symbolic-representations]]
==== Anschlüsse für mehrere Einheiten und alternative Darstellung definieren

Symbols with multiple units and/or graphical representations are particularly problematic when creating and editing pins. The majority of pins are specific to each symbol unit (because each unit has a different set of pins) and to each body style (because the form and position is different between the normal body style and the alternate form).

The symbol library editor allows the simultaneous creation of pins. By default, changes made to a pin are made for all units of a multiple unit symbol and to both representations for symbols with an alternate symbolic representation. The only exception to this is the pin's graphical type and name, which remain unlinked between symbol units and body styles. This dependency was established to allow for easier pin creation and editing in most cases. This dependency can be disabled by toggling the image:images/icons/pin2pin_24.png[Synchronized pin edit mode icon] icon on the main tool bar. This will allow you to create pins for each unit and representation completely independently.

Pins can be common or specific to different units. Pins can also be common to both symbolic representations or specific to each symbolic representation. When a pin is common to all units, it only has to drawn once. Pins are set as common or specific in the pin properties dialog.

An example is the output pin in the 7400 quad dual input NAND gate. Since there are four units and two symbolic representations, there are eight separate output pins defined in the symbol definition. When creating a new 7400 symbol, unit A of the normal symbolic representation will be shown in the library editor. To edit the pin style in the alternate symbolic representation, it must first be enabled by clicking the image:images/icons/morgan2_24.png[Alternate representation icon] button on the tool bar. To edit the pin number for each unit, select the appropriate unit using the image:images/toolbar_libedit_alias.png[images/toolbar_libedit_alias.png] drop down control.

[[pin-table]]
==== Pin Table

Another way to edit pins is to use the Pin Table, which is accessible via the image:images/icons/pin_table_24.png[Pin table icon] icon. The Pin Table displays all of the pins in the symbol and their properties in a table view, so it is useful for making bulk pin changes.

Any pin property can be edited by clicking on the appropriate cell. Pins can be added and removed with the image:images/icons/small_plus_16.png[Plus icon] and image:images/icons/small_trash_16.png[Trash icon] icons, respectively.

NOTE: Columns of the pin table can be shown or hidden by right-clicking on the header row and checking or unchecking additional columns. Some columns are hidden by default.

The screenshot below shows the pin table for a quad opamp.

image::images/eeschema_libedit_pin_table.png[alt="Pin table", scaledwidth="95%"]

[[alternate-pin-definitions]]
==== Alternate Pin Definitions

Pins can have alternate pin definitions added to them. Alternate pin definitions allow a user to select a different name, electrical type, and graphical style for a pin when the symbol has been placed in the schematic. This can be used for pins that have multiple functions, such as microcontroller pins.

Alternate pin definitions are added in the Pin Properties dialog as shown below. Each alternate definition contains a pin name, electrical type, and graphic style. This microcontroller pin has all of its peripheral functions defined in the symbol as alternate pin names.

image::images/eeschema_libedit_alternate_pin_definitions.png[alt="Alternate pin definitions", scaledwidth="60%"]

Alternate pin definitions are selected in the Schematic Editor once the symbol has been placed in the schematic. The alternate pin is assigned in the Alternate Pin Assignments tab of the Symbol Properties dialog. Alternate definitions are selectable in the dropdown in the Alternate Assignment column.

image::images/eeschema_alternate_pin_assignment_selection.png[alt="Selecting an alternate pin definition", scaledwidth="60%"]

[[symbol-fields]]
=== Symbol Fields

All library symbols are defined with four default fields. The reference designator, value, footprint assignment, and datasheet link fields are created whenever a symbol is created or copied. Only the reference designator and value fields are required.

Symbols defined in libraries are typically defined with only these four default fields. Additional fields such as vendor, part number, unit cost, etc. can be added to library symbols but generally this is done in the schematic editor so the additional fields can be applied to all of the symbols in the schematic.

NOTE: A convenient way to create additional empty symbol fields is to use define field name templates. Field name templates define empty fields that are added to each symbol when it is inserted into the schematic. Field name templates can be defined globally (for all schematics) in the Schematic Editor Preferences, or they can be defined locally (specific to each project) in the Schematic Setup dialog.

[[editing-symbol-fields]]
==== Editing Symbol Fields

To edit an existing symbol field, right-click on the field text to show the field context menu shown below.

image::images/de/eeschema_libedit_field_context_menu.png[alt="Symbol field context menu", scaledwidth="35%"]

To add new fields, delete optional fields, or edit existing fields, use the image:images/icons/part_properties_24.png[Component properties icon] icon on the main tool bar to open the <<symbol-properties,Symbol Properties dialog>>.

Fields are text information associated a the symbol. Do not confuse them with text in the graphic representation of a symbol.

Wichtige Hinweise:

* Modifying the `Value` field changes the name of the symbol. The symbol's name in the library will change when the symbol is saved.
* The Symbol Properties dialog must be used to edit a field that is empty or has the invisible attribute enabled because such fields cannot be clicked on.
* The footprint is defined as an absolute footprint using the `LIBNAME:FOOTPRINTNAME` format where `LIBNAME` is the name of the footprint library defined in the footprint library table (see the "Footprint Library Table" section in the PCB Editor manual) and `FOOTPRINTNAME` is the name of the footprint in the library `LIBNAME`.

[[creating-power-ports]]
=== Power Ports

Power ports, or power symbols, are conventionally used to label a wire as part of a power net, like `VCC`, `+5V`, or `GND`. In the schematic below, the `+3.3V` and `GND` symbols are power ports. In addition to acting as a visual indicator that a net is a power rail, a power port will determine the name of the net it is attached to. This is true even if there is another net label attached to the net; the net name determined by the power symbol overrides any other net names.

image::images/eeschema_power_port_example.png[alt="Power port example", scaledwidth="60%"]

It may be useful to place power symbols in a dedicated library. KiCad's symbol library places power symbols in the `power` library, and users may create libraries to store their own power symbols. If the "Define as power symbol" box is checked in a symbol's properties, that symbol will appear in the Schematic Editor's "Add Power Port" dialog for convenient access.

Power symbols are handled and created the same way as normal symbols, but there are several additional considerations described below. They consist of a graphical symbol and a pin of the type "Power input" that is marked hidden.

Below is an example of a `GND` power symbol.

image::images/de/eeschema_libedit_power_symbol.png[alt="Editing a power symbol", scaledwidth="95%"]

==== Creating a Power Port Symbol

Power Port symbols consist of a pin of type "Power input" that is marked invisible. Invisible power input pins have a special property of automatically connecting to a net with the same name as the pin name. A net that is wired to an invisible power input pin will therefore be named after the pin, even if there are other net labels on the net. This connection is global.

NOTE: If the power symbol has the "Define as power symbol" property checked, the power input pin does not need to be marked invisible. However, the convention is to make these pins invisible anyway.

image::images/eeschema_libedit_power_symbol_pin.png[alt="Power symbol pin", scaledwidth="60%"]

Um ein Spannungsversorgungssymbol zu erstellen führen Sie folgende Schritte aus:

* Add a pin of type "Power input", with "Visible" unchecked, and the pin named according to the desired net. Make the pin number `1`, the length `0`, and set the graphic style to "Line". The pin name establishes the connection to the net; in this case the pin will automatically connect to the net `GND`. The pin number, length, and line style do not matter electrically.
* Place the pin on the symbol anchor.
* Use the shape tools to draw the symbol graphics.
* Set the symbol value. The symbol value does not matter electrically, but it is displayed in the schematic. To eliminate confusion, it should match the pin name (which determines the connected net name).
* Check the "Define as power symbol" box in Symbol Properties window. This makes the symbol appear in the "Add Power Port" dialog, makes the `Value` field read-only in the schematic, prevents the symbol from being assigned a footprint, and excludes the symbol from the board, BOM, and netlists.
* Set the symbol reference and uncheck the "Show" box. The reference text is not important except for the first character, which should be `\#`. For the power port shown above, the reference could be `#GND`. Symbols with references that begin with `#` are not added to the PCB, are not included in Bill of Materials exports or netlists, and they cannot be assigned a footprint in the footprint assignment tool. If a power port's reference does not begin with `#`, the character will be inserted automatically when the annotation or footprint assignment tools are run.

An easier method to create a new power port symbol is to use another symbol as a starting point, <<creating-a-symbol-from-another-symbol,as described earlier>>.

NOTE: When modifying an existing power port symbol, make sure to rename the pin name so that the new symbol connects to the appropriate power net.

:experimental:

[[viewlib]]
== Symbol Library Browser

=== Einleitung

The Symbol Library Browser allows you to quickly examine the content of symbol libraries. The Symbol Library Viewer can be accessed by clicking image:images/icons/library_browser_24.png[Library viewer icon] icon on the main toolbar, **View** -> **Symbol Library Browser...**, or clicking **Select With Browser** in the "Choose Symbol" window.

image::images/de/eeschema_viewlib_choose.png[alt="Bauteilfilter im Bauteilbrowser", scaledwidth="60%"]

[[viewlib---main-screen]]
=== Bibliotheksbrowser - Hauptfenster

image::images/de/eeschema_viewlib_select_library.png[alt="Bauteilbibliotheksbrowser ohne spezielle Auswahl", scaledwidth="95%"]

To examine the contents of a library, select a library from the list on the left hand pane. All symbols in the selected library will appear in the second pane. Select a symbol name to view the symbol.

image::images/de/eeschema_viewlib_select_component.png[alt="Bauteileditor mit ausgewähltem Bauteil", scaledwidth="95%"]

[[viewlib-top-toolbar]]
=== Symbol Library Browser Top Toolbar

The top tool bar in Symbol Library Brower is shown below.

image::images/de/toolbar_viewlib.png[alt="images/de/toolbar_viewlib.png", scaledwidth="95%"]

Die möglichen Befehle sind:

[width="100%", cols="20%,80%"]
|=======================================================================
|image:images/icons/library_browser_24.png[Symbol selection icon]
|Selection of the symbol which can be also selected in the displayed
list.

|image:images/icons/lib_previous_24.png[Previous symbol icon]
|Display previous symbol.

|image:images/icons/lib_next_24.png[Next symbol icon]
|Display next symbol.

|image:images/icons/refresh_24.png[] image:images/icons/zoom_in_24.png[]
image:images/icons/zoom_out_24.png[] image:images/icons/zoom_fit_in_page_24.png[]
|Zoom tools.

|image:images/icons/morgan1_24.png[] image:images/icons/morgan2_24.png[]
|Selection of the representation (normal or alternate) if an alternate
representation exists.

|image:images/toolbar_viewlib_part.png[alt="images/toolbar_viewlib_part.png",width="70%"]
|Selection of the unit for symbols that contain multiple units.

|image:images/icons/datasheet_24.png[icons/datasheet_png]
|If they exist, display the associated documents.

|image:images/icons/add_symbol_to_schematic_24.png[Add symbol to schematic icon]
|Close the browser and place the selected symbol in the schematic.
|=======================================================================

:experimental:

[[create-a-netlist]]
== Eine Netzliste erzeugen

=== Überblick

A netlist is a file which describes electrical connections between symbol pins. These connections are referred to as nets. Netlist files contain:

* A list of symbols and their pins.
* A list of connections (nets) between symbol pins.

Many different netlist formats exist. Sometimes the symbols list and the list of nets are two separate files. This netlist is fundamental in the use of schematic capture software, because the netlist is the link with other electronic CAD software, such as:

* PCB layout software.
* Schematic and electrical signal simulators.
* Programmable logic (FPGA, CPLD, etc.) compilers.

KiCad supports several netlist formats:

* KiCad format, which can be imported by the KiCad PCB Editor. However, the <<eeschema_schematic_to_pcb.adoc#schematic-to-pcb,"Update PCB from Schematic">> tool should be used instead of importing a KiCad netlist into the PCB editor.
* OrCAD PCB2 format, for designing PCBs with OrCAD.
* CADSTAR format, for designing PCBs with CADSTAR.
* Spice format, for use with various external circuit simulators.

NOTE: In KiCad version 5.0 and later, it is not necessary to create a netlist for transferring a design from the schematic editor to the PCB editor. Instead, use the <<eeschema_schematic_to_pcb.adoc#schematic-to-pcb,"Update PCB from Schematic">> tool.

[[netlist-formats]]
=== Netzlistenformate

Netlists are exported with the Export Netlist dialog (**File**->**Export**->**Netlist...**).

Several netlist formats are available, and are selectable with the tabs at the top of the window. Some netlist formats have options.

Clicking the **Export Netlist** button prompts for a netlist filename and saves the netlist.

[NOTE]
Netlist generation can take up to several minutes for large schematics.

Custom generators can be added by clicking the **Add Generator...** button. Custom generators are external tools that are called by KiCad, for example Python scripts or XSLT stylesheets. For more information on custom netlist generators, see <<adding-new-netlist-generators,the section on adding custom netlist generators>>.

==== KiCad Netlist Format

image::images/eeschema_netlist_dialog_kicad.png[alt="KiCad netlist export", scaledwidth="70%"]

The KiCad netlist exporter does not have any options.

NOTE: In KiCad version 5.0 and later, it is not necessary to create a netlist for transferring a design from the schematic editor to the PCB editor. Instead, use the <<eeschema_schematic_to_pcb.adoc#schematic-to-pcb,"Update PCB from Schematic">> tool.

==== OrCAD PCB2 Netlist Format

image::images/eeschema_netlist_dialog_orcad.png[alt="OrCAD netlist export", scaledwidth="70%"]

The OrCAD netlist exporter does not have any options.

==== CADSTAR Netlist Format

image::images/eeschema_netlist_dialog_cadstar.png[alt="CADSTAR netlist export", scaledwidth="70%"]

The CADSTAR netlist exporter does not have any options.

==== Spice Netlist Format

image::images/de/eeschema_netlist_dialog_spice.png[alt="Spice netlist export", scaledwidth="70%"]

The Spice netlist format offers several options.

When the *Reformat passive symbol values* box is checked, passive symbol values will be adjusted to be compatible with Spice. Specifically:

* `&mu;` and `M` as unit prefixes are replaced with `u` and `Meg`, respectively
* Units are removed (e.g. `4.7k&ohm;` is changed to `4.7k`)
* Values in RKM format are rewritten to be Spice-compatible (e.g. `4u7` is changed to `4.7u`)

The Spice netlist exporter also provides an easy way to simulate the generated netlist with an external simulator. This can be useful for running a simulation without using <<eeschema_simulator.adoc#simulator,KiCad's internal ngspice simulator>>, or for running an ngspice simulation with options that are not supported by KiCad's simulator tool.

Enter the path to the external simulator in the text box, with `%I` representing the generated netlist. Click the **Create Netlist and Run Simulator Command** button to generate the netlist and automatically run the simulator.

NOTE: The default simulator command (`spice "%I"`) must be adjusted to point to a simulator installed on your system.

For more information on the contents of Spice netlists, see the <<spice-netlists,Spice netlist section>>.

[[netlist-examples]]
=== Beispiele für Netzlisten

Below is the schematic from the `sallen_key` project included in KiCad's simulation demos.

image::images/eeschema_netlist_schematic.png[alt="sallen_key demo schematic", scaledwidth="95%"]

The KiCad format netlist for this schematic is as follows:

----
(export (version "E")
  (design
    (source "/usr/share/kicad/demos/simulation/sallen_key/sallen_key.kicad_sch")
    (date "Sun 01 May 2022 03:14:05 PM EDT")
    (tool "Eeschema (6.0.4)")
    (sheet (number "1") (name "/") (tstamps "/")
      (title_block
        (title)
        (company)
        (rev)
        (date)
        (source "sallen_key.kicad_sch")
        (comment (number "1") (value ""))
        (comment (number "2") (value ""))
        (comment (number "3") (value ""))
        (comment (number "4") (value ""))
        (comment (number "5") (value ""))
        (comment (number "6") (value ""))
        (comment (number "7") (value ""))
        (comment (number "8") (value ""))
        (comment (number "9") (value "")))))
  (components
    (comp (ref "C1")
      (value "100n")
      (libsource (lib "sallen_key_schlib") (part "C") (description ""))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-00005789077d"))
    (comp (ref "C2")
      (value "100n")
      (fields
        (field (name "Fieldname") "Value")
        (field (name "SpiceMapping") "1 2")
        (field (name "Spice_Primitive") "C"))
      (libsource (lib "sallen_key_schlib") (part "C") (description ""))
      (property (name "Fieldname") (value "Value"))
      (property (name "Spice_Primitive") (value "C"))
      (property (name "SpiceMapping") (value "1 2"))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-00005789085b"))
    (comp (ref "R1")
      (value "1k")
      (fields
        (field (name "Fieldname") "Value")
        (field (name "SpiceMapping") "1 2")
        (field (name "Spice_Primitive") "R"))
      (libsource (lib "sallen_key_schlib") (part "R") (description ""))
      (property (name "Fieldname") (value "Value"))
      (property (name "SpiceMapping") (value "1 2"))
      (property (name "Spice_Primitive") (value "R"))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-0000578906ff"))
    (comp (ref "R2")
      (value "1k")
      (fields
        (field (name "Fieldname") "Value")
        (field (name "SpiceMapping") "1 2")
        (field (name "Spice_Primitive") "R"))
      (libsource (lib "sallen_key_schlib") (part "R") (description ""))
      (property (name "Fieldname") (value "Value"))
      (property (name "SpiceMapping") (value "1 2"))
      (property (name "Spice_Primitive") (value "R"))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-000057890691"))
    (comp (ref "U1")
      (value "AD8051")
      (fields
        (field (name "Spice_Lib_File") "ad8051.lib")
        (field (name "Spice_Model") "AD8051")
        (field (name "Spice_Netlist_Enabled") "Y")
        (field (name "Spice_Primitive") "X"))
      (libsource (lib "sallen_key_schlib") (part "Generic_Opamp") (description ""))
      (property (name "Spice_Primitive") (value "X"))
      (property (name "Spice_Model") (value "AD8051"))
      (property (name "Spice_Lib_File") (value "ad8051.lib"))
      (property (name "Spice_Netlist_Enabled") (value "Y"))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-00005788ff9f"))
    (comp (ref "V1")
      (value "AC 1")
      (libsource (lib "sallen_key_schlib") (part "VSOURCE") (description ""))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-000057336052"))
    (comp (ref "V2")
      (value "DC 10")
      (fields
        (field (name "Fieldname") "Value")
        (field (name "Spice_Node_Sequence") "1 2")
        (field (name "Spice_Primitive") "V"))
      (libsource (lib "sallen_key_schlib") (part "VSOURCE") (description ""))
      (property (name "Fieldname") (value "Value"))
      (property (name "Spice_Primitive") (value "V"))
      (property (name "Spice_Node_Sequence") (value "1 2"))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-0000578900ba"))
    (comp (ref "V3")
      (value "DC 10")
      (fields
        (field (name "Fieldname") "Value")
        (field (name "Spice_Node_Sequence") "1 2")
        (field (name "Spice_Primitive") "V"))
      (libsource (lib "sallen_key_schlib") (part "VSOURCE") (description ""))
      (property (name "Fieldname") (value "Value"))
      (property (name "Spice_Primitive") (value "V"))
      (property (name "Spice_Node_Sequence") (value "1 2"))
      (property (name "Sheetname") (value ""))
      (property (name "Sheetfile") (value "sallen_key.kicad_sch"))
      (sheetpath (names "/") (tstamps "/"))
      (tstamps "00000000-0000-0000-0000-000057890232")))
  (libparts
    (libpart (lib "sallen_key_schlib") (part "C")
      (footprints
        (fp "C?")
        (fp "C_????_*")
        (fp "C_????")
        (fp "SMD*_c")
        (fp "Capacitor*"))
      (fields
        (field (name "Reference") "C")
        (field (name "Value") "C"))
      (pins
        (pin (num "1") (name "") (type "passive"))
        (pin (num "2") (name "") (type "passive"))))
    (libpart (lib "sallen_key_schlib") (part "Generic_Opamp")
      (fields
        (field (name "Reference") "U")
        (field (name "Value") "Generic_Opamp"))
      (pins
        (pin (num "1") (name "+") (type "input"))
        (pin (num "2") (name "-") (type "input"))
        (pin (num "3") (name "V+") (type "power_in"))
        (pin (num "4") (name "V-") (type "power_in"))
        (pin (num "5") (name "") (type "output"))))
    (libpart (lib "sallen_key_schlib") (part "R")
      (footprints
        (fp "R_*")
        (fp "Resistor_*"))
      (fields
        (field (name "Reference") "R")
        (field (name "Value") "R"))
      (pins
        (pin (num "1") (name "") (type "passive"))
        (pin (num "2") (name "") (type "passive"))))
    (libpart (lib "sallen_key_schlib") (part "VSOURCE")
      (fields
        (field (name "Reference") "V")
        (field (name "Value") "VSOURCE")
        (field (name "Fieldname") "Value")
        (field (name "Spice_Primitive") "V")
        (field (name "Spice_Node_Sequence") "1 2"))
      (pins
        (pin (num "1") (name "") (type "input"))
        (pin (num "2") (name "") (type "input")))))
  (libraries
    (library (logical "sallen_key_schlib")
      (uri "/usr/share/kicad/demos/simulation/sallen_key/sallen_key_schlib.kicad_sym")))
  (nets
    (net (code "1") (name "/lowpass")
      (node (ref "C1") (pin "1") (pintype "passive"))
      (node (ref "U1") (pin "2") (pinfunction "-") (pintype "input"))
      (node (ref "U1") (pin "5") (pintype "output")))
    (net (code "2") (name "GND")
      (node (ref "C2") (pin "2") (pintype "passive"))
      (node (ref "V1") (pin "2") (pintype "input"))
      (node (ref "V2") (pin "2") (pintype "input"))
      (node (ref "V3") (pin "1") (pintype "input")))
    (net (code "3") (name "Net-(C1-Pad2)")
      (node (ref "C1") (pin "2") (pintype "passive"))
      (node (ref "R1") (pin "1") (pintype "passive"))
      (node (ref "R2") (pin "2") (pintype "passive")))
    (net (code "4") (name "Net-(C2-Pad1)")
      (node (ref "C2") (pin "1") (pintype "passive"))
      (node (ref "R2") (pin "1") (pintype "passive"))
      (node (ref "U1") (pin "1") (pinfunction "+") (pintype "input")))
    (net (code "5") (name "Net-(R1-Pad2)")
      (node (ref "R1") (pin "2") (pintype "passive"))
      (node (ref "V1") (pin "1") (pintype "input")))
    (net (code "6") (name "VDD")
      (node (ref "U1") (pin "3") (pinfunction "V+") (pintype "power_in"))
      (node (ref "V2") (pin "1") (pintype "input")))
    (net (code "7") (name "VSS")
      (node (ref "U1") (pin "4") (pinfunction "V-") (pintype "power_in"))
      (node (ref "V3") (pin "2") (pintype "input")))))
----

In Spice format, the netlist is as follows:

----
.title KiCad schematic
.include "ad8051.lib"
XU1 Net-_C2-Pad1_ /lowpass VDD VSS /lowpass AD8051
C2 Net-_C2-Pad1_ GND 100n
C1 /lowpass Net-_C1-Pad2_ 100n
R2 Net-_C2-Pad1_ Net-_C1-Pad2_ 1k
R1 Net-_C1-Pad2_ Net-_R1-Pad2_ 1k
V1 Net-_R1-Pad2_ GND AC 1
V2 VDD GND DC 10
V3 GND VSS DC 10
.ac dec 10 1 1Meg
.end
----


[[notes-on-netlists]]
=== Anmerkungen zu Netzlisten

[[netlist-name-precautions]]
==== Zu beachtende Punkte für die Benennung von Netzlisten

Many software tools that use netlists do not accept spaces in component names, pins, nets, or other fields. Avoid using spaces in pins, labels, names, and value fields of components to ensure maximum compatibility.

In the same way, special characters other than letters and numbers can cause problems. Note that this limitation is not related to KiCad, but to the netlist formats that can then become untranslatable by other software that reads those netlist files.

[[spice-netlists]]
==== Spice netlists

Spice simulators expect simulation commands (`.PROBE`, `.AC`, `.TRAN`, etc.) to be included in the netlist.

Any text line included in the schematic diagram starting with a period (`.`) will be included in the netlist. If a text object contains multiple lines, only the lines beginning with a period will be included.

`.include` directives for including model library files are automatically added to the netlist based on the Spice model settings for the symbols in the schematic.

[[other-formats]]
=== Andere Formate

KiCad supports custom netlist generators for exporting netlists in other formats. Some examples of netlist generators are given in the <<eeschema_creating_customized_netlists_and_bom_files.adoc#creating-customized-netlists-and-bom-files,custom netlist generators section>>.

A netlist generator is a script or program that converts the intermediate netlist file created by KiCad into the desired netlist format. The intermediate netlist file contains all of the netlist information required to create an arbitrary netlist for the schematic. Python and XSLT are commonly used tools to create custom netlist generators.

[[adding-new-netlist-generators]]
==== Adding new netlist generators

New netlist generators are added by clicking the **Add Generator...** button.

image::images/de/eeschema_netlist_dialog_add_plugin.png[alt="Custom Netlist Generator", scaledwidth="40%"]

New generators require a name and a command. The name is shown in the tab label, and the command is run whenever the **Export Netlist** button is clicked.

When the netlist is generated, KiCad creates an intermediate XML file which contains all of the netlist information from the schematic. The generator command is then run in order to transform the intermediate netlist into the desired netlist format.

The netlist command must be set up properly so that the netlist generator script takes the intermediate netlist file as input and outputs the desired netlist file. The `%I` argument represents the input intermediate netlist filename and the `%O` argument represents the output netlist filename. The exact netlist command will depend on the generator script used.

[[command-line-format]]
==== Befehlszeilenformat

Consider the following example which uses `xsltproc` to generate a netlist in PADS ASC format. `xsltproc` converts the intermediate netlist using the `netlist_form_pads-pcb.asc.xsl` stylesheet to define the output format:

`xsltproc -o %O.net /usr/share/kicad/plugins/netlist_form_pads-pcb.asc.xsl %I`

The purpose of each part of the command is as follows:

[width="100%", cols="58%,42%"]
|=======================================================================
|`xsltproc` |A tool to convert an XML file (the intermediate netlist) according
to an XSLT stylesheet.

|`-o %O.net` |Output filename. `%O` is replaced with the name of the
intermediate netlist file, which is `<schematic name>.xml`. Therefore in this
example the complete output filename is `<schematic name>.xml.net`. An arbitrary
output filename can be specified if desired with `-o <filename>`.

|`/usr/share/kicad/plugins/netlist_form_pads-pcb.asc.xsl` |XSLT stylesheet which
determines how the output is formatted. This particular stylesheet is included
with KiCad, but custom stylesheets can also be created.

|`%I` |Input (intermediate netlist) filename. `%I` is replaced with the name of
the intermediate netlist file, which is `<schematic name>.xml`.
|=======================================================================

For netlist generators that do not use `xsltproc`, the generator command will differ.

[[intermediate-netlist-file-format]]
==== Dateiformat der Zwischen-Netzliste

See the <<eeschema_creating_customized_netlists_and_bom_files.adoc#creating-customized-netlists-and-bom-files,custom netlist generators section>> for more information about netlist generators, a description of the intermediate netlist format, and some examples of netlist generators.

:experimental:

[[creating-customized-netlists-and-bom-files]]
== Erstellen angepasster Dateien für Netzlisten und Stücklisten

[[intermediate-netlist-file]]
=== Zwischenzeitliche Netzlistendatei

BOM files and netlist files can be converted from an Intermediate netlist file created by KiCad.

Diese Datei benutzt XML Syntax und wird "zwischenzeitliche Netzliste" genannt. Die Zwischennetzliste enthält eine große Menge von Daten über Ihre Leiterplatte und aufgrund dessen kann sie dafür genutzt werden, eine Stückliste und andere Berichte zu erstellen.

Abhängig von der Ausgabe (Stückliste oder Netzliste) werden unterschiedliche Untermengen der kompletten Zwischennetzlistendatei für die Nachbearbeitung verwendet.

[[schematic-sample]]
==== Schaltplanbeispiel

image::images/schematic-sample.png[width="70%"][alt="Schaltplanbeispiel", scaledwidth="95%"]

[[the-intermediate-netlist-file-sample]]
==== Dateibeispiel der Zwischennetzliste

Die korrespondierende Zwischennetzliste (als XML-Datei) des Schaltkreises ist unten zu sehen.

-----------------------------------------------------------------
<?xml version="1.0" encoding="utf-8"?>
<export version="D">
  <design>
    <source>F:\kicad_aux\netlist_test\netlist_test.sch</source>
    <date>29/08/2010 20:35:21</date>
    <tool>eeschema (2010-08-28 BZR 2458)-unstable</tool>
  </design>
  <components>
    <comp ref="P1">
      <value>CONN_4</value>
      <libsource lib="conn" part="CONN_4"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E2141</tstamp>
    </comp>
    <comp ref="U2">
      <value>74LS74</value>
      <libsource lib="74xx" part="74LS74"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E20BA</tstamp>
    </comp>
    <comp ref="U1">
      <value>74LS04</value>
      <libsource lib="74xx" part="74LS04"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E20A6</tstamp>
    </comp>
    <comp ref="C1">
      <value>CP</value>
      <libsource lib="device" part="CP"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E2094</tstamp>
    </comp>
    <comp ref="R1">
      <value>R</value>
      <libsource lib="device" part="R"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E208A</tstamp>
    </comp>
  </components>
  <libparts>
    <libpart lib="device" part="C">
      <description>Condensateur non polarise</description>
      <footprints>
        <fp>SM*</fp>
        <fp>C?</fp>
        <fp>C1-1</fp>
      </footprints>
      <fields>
        <field name="Reference">C</field>
        <field name="Value">C</field>
      </fields>
      <pins>
        <pin num="1" name="~" type="passive"/>
        <pin num="2" name="~" type="passive"/>
      </pins>
    </libpart>
    <libpart lib="device" part="R">
      <description>Resistance</description>
      <footprints>
        <fp>R?</fp>
        <fp>SM0603</fp>
        <fp>SM0805</fp>
        <fp>R?-*</fp>
        <fp>SM1206</fp>
      </footprints>
      <fields>
        <field name="Reference">R</field>
        <field name="Value">R</field>
      </fields>
      <pins>
        <pin num="1" name="~" type="passive"/>
        <pin num="2" name="~" type="passive"/>
      </pins>
    </libpart>
    <libpart lib="conn" part="CONN_4">
      <description>Symbole general de connecteur</description>
      <fields>
        <field name="Reference">P</field>
        <field name="Value">CONN_4</field>
      </fields>
      <pins>
        <pin num="1" name="P1" type="passive"/>
        <pin num="2" name="P2" type="passive"/>
        <pin num="3" name="P3" type="passive"/>
        <pin num="4" name="P4" type="passive"/>
      </pins>
    </libpart>
    <libpart lib="74xx" part="74LS04">
      <description>Hex Inverseur</description>
      <fields>
        <field name="Reference">U</field>
        <field name="Value">74LS04</field>
      </fields>
      <pins>
        <pin num="1" name="~" type="input"/>
        <pin num="2" name="~" type="output"/>
        <pin num="3" name="~" type="input"/>
        <pin num="4" name="~" type="output"/>
        <pin num="5" name="~" type="input"/>
        <pin num="6" name="~" type="output"/>
        <pin num="7" name="GND" type="power_in"/>
        <pin num="8" name="~" type="output"/>
        <pin num="9" name="~" type="input"/>
        <pin num="10" name="~" type="output"/>
        <pin num="11" name="~" type="input"/>
        <pin num="12" name="~" type="output"/>
        <pin num="13" name="~" type="input"/>
        <pin num="14" name="VCC" type="power_in"/>
      </pins>
    </libpart>
    <libpart lib="74xx" part="74LS74">
      <description>Dual D FlipFlop, Set &amp; Reset</description>
      <docs>74xx/74hc_hct74.pdf</docs>
      <fields>
        <field name="Reference">U</field>
        <field name="Value">74LS74</field>
      </fields>
      <pins>
        <pin num="1" name="Cd" type="input"/>
        <pin num="2" name="D" type="input"/>
        <pin num="3" name="Cp" type="input"/>
        <pin num="4" name="Sd" type="input"/>
        <pin num="5" name="Q" type="output"/>
        <pin num="6" name="~Q" type="output"/>
        <pin num="7" name="GND" type="power_in"/>
        <pin num="8" name="~Q" type="output"/>
        <pin num="9" name="Q" type="output"/>
        <pin num="10" name="Sd" type="input"/>
        <pin num="11" name="Cp" type="input"/>
        <pin num="12" name="D" type="input"/>
        <pin num="13" name="Cd" type="input"/>
        <pin num="14" name="VCC" type="power_in"/>
      </pins>
    </libpart>
  </libparts>
  <libraries>
    <library logical="device">
      <uri>F:\kicad\share\library\device.lib</uri>
    </library>
    <library logical="conn">
      <uri>F:\kicad\share\library\conn.lib</uri>
    </library>
    <library logical="74xx">
      <uri>F:\kicad\share\library\74xx.lib</uri>
    </library>
  </libraries>
  <nets>
    <net code="1" name="GND">
      <node ref="U1" pin="7"/>
      <node ref="C1" pin="2"/>
      <node ref="U2" pin="7"/>
      <node ref="P1" pin="4"/>
    </net>
    <net code="2" name="VCC">
      <node ref="R1" pin="1"/>
      <node ref="U1" pin="14"/>
      <node ref="U2" pin="4"/>
      <node ref="U2" pin="1"/>
      <node ref="U2" pin="14"/>
      <node ref="P1" pin="1"/>
    </net>
    <net code="3" name="">
      <node ref="U2" pin="6"/>
    </net>
    <net code="4" name="">
      <node ref="U1" pin="2"/>
      <node ref="U2" pin="3"/>
    </net>
    <net code="5" name="/SIG_OUT">
      <node ref="P1" pin="2"/>
      <node ref="U2" pin="5"/>
      <node ref="U2" pin="2"/>
    </net>
    <net code="6" name="/CLOCK_IN">
      <node ref="R1" pin="2"/>
      <node ref="C1" pin="1"/>
      <node ref="U1" pin="1"/>
      <node ref="P1" pin="3"/>
    </net>
  </nets>
</export>
-----------------------------------------------------------------

[[conversion-to-a-new-netlist-format]]
=== Umwandlung in ein neues Netzlistenformat

Unter Anwendung eines Nachtbearbeitungsfilters auf die Zwischennetzlistendatei können Sie fremde Netzlistenformate und auch Stücklisten erzeugen. Weil diese Umwandlung eine Text zu Text Umwandlung ist, kann dieser Nachtbearbeitungsfilter in Python, XSLT oder jedem anderen Werkzeug geschrieben werden, das XML als Eingabe verarbeiten kann.

XSLT itself is an XML language very suitable for XML transformations. There is a free program called _xsltproc_ that you can download and install. The xsltproc program can be used to read the Intermediate XML netlist input file, apply a style-sheet to transform the input, and save the results in an output file. Use of xsltproc requires a style-sheet file using XSLT conventions. The full conversion process is handled by KiCad, after it is configured once to run xsltproc in a specific way.

[[xslt-approach]]
=== XSLT-Vorgehensweise

Das Dokument, das die XSL-Umwandlung (XSLT) beschreibt, gibt es unter:

*http://www.w3.org/TR/xslt*

[[create-a-pads-pcb-netlist-file]]
==== Erstellen einer PadsPcb Netzlistendatei

Das PadsPcb Format besteht aus zwei Teilen.

* Die Footprintliste.

* Die Netzeliste: Gruppiert Referenzen der Pads nach Netzen.

Direkt unten ist ein Stylesheet welches die Zwischennetzlistendatei in ein PadsPcb Netzlistenformat umwandelt:

-------------------------------------------------------------------------------
<?xml version="1.0" encoding="ISO-8859-1"?>
<!--XSL style sheet to Eeschema Generic Netlist Format to PADS netlist format
    Copyright (C) 2010, SoftPLC Corporation.
    GPL v2.

    How to use:
        https://lists.launchpad.net/kicad-developers/msg05157.html
-->

<!DOCTYPE xsl:stylesheet [
  <!ENTITY nl  "&#xd;&#xa;"> <!--new line CR, LF -->
]>

<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform">
<xsl:output method="text" omit-xml-declaration="yes" indent="no"/>

<xsl:template match="/export">
    <xsl:text>*PADS-PCB*&nl;*PART*&nl;</xsl:text>
    <xsl:apply-templates select="components/comp"/>
    <xsl:text>&nl;*NET*&nl;</xsl:text>
    <xsl:apply-templates select="nets/net"/>
    <xsl:text>*END*&nl;</xsl:text>
</xsl:template>

<!-- for each component -->
<xsl:template match="comp">
    <xsl:text> </xsl:text>
    <xsl:value-of select="@ref"/>
    <xsl:text> </xsl:text>
    <xsl:choose>
        <xsl:when test = "footprint != '' ">
            <xsl:apply-templates select="footprint"/>
        </xsl:when>
        <xsl:otherwise>
            <xsl:text>unknown</xsl:text>
        </xsl:otherwise>
    </xsl:choose>
    <xsl:text>&nl;</xsl:text>
</xsl:template>

<!-- for each net -->
<xsl:template match="net">
    <!-- nets are output only if there is more than one pin in net -->
    <xsl:if test="count(node)>1">
        <xsl:text>*SIGNAL* </xsl:text>
        <xsl:choose>
            <xsl:when test = "@name != '' ">
                <xsl:value-of select="@name"/>
            </xsl:when>
            <xsl:otherwise>
                <xsl:text>N-</xsl:text>
                <xsl:value-of select="@code"/>
            </xsl:otherwise>
        </xsl:choose>
        <xsl:text>&nl;</xsl:text>
        <xsl:apply-templates select="node"/>
    </xsl:if>
</xsl:template>

<!-- for each node -->
<xsl:template match="node">
    <xsl:text> </xsl:text>
    <xsl:value-of select="@ref"/>
    <xsl:text>.</xsl:text>
    <xsl:value-of select="@pin"/>
    <xsl:text>&nl;</xsl:text>
</xsl:template>

</xsl:stylesheet>
-------------------------------------------------------------------------------

Und dies ist die PadsPcb Ausgabe nach dem Durchlauf von xsltproc:

------------------
*PADS-PCB*
*PART*
P1 unknown
U2 unknown
U1 unknown
C1 unknown
R1 unknown
*NET*
*SIGNAL* GND
U1.7
C1.2
U2.7
P1.4
*SIGNAL* VCC
R1.1
U1.14
U2.4
U2.1
U2.14
P1.1
*SIGNAL* N-4
U1.2
U2.3
*SIGNAL* /SIG_OUT
P1.2
U2.5
U2.2
*SIGNAL* /CLOCK_IN
R1.2
C1.1
U1.1
P1.3

*END*
------------------

Die Befehlszeile um diese Umwandlung durchzuführen lautet:

-------------------------------------------
kicad\\bin\\xsltproc.exe -o test.net kicad\\bin\\plugins\\netlist_form_pads-pcb.xsl test.tmp
-------------------------------------------

[[create-a-cadstar-netlist-file]]
==== Eine Cadstar Netzlistendatei erstellen

Das Cadstarformat besteht aus zwei Teilen.

* Die Footprintliste.

* Die Netzeliste: Gruppiert Referenzen der Pads nach Netzen.

Hier ist die Stylesheet-Datei um diese spezielle Umwandlung durchzuführen.

-----
<?xml version="1.0" encoding="ISO-8859-1"?>
<!--XSL style sheet to Eeschema Generic Netlist Format to CADSTAR netlist format
    Copyright (C) 2010, Jean-Pierre Charras.
    Copyright (C) 2010, SoftPLC Corporation.
    GPL v2.

<!DOCTYPE xsl:stylesheet [
  <!ENTITY nl  "&#xd;&#xa;"> <!--new line CR, LF -->
]>

<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform">
<xsl:output method="text" omit-xml-declaration="yes" indent="no"/>

<!-- Netlist header -->
<xsl:template match="/export">
    <xsl:text>.HEA&nl;</xsl:text>
    <xsl:apply-templates select="design/date"/>  <!-- Generate line .TIM <time> -->
    <xsl:apply-templates select="design/tool"/>  <!-- Generate line .APP <eeschema version> -->
    <xsl:apply-templates select="components/comp"/>  <!-- Generate list of components -->
    <xsl:text>&nl;&nl;</xsl:text>
    <xsl:apply-templates select="nets/net"/>          <!-- Generate list of nets and connections -->
    <xsl:text>&nl;.END&nl;</xsl:text>
</xsl:template>

 <!-- Generate line .TIM 20/08/2010 10:45:33 -->
<xsl:template match="tool">
    <xsl:text>.APP "</xsl:text>
    <xsl:apply-templates/>
    <xsl:text>"&nl;</xsl:text>
</xsl:template>

 <!-- Generate line .APP "eeschema (2010-08-17 BZR 2450)-unstable" -->
<xsl:template match="date">
    <xsl:text>.TIM </xsl:text>
    <xsl:apply-templates/>
    <xsl:text>&nl;</xsl:text>
</xsl:template>

<!-- for each component -->
<xsl:template match="comp">
    <xsl:text>.ADD_COM </xsl:text>
    <xsl:value-of select="@ref"/>
    <xsl:text> </xsl:text>
    <xsl:choose>
        <xsl:when test = "value != '' ">
            <xsl:text>"</xsl:text> <xsl:apply-templates select="value"/> <xsl:text>"</xsl:text>
        </xsl:when>
        <xsl:otherwise>
            <xsl:text>""</xsl:text>
        </xsl:otherwise>
    </xsl:choose>
    <xsl:text>&nl;</xsl:text>
</xsl:template>

<!-- for each net -->
<xsl:template match="net">
    <!-- nets are output only if there is more than one pin in net -->
    <xsl:if test="count(node)>1">
    <xsl:variable name="netname">
        <xsl:text>"</xsl:text>
        <xsl:choose>
            <xsl:when test = "@name != '' ">
                <xsl:value-of select="@name"/>
            </xsl:when>
            <xsl:otherwise>
                <xsl:text>N-</xsl:text>
                <xsl:value-of select="@code"/>
        </xsl:otherwise>
        </xsl:choose>
        <xsl:text>"&nl;</xsl:text>
        </xsl:variable>
        <xsl:apply-templates select="node" mode="first"/>
        <xsl:value-of select="$netname"/>
        <xsl:apply-templates select="node" mode="others"/>
    </xsl:if>
</xsl:template>

<!-- for each node -->
<xsl:template match="node" mode="first">
    <xsl:if test="position()=1">
       <xsl:text>.ADD_TER </xsl:text>
    <xsl:value-of select="@ref"/>
    <xsl:text>.</xsl:text>
    <xsl:value-of select="@pin"/>
    <xsl:text> </xsl:text>
    </xsl:if>
</xsl:template>

<xsl:template match="node" mode="others">
    <xsl:choose>
        <xsl:when test='position()=1'>
        </xsl:when>
        <xsl:when test='position()=2'>
           <xsl:text>.TER     </xsl:text>
        </xsl:when>
        <xsl:otherwise>
           <xsl:text>         </xsl:text>
        </xsl:otherwise>
    </xsl:choose>
    <xsl:if test="position()>1">
        <xsl:value-of select="@ref"/>
        <xsl:text>.</xsl:text>
        <xsl:value-of select="@pin"/>
        <xsl:text>&nl;</xsl:text>
    </xsl:if>
</xsl:template>

</xsl:stylesheet>
-----

Hier ist die Cadstar Ausgabedatei.

-----
.HEA
.TIM 21/08/2010 08:12:08
.APP "eeschema (2010-08-09 BZR 2439)-unstable"
.ADD_COM P1 "CONN_4"
.ADD_COM U2 "74LS74"
.ADD_COM U1 "74LS04"
.ADD_COM C1 "CP"
.ADD_COM R1 "R"


.ADD_TER U1.7 "GND"
.TER     C1.2
         U2.7
         P1.4
.ADD_TER R1.1 "VCC"
.TER     U1.14
         U2.4
         U2.1
         U2.14
         P1.1
.ADD_TER U1.2 "N-4"
.TER     U2.3
.ADD_TER P1.2 "/SIG_OUT"
.TER     U2.5
         U2.2
.ADD_TER R1.2 "/CLOCK_IN"
.TER     C1.1
         U1.1
         P1.3

.END
-----

[[create-a-orcadpcb2-netlist-file]]
==== Eine OrcadPCB2 Netzlistendatei erstellen

Dieses Format hat nur einen Teil, die Footprintliste. Jeder Footprint enthält selbst seine Liste von Pads mit einer Referenz zu einem Netz.

Hier ist das Stylesheet für diese spezielle Umwandlung:

-----
<?xml version="1.0" encoding="ISO-8859-1"?>
<!--XSL style sheet to Eeschema Generic Netlist Format to CADSTAR netlist format
    Copyright (C) 2010, SoftPLC Corporation.
    GPL v2.

    How to use:
        https://lists.launchpad.net/kicad-developers/msg05157.html
-->

<!DOCTYPE xsl:stylesheet [
  <!ENTITY nl  "&#xd;&#xa;"> <!--new line CR, LF -->
]>

<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform">
<xsl:output method="text" omit-xml-declaration="yes" indent="no"/>

<!--
    Netlist header
    Creates the entire netlist
    (can be seen as equivalent to main function in C
-->
<xsl:template match="/export">
    <xsl:text>( { Eeschema Netlist Version 1.1  </xsl:text>
    <!-- Generate line .TIM <time> -->
<xsl:apply-templates select="design/date"/>
<!-- Generate line eeschema version ... -->
<xsl:apply-templates select="design/tool"/>
<xsl:text>}&nl;</xsl:text>

<!-- Generate the list of components -->
<xsl:apply-templates select="components/comp"/>  <!-- Generate list of components -->

<!-- end of file -->
<xsl:text>)&nl;*&nl;</xsl:text>
</xsl:template>

<!--
    Generate id in header like "eeschema (2010-08-17 BZR 2450)-unstable"
-->
<xsl:template match="tool">
    <xsl:apply-templates/>
</xsl:template>

<!--
    Generate date in header like "20/08/2010 10:45:33"
-->
<xsl:template match="date">
    <xsl:apply-templates/>
    <xsl:text>&nl;</xsl:text>
</xsl:template>

<!--
    This template read each component
    (path = /export/components/comp)
    creates lines:
     ( 3EBF7DBD $noname U1 74LS125
      ... pin list ...
      )
    and calls "create_pin_list" template to build the pin list
-->
<xsl:template match="comp">
    <xsl:text> ( </xsl:text>
    <xsl:choose>
        <xsl:when test = "tstamp != '' ">
            <xsl:apply-templates select="tstamp"/>
        </xsl:when>
        <xsl:otherwise>
            <xsl:text>00000000</xsl:text>
        </xsl:otherwise>
    </xsl:choose>
    <xsl:text> </xsl:text>
    <xsl:choose>
        <xsl:when test = "footprint != '' ">
            <xsl:apply-templates select="footprint"/>
        </xsl:when>
        <xsl:otherwise>
            <xsl:text>$noname</xsl:text>
        </xsl:otherwise>
    </xsl:choose>
    <xsl:text> </xsl:text>
    <xsl:value-of select="@ref"/>
    <xsl:text> </xsl:text>
    <xsl:choose>
        <xsl:when test = "value != '' ">
            <xsl:apply-templates select="value"/>
        </xsl:when>
        <xsl:otherwise>
            <xsl:text>"~"</xsl:text>
        </xsl:otherwise>
    </xsl:choose>
    <xsl:text>&nl;</xsl:text>
    <xsl:call-template name="Search_pin_list" >
        <xsl:with-param name="cmplib_id" select="libsource/@part"/>
        <xsl:with-param name="cmp_ref" select="@ref"/>
    </xsl:call-template>
    <xsl:text> )&nl;</xsl:text>
</xsl:template>

<!--
    This template search for a given lib component description in list
    lib component descriptions are in /export/libparts,
    and each description start at ./libpart
    We search here for the list of pins of the given component
    This template has 2 parameters:
        "cmplib_id" (reference in libparts)
        "cmp_ref"   (schematic reference of the given component)
-->
<xsl:template name="Search_pin_list" >
    <xsl:param name="cmplib_id" select="0" />
    <xsl:param name="cmp_ref" select="0" />
        <xsl:for-each select="/export/libparts/libpart">
            <xsl:if test = "@part = $cmplib_id ">
                <xsl:apply-templates name="build_pin_list" select="pins/pin">
                    <xsl:with-param name="cmp_ref" select="$cmp_ref"/>
                </xsl:apply-templates>
            </xsl:if>
        </xsl:for-each>
</xsl:template>


<!--
    This template writes the pin list of a component
    from the pin list of the library description
    The pin list from library description is something like
          <pins>
            <pin num="1" type="passive"/>
            <pin num="2" type="passive"/>
          </pins>
    Output pin list is ( <pin num> <net name> )
    something like
            ( 1 VCC )
            ( 2 GND )
-->
<xsl:template name="build_pin_list" match="pin">
    <xsl:param name="cmp_ref" select="0" />

    <!-- write pin numner and separator -->
    <xsl:text>  ( </xsl:text>
    <xsl:value-of select="@num"/>
    <xsl:text> </xsl:text>

    <!-- search net name in nets section and write it: -->
    <xsl:variable name="pinNum" select="@num" />
    <xsl:for-each select="/export/nets/net">
        <!-- net name is output only if there is more than one pin in net
             else use "?" as net name, so count items in this net
        -->
        <xsl:variable name="pinCnt" select="count(node)" />
        <xsl:apply-templates name="Search_pin_netname" select="node">
            <xsl:with-param name="cmp_ref" select="$cmp_ref"/>
            <xsl:with-param name="pin_cnt_in_net" select="$pinCnt"/>
            <xsl:with-param name="pin_num"> <xsl:value-of select="$pinNum"/>
            </xsl:with-param>
        </xsl:apply-templates>
    </xsl:for-each>

    <!-- close line -->
    <xsl:text> )&nl;</xsl:text>
</xsl:template>

<!--
    This template writes the pin netname of a given pin of a given component
    from the nets list
    The nets list description is something like
      <nets>
        <net code="1" name="GND">
          <node ref="J1" pin="20"/>
              <node ref="C2" pin="2"/>
        </net>
        <net code="2" name="">
          <node ref="U2" pin="11"/>
        </net>
    </nets>
    This template has 2 parameters:
        "cmp_ref"   (schematic reference of the given component)
        "pin_num"   (pin number)
-->

<xsl:template name="Search_pin_netname" match="node">
    <xsl:param name="cmp_ref" select="0" />
    <xsl:param name="pin_num" select="0" />
    <xsl:param name="pin_cnt_in_net" select="0" />

    <xsl:if test = "@ref = $cmp_ref ">
        <xsl:if test = "@pin = $pin_num">
        <!-- net name is output only if there is more than one pin in net
             else use "?" as net name
        -->
            <xsl:if test = "$pin_cnt_in_net>1">
                <xsl:choose>
                    <!-- if a net has a name, use it,
                        else build a name from its net code
                    -->
                    <xsl:when test = "../@name != '' ">
                        <xsl:value-of select="../@name"/>
                    </xsl:when>
                    <xsl:otherwise>
                        <xsl:text>$N-0</xsl:text><xsl:value-of select="../@code"/>
                    </xsl:otherwise>
                </xsl:choose>
            </xsl:if>
            <xsl:if test = "$pin_cnt_in_net &lt;2">
                <xsl:text>?</xsl:text>
            </xsl:if>
        </xsl:if>
    </xsl:if>

</xsl:template>

</xsl:stylesheet>
-----

Hier ist die OrcadPCB2 Ausgabedatei.

-----------------------------------------------------
( { Eeschema Netlist Version 1.1  29/08/2010 21:07:51
eeschema (2010-08-28 BZR 2458)-unstable}
 ( 4C6E2141 $noname P1 CONN_4
  (  1 VCC )
  (  2 /SIG_OUT )
  (  3 /CLOCK_IN )
  (  4 GND )
 )
 ( 4C6E20BA $noname U2 74LS74
  (  1 VCC )
  (  2 /SIG_OUT )
  (  3 N-04 )
  (  4 VCC )
  (  5 /SIG_OUT )
  (  6 ? )
  (  7 GND )
  (  14 VCC )
 )
 ( 4C6E20A6 $noname U1 74LS04
  (  1 /CLOCK_IN )
  (  2 N-04 )
  (  7 GND )
  (  14 VCC )
 )
 ( 4C6E2094 $noname C1 CP
  (  1 /CLOCK_IN )
  (  2 GND )
 )
 ( 4C6E208A $noname R1 R
  (  1 VCC )
  (  2 /CLOCK_IN )
 )
)
*
-----------------------------------------------------

[[eeschema-plugins-interface]]
==== Netlist plugins interface

Intermediate Netlist converters can be automatically launched within the Schematic Editor.

[[init-the-dialog-window-1]]
===== Das Dialogfenster aufrufen

Sie können ein neues Netzlisten-Plugin hinzufügen mit einem Klick auf "Plugin hinzufügen".

image::images/de/eeschema_netlist_dialog_add_plugin.png[alt="Auswahlbutton zum Einfügen von Plugins", scaledwidth="50%"]

So sehen die Konfigurationsdaten für das PadsPcb Plugin aus:

image::images/de/eeschema_netlist_dialog_padspcb.png[alt="Einstellungen des Plugins PadsPCB", scaledwidth="80%"]

[[plugin-configuration-parameters]]
===== Konfiguration der Plugin-Parameter

The netlist plug-in configuration dialog requires the following information:

* *Titel*: Zum Beispiel der Name des Netzlistenformats.

* *Netzliste Befehl*: Der Audruf um den Konverter zu starten.

Sobald Sie auf den Button _Erstellen_ drücken, wird folgendes passieren:

1.  KiCad creates an intermediate netlist file *.xml, for instance test.xml.

2.  KiCad runs the plug-in by reading test.xml and creates test.net.

[[generate-netlist-files-with-the-command-line]]
===== Netzlistendateien über die Befehlszeile erzeugen

Angenommen wir benutzen das Programm _xsltproc.exe_ um ein Stylesheet auf die zwischenzeitliche Netzlistendatei anzuwenden, dann wird _xsltproc.exe_ mit folgendem Befehl ausgeführt:

_xsltproc.exe -o <output filename> < style-sheet filename> <input XML file to convert>_

In KiCad unter Windows ist die Befehlszeile wie folgt:

_f:/kicad/bin/xsltproc.exe -o "%O" f:/kicad/bin/plugins/netlist_form_pads-pcb.xsl "%I"_

Unter Linux sieht der Befehl (abhängig vom Installationsort) wie folgt aus:

_xsltproc -o "%O" /usr/local/kicad/bin/plugins/netlist_form_pads-pcb.xsl "%I"_

Where _netlist_form_pads-pcb.xsl_ is the style-sheet that you are applying. Do not forget the double quotes around the file names, this allows them to have spaces after the substitution by KiCad.

Das Befehlszeilenformat akzeptiert Parameter für Dateinamen:

Die unterstützten Formatierungsparameter sind:

* %B => Basisdateiname und Pfad der ausgewählten Ausgabedatei ohne Pfad und Erweiterung.

* %I => Kompletter Dateiname und Pfad der temporären Eingangsdatei (die Zwischennetzliste).

* %O => Kompletter Dateiname und Pfad der vom Benutzer gewählten Ausgabedatei.

_%I_ wird vom tatsächlichen Zwischendateiname ersetzt.

_%O_ wird vom tatsächlichen Ausgabedateiname ersetzt.

[[command-line-format-example-for-xsltproc]]
===== Befehlszeilenformat: Beispiel für xsltproc

Das Befehlszeilenformat für xsltproc sieht wie folgt aus:

<Pfad zu xsltproc>xsltproc <xsltproc Parameter>

Unter Windows:

*f:/kicad/bin/xsltproc.exe -o "%O" f:/kicad/bin/plugins/netlist_form_pads-pcb.xsl "%I"*

Unter Linux (wieder abhängig vom Installationsort):

*xsltproc -o "%O" /usr/local/kicad/bin/plugins/netlist_form_pads-pcb.xsl "%I"*

Die obigen Beispiele gehen davon aus, dass xsltproc auf Ihren PC unter Windows installiert ist und sich alle Dateien in kicad/bin befinden.

[[bill-of-materials-generation]]
==== Stücklistenerzeugung

Weil die zwischenzeitliche Netzlistendatei alle Informationen über verwendete Bauteile enthält, kann eine Stückliste aus ihr abgeleitet werden. Hier ist das Einstellungsfenster des Plugin (in Linux) um eine angepasste Stücklistendatei zu erzeugen:

image::images/de/bom-netlist-tab.png[alt="Einstellungen BOM in der Netzliste", scaledwidth="80%"]

Der Pfad zum Stylesheet bom2csv.xsl ist abhängig vom verwendeten Betriebssystem. Das derzeit beste XSLT Stylesheet zur Stücklistenerzeugung heißt __bom2csv.xsl__. Sie können es nach Ihren Anforderungen anpassen und wenn Sie etwas allgemein Nutzbares erzeugen, fragen Sie ob es Teil des KiCad Projekts werden kann.

[[command-line-format-example-for-python-scripts]]
=== Kommandozeilenformat: Beispiel für Pythonskripte

Das Befehlszeilenformat für Python sieht so aus:

python <script file name> <input filename> <output filename>

Unter Windows:

*python *.exe f:/kicad/python/my_python_script.py "%I" "%O"*

Unter Linux (wieder abhängig vom Installationsort):

*python /usr/local/kicad/python/my_python_script.py "%I" "%O"*

Dabei wird angenommen, dass Python auf Ihrem PC installiert ist.

[[intermediate-netlist-structure]]
=== Struktur der Zwischennetzliste

Dieses Beispiel gibt Ihnen eine Idee für das Netzlistendateiformat:

---------------------------------------------------------------
<?xml version="1.0" encoding="utf-8"?>
<export version="D">
  <design>
    <source>F:\kicad_aux\netlist_test\netlist_test.sch</source>
    <date>29/08/2010 21:07:51</date>
    <tool>eeschema (2010-08-28 BZR 2458)-unstable</tool>
  </design>
  <components>
    <comp ref="P1">
      <value>CONN_4</value>
      <libsource lib="conn" part="CONN_4"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E2141</tstamp>
    </comp>
    <comp ref="U2">
      <value>74LS74</value>
      <libsource lib="74xx" part="74LS74"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E20BA</tstamp>
    </comp>
    <comp ref="U1">
      <value>74LS04</value>
      <libsource lib="74xx" part="74LS04"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E20A6</tstamp>
    </comp>
    <comp ref="C1">
      <value>CP</value>
      <libsource lib="device" part="CP"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E2094</tstamp>
    <comp ref="R1">
      <value>R</value>
      <libsource lib="device" part="R"/>
      <sheetpath names="/" tstamps="/"/>
      <tstamp>4C6E208A</tstamp>
    </comp>
  </components>
  <libparts/>
  <libraries/>
  <nets>
    <net code="1" name="GND">
      <node ref="U1" pin="7"/>
      <node ref="C1" pin="2"/>
      <node ref="U2" pin="7"/>
      <node ref="P1" pin="4"/>
    </net>
    <net code="2" name="VCC">
      <node ref="R1" pin="1"/>
      <node ref="U1" pin="14"/>
      <node ref="U2" pin="4"/>
      <node ref="U2" pin="1"/>
      <node ref="U2" pin="14"/>
      <node ref="P1" pin="1"/>
    </net>
    <net code="3" name="">
      <node ref="U2" pin="6"/>
    </net>
    <net code="4" name="">
      <node ref="U1" pin="2"/>
      <node ref="U2" pin="3"/>
    </net>
    <net code="5" name="/SIG_OUT">
      <node ref="P1" pin="2"/>
      <node ref="U2" pin="5"/>
      <node ref="U2" pin="2"/>
    </net>
    <net code="6" name="/CLOCK_IN">
      <node ref="R1" pin="2"/>
      <node ref="C1" pin="1"/>
      <node ref="U1" pin="1"/>
      <node ref="P1" pin="3"/>
    </net>
  </nets>
</export>
---------------------------------------------------------------

[[general-netlist-file-structure]]
==== Allgemeine Struktur der Netzlistendatei

Die Zwischennetzliste hat fünf Abschnitte.

* Einen Header Abschnitt.
* Einen Abschnitt der Bauteile.
* Einen Abschnitt der Bibliotheksteile.
* Einen Abschnitt der Bibliotheken.
* Einen Abschnitt der Netze.

Der Dateiinhalt hat das Trennzeichen <export>.

--------------------
<export version="D">
...
</export>
--------------------

[[the-header-section]]
==== Der Header

Der Header hat das Trennzeichen <design>.

-----------------------------------------------------------
<design>
<source>F:\kicad_aux\netlist_test\netlist_test.sch</source>
<date>21/08/2010 08:12:08</date>
<tool>eeschema (2010-08-09 BZR 2439)-unstable</tool>
</design>
-----------------------------------------------------------

Dieser Abschnitt kann als ein Kommentarabschnitt betrachtet werden.

[[the-components-section]]
==== Der Abschnitt der Bauteile

Der Abschnitt der Bauteile hat das Trennzeichen <components>.

-------------------------------------
<components>
<comp ref="P1">
<value>CONN_4</value>
<libsource lib="conn" part="CONN_4"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>4C6E2141</tstamp>
</comp>
</components>
-------------------------------------

Dieser Abschnitt enthält die Liste der Bauteile ihres Schaltplans. Jedes Bauteil ist wie folgt beschrieben:

-------------------------------------
<comp ref="P1">
<value>CONN_4</value>
<libsource lib="conn" part="CONN_4"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>4C6E2141</tstamp>
</comp>
-------------------------------------

[width="100%", cols="37%,63%"]
|=======================================================================
|*libsource* |name of the lib where this component was found.

|*part* |component name inside this library.

|*sheetpath* |path of the sheet inside the hierarchy: identify the sheet
within the full schematic hierarchy.

|*tstamps (time stamps)* |time stamp of the schematic file.

|*tstamp (time stamp)* |time stamp of the component.
|=======================================================================

[[note-about-time-stamps-for-components]]
===== Anmerkung zu Zeitstempeln für Bauteile

Um ein Bauteil in einer Netzliste und damit auf der Leiterplatte zu identifizieren, wird die Zeitstempel-Referenz als einzigartig für jedes Bauteil verwendet. Jedoch stellt KiCad einen zusätzlichen Hilfsweg zur Verfügung um ein Bauteil zu identifizieren, und zwar über den zugehörigen Footprint auf der Leiterplatte. Das erlaubt die Neunummerierung von Bauteilen in einem Schaltplanprojekt ohne den Verlust der Verbindung zwischen Bauteil und seinem Footprint.

Ein Zeitstempel ist eine einzigartige Identifizierung für jedes Bauteil oder Blatt in einem Schaltplanprojekt. Jedoch wird in einer komplexen Hierarchie das selbe Blatt mehr als einmal verwendet, daher enthält dieses Blatt Bauteile mit dem gleichen Zeitstempel.

Ein gegebenes Blatt hat eine einzigartige Identifizierung innerhalb einer komplexen Hierarchie: seinen Blattpfad. Ein gegebenes Bauteil (in einer komplexen Hierarchie) hat ebenfalls eine einzigartige Identifizierung: den Blattpfad + seinen Zeitstempel.

[[the-libparts-section]]
==== Der Abschnitt der Bibliotheksteile

Der Abschnitt der Bibliotheksteile hat das Trennzeichen <libparts> und der Inhalt dieses Abschnitts ist in den Schaltplanbibliotheken festgelegt. Der Abschnitt der Bibliotheksteile enthält:

* The allowed footprints names (names use wildcards) delimiter <fp>.
* Die in der Bibliothek definierten Felder, Trennzeichen <fields>.
* Die Liste der Anschlüsse, Trennzeichen <pins>.

--------------------------------------------------
<libparts>
<libpart lib="device" part="CP">
  <description>Condensateur polarise</description>
  <footprints>
    <fp>CP*</fp>
    <fp>SM*</fp>
  </footprints>
  <fields>
    <field name="Reference">C</field>
    <field name="Valeur">CP</field>
  </fields>
  <pins>
    <pin num="1" name="1" type="passive"/>
    <pin num="2" name="2" type="passive"/>
  </pins>
</libpart>
</libparts>
--------------------------------------------------

Zeilen wie <pin num="1" type="passive"/> geben ebenfalls den elektrischen Typ des Anschlusses an. Die möglichen elektrischen Typen sind:

[width="94%", cols="25%,75%"]
|================================================================
|Input |Normaler Eingang
|Output |Normaler Ausgang
|Bidirectional |Eingang oder Ausgang
|Tri-state |Bus Ein-/Ausgang
|Passive |Üblicherweise die Enden von passiven Bauteilen
|Unspecified |Unbekannter elektrischer Typ
|Power input |Spannungseingang des Bauteils
|Power output |Spannungsausgang wie z.B. Ausgang eines Spannungsreglers
|Open collector |Offener Kollektorausgang wie häufig in Analog Komparatoren zu finden
|Open emitter |Ausgang der manchmal bei Logikbausteinen zu finden ist
|Not connected |Darf im Schaltplan nicht verbunden werden
|================================================================

[[the-libraries-section]]
==== Der Abschnitt der Bibliotheken

Der Abschnitt der Bibliotheken hat das Trennzeichen <libraries>. Dieser Abschnitt enthält die Liste der im Projekt verwendeten Schaltplanbibliotheken.

------------------------------------------------
<libraries>
  <library logical="device">
    <uri>F:\kicad\share\library\device.lib</uri>
  </library>
  <library logical="conn">
    <uri>F:\kicad\share\library\conn.lib</uri>
  </library>
</libraries>
------------------------------------------------

[[the-nets-section]]
==== Der Abschnitt der Netze

Der Abschnitt der Netze hat das Trennzeichen <nets>. Dieser Abschnitt enthält die "Verbindungen" des Schaltplans.

-----------------------------
<nets>
  <net code="1" name="GND">
    <node ref="U1" pin="7"/>
    <node ref="C1" pin="2"/>
    <node ref="U2" pin="7"/>
    <node ref="P1" pin="4"/>
  </net>
  <net code="2" name="VCC">
    <node ref="R1" pin="1"/>
    <node ref="U1" pin="14"/>
    <node ref="U2" pin="4"/>
    <node ref="U2" pin="1"/>
    <node ref="U2" pin="14"/>
    <node ref="P1" pin="1"/>
  </net>
</nets>
-----------------------------

Dieser Abschnitt listet alle Netze des Schaltplans auf.

Ein mögliches Netz enthält das folgende:

--------------------------
<net code="1" name="GND">
  <node ref="U1" pin="7"/>
  <node ref="C1" pin="2"/>
  <node ref="U2" pin="7"/>
  <node ref="P1" pin="4"/>
</net>
--------------------------

[width="77%", cols="20%,80%"]
|================================================
|net code |ist ein interner Identifikator für dieses Netz
|name |ist der Name für dieses Netz
|node |gibt eine Anschlussreferenz an der mit diesem Netz verbunden ist
|================================================

[[more-about-xsltproc]]
=== Mehr über xsltproc

Finden Sie auf der Seite: _http://xmlsoft.org/XSLT/xsltproc.html_

[[introduction-7]]
==== Einleitung

xsltproc ist ein Befehlszeilenwerkzeug, um XSLT Stylesheets auf XML Dokumente anzuwenden. Obwohl es als Teil des GNOME-Projekts entwickelt wurde, kann es unabhängig vom GNOME-Desktop verwendet werden.

xsltproc wird von auf Befehlszeile mit dem Namen des zu verwendenden Stylesheets, gefolgt vom Namen der Datei oder Dateien auf welche das Stylesheet angewendet werden soll aufgerufen. Es wird die Standard Eingabe verwenden, wenn ein Dateiname mit - angegeben wird.

Wenn ein Stylesheet in einem XML-Dokument mit Stylesheet Verarbeitungshinweisen enthalten ist, muss kein Stylesheet auf der Befehlszeile angegeben werden. xsltproc wird das enthaltene Stylesheet automatisch erkennen und benutzen. Standardmäßig erfolgt die Ausgabe nach __stdout__. Sie können eine Ausgabedatei mit der -o Option angeben.

[[synopsis]]
==== Übersicht

---------------------------------------------------------------------------
xsltproc [[-V] | [-v] | [-o *file* ] | [--timing] | [--repeat] |
[--debug] | [--novalid] | [--noout] | [--maxdepth *val* ] | [--html] |
[--param *name* *value* ] | [--stringparam *name* *value* ] | [--nonet] |
[--path *paths* ] | [--load-trace] | [--catalogs] | [--xinclude] |
[--profile] | [--dumpextensions] | [--nowrite] | [--nomkdir] |
[--writesubtree] | [--nodtdattr]] [ *stylesheet* ] [ *file1* ] [ *file2* ]
[ *....* ]
---------------------------------------------------------------------------

[[command-line-options]]
==== Befehlszeilen-Optionen

_-V_ or _--version_

Zeigt die verwendete Version von libxml und libxslt an.

_-v_ or _--verbose_

Gebe jeden Schritt aus, den xsltproc bei der Verarbeitung des Stylesheets und des Dokuments durchführt

_-o_ or _--output file_

Leite die Ausgabe auf den Dateinamen __file__ um. Für mehrere Ausgaben, auch als ``chunking'' benannt, leitet -o Verzeichnis/ die Ausgabendateien in ein spezielles Verzeichnis um. Das Verzeichnis muss schon angelegt sein.

_--timing_

Zeigt die Zeit an, die für das Lesen des Stylesheets, des Dokuments, Anwenden des Stylesheets und speichern des Ergebnisses benötigt wurde. Die Zeiten werden in Millisekunden angegeben.

_--repeat_

Führe die Umwandlung 20 mal durch. Wird für Zeit bestimmende Tests verwendet.

_--debug_

Gibt den XML-Baum des umgewandelten Dokuments aus; für Debug Zwecke.

_--novalid_

Überspringe das Laden der DTD des Dokuments.

_--noout_

Das Ergebnis nicht ausgeben.

_--maxdepth value_

Stellt die maximale Tiefe des Vorlagenstapels ein, bevor libxslt feststellt, dass es in einer unendlichen Schleife festhängt. Der Standard ist 500.

_--html_

Das Eingabedokument ist eine HTML-Datei.

_--param name value_

Übergibt einen Parameter mit dem Namen _name_ und des Wertes _value_ an das Stylesheet. Sie können mehrere Namen/Wert Paare bis zu einem Maximum von 32 angeben. Wenn der übergebene Wert eine Zeichenkette und kein Knoten Identifikator ist, benutzen Sie stattdessen --stringparam.

_--stringparam name value_

Übergibt einen Parameter mit dem Namen _name_ und Wert _value_ wobei _value_ eine Zeichenkette und kein Knoten Identifikator ist. (Anmerkung: die Zeichenkette muss UTF-8 sein.)

_--nonet_

Nicht das Internet benutzen um DTD's, Entities oder Dokumente zu laden.

_--path paths_

Benutze die Liste (getrennt mit Leerzeichen oder Doppelpunkt) von Dateisystempfaden, angegeben über _paths_, um DTD's, Entities oder Dokumente zu laden.

_--load-trace_

Gibt alle während der Verarbeitung geladene Dokumente auf stderr aus.

_--catalogs_

Benutze den in SGML_CATALOG_FILES spezifizierten SGML-Katalog um den Ort von externen Entities aufzulösen. Standardmäßig sucht xsltproc nach dem Katalog, der in XML_CATALOG_FILES spezifiziert ist. Wenn das nicht spezifiziert ist, benutzt es /etc/xml/catalog.

_--xinclude_

Verarbeitet das Eingabe-Dokument unter Benutzung der Xinclude-Spezifikation. Mehr Details dazu können in der Xinclude-Spezifikation gefunden werden: http://www.w3.org/TR/xinclude/[http://www.w3.org/TR/xinclude/]

_--profile --norman_

Gibt detaillierte Information über die in jedem Teil des Stylesheets benötigte Zeit aus. Das ist hilfreich um die Performance des Stylesheets zu optimieren.

_--dumpextensions_

Gibt die Liste aller registrierten Erweiterungen auf stdout aus.

_--nowrite_

Untersagt jegliches Schreiben in eine Datei oder Ressource.

_--nomkdir_

Untersagt das Erstellen von Verzeichnissen.

_--writesubtree path_

Erlaubt das Schreiben von Dateien nur unterhalb des Pfades _path_.

_--nodtdattr_

Keine Standardattribute aus dem DTD des Dokuments anwenden.

[[xsltproc-return-values]]
==== Xsltproc Rückgabewerte

xsltproc gibt eine Status Nummer zurück, die sehr hilfreich sein kann, wenn es aus einem Skript aufgerufen wird.

0: Normal

1: Kein Argument

2: zu viele Parameter

3: unbekannte Option

4: konnte Stylesheet nicht abarbeiten

5: Fehler im Stylesheet

6: Fehler in einem der Dokumente

7: nicht unterstützte xsl:Ausgabe Methode

8: Zeichenketten-Parameter enthält sowohl einfache als auch doppelte Anführungszeichen

9: interner Verarbeitungsfehler

10: Verarbeitung wurde durch eine Abbruch Nachricht gestoppt

11: konnte das Ergebnis in die Ausgabedatei schreiben

[[more-information-about-xsltproc]]
==== Mehr Information über xsltproc

libxml Webseite: http://www.xmlsoft.org/[http://www.xmlsoft.org/]

W3C XSLT Webseite: http://www.w3.org/TR/xslt[http://www.w3.org/TR/xslt]

:experimental:

[[simulator]]
== Simulator ==

KiCad provides an embedded electrical circuit simulator using http://ngspice.sourceforge.net[ngspice] as the simulation engine.

When working with the simulator, you may find the official _pspice_ library useful. It contains common symbols used for simulation like voltage/current sources or transistors with pins numbered to match the ngspice node order specification.

There are also a few demo projects to illustrate the simulator capabilities. You will find them in _demos/simulation_ directory.

=== Assigning models

Before a simulation is launched, components need to have Spice model assigned.

Each component can have only one model assigned, even if component consists of multiple units. In such case, the first unit should have the model specified.

[[sim-passive-models]] Passive components with reference matching a device type in Spice notation (_R*_ for resistors, _C*_ for capacitors, _L*_ for inductors) will have models assigned implicitly and use the value field to determine their properties.

[NOTE]
Keep in mind that in Spice notation 'M' stands for milli and 'Meg' corresponds to mega. If you prefer to use 'M' to indicate mega prefix, you may request doing so in the <<sim-settings, simulation settings dialog>>.

Spice model information is stored as text in symbol fields, therefore you may either define it in symbol editor or schematics editor. Open symbol properties dialog and click on _Edit Spice Model_ button to open Spice Model Editor dialog.

Spice Model Editor dialog has three tabs corresponding to different model types. There are two options common to all model types:

[width="90%", cols="30%a,70%a"]
|====
|Disable symbol for simulation
|When checked the component is excluded from simulation.
|Alternate node sequence
|Allows one to override symbol pin to model node mapping.
To define a different mapping, specify pin numbers in order expected by the model.

'Example:' +
____
`* connections:` +
`* 1: non-inverting input` +
`* 2: inverting input` +
`* 3: positive power supply` +
`* 4: negative power supply` +
`* 5: output` +
`.subckt tl071 1 2 3 4 5`
____

image::images/opamp_symbol.png[alt="Generic operational amplifier symbol"]

To match the symbol pins to the Spice model nodes shown above, one needs to use an alternate node sequence option with value: "1{nbsp}3{nbsp}5{nbsp}2{nbsp}4". It is a list of pin numbers corresponding to the Spice model nodes order.
|====

==== Passive

_Passive_ tab allows the user to assign a passive device model (resistor, capacitor or inductor) to a component. It is a rarely used option, as normally passive components have models assigned <<sim-passive-models,implicitly>>, unless component reference does not match the actual device type.

[NOTE]
Explicitly defined passive device models have priority over the ones assigned implicitly. It means that once a passive device model is assigned, the reference and value fields are not taken into account during simulation. It may lead to a confusing situation when assigned model value does not match the one displayed on a schematic sheet.

image::images/sim_model_passive.png[alt="Passive device model editor tab"]

[width="90%", cols="30%a,70%a"]
|====
|Type
|Selects the device type (resistor, capacitor or inductor).
|Value
|Defines the device property (resistance, capacitance or inductance). The value
may use common Spice unit prefixes (as listed below the text input field) and
should use point as the decimal separator. Note that Spice does not correctly
interpret prefixes intertwined in the value (e.g. 1k5).
|====

==== Model

_Model_ tab is used to assign a semiconductor or a complex model defined in an external library file. Spice model libraries are often offered by device manufacturers.

The main text widget displays the selected library file contents. It is a common practice to put models description inside library files, including the node order.

image::images/sim_model_subckt.png[alt="Semiconductor device model editor tab"]

[width="90%", cols="30%a,70%a"]
|====================
|File
|Path to a Spice library file. This file is going to be used by the simulator,
as it is added using _.include_ directive.
|Model
|Selected device model. When a file is selected, the list is filled with available
models to choose from.
|Type
|Selects model type (subcircuit, BJT, MOSFET or diode). Normally it is set
automatically when a model is selected.
|====================

==== Source

_Source_ tab is used to assign a power or signal source model. There are two sections: _DC/AC analysis_ and _Transient analysis_. Each defines source parameters for the corresponding simulation type.

_Source type_ option applies to all simulation types.

image::images/sim_model_source.png[alt="Source model editor tab"]

Refer to the http://ngspice.sourceforge.net/docs/ngspice-27-manual.pdf[ngspice documentation], chapter 4 (Voltage and Current Sources) for more details about sources.

[[sim-directives]]
=== Spice directives

It is possible to add Spice directives by placing them in text fields on a schematic sheet. This approach is convenient for defining the default simulation type. This functionality is limited to Spice directives starting with a dot (e.g. `.tran 10n 1m`), it is not possible to place additional components using text fields.

=== Simulation

To launch a simulation, open _Spice Simulator_ dialog by selecting menu _Tools->Simulator_ in the schematics editor window.

image::images/sim_main_dialog.png[alt="Main simulation dialog"]

The dialog is divided into several sections:

* <<sim-toolbar,Toolbar>>
* <<sim-plot-panel,Plot panel>>
* <<sim-output-console,Output console>>
* <<sim-signals-list,Signals list>>
* <<sim-cursors-list,Cursors list>>
* <<sim-tune-panel,Tune panel>>

==== Menu

[[sim-menu-file]]
===== File
[width="90%", cols="30%,70%"]
|====
|New Plot | Create a new tab in the plot panel.
|Open Workbook | Open a list of plotted signals.
|Save Workbook | Save a list of plotted signals.
|Save as image | Export the active plot to a .png file.
|Save as .csv file | Export the active plot raw data points to a .csv file.
|Exit Simulation | Close the dialog.
|====

[[sim-menu-simulation]]
===== Simulation
[width="90%", cols="30%,70%"]
|====
|Run Simulation | Perform a simulation using the current settings.
|Add signals... | Open a dialog to select signals to be plotted.
|Probe from schematics | Start the schematics <<sim-probe-tool,Probe>> tool.
|Tune component value | Start the <<sim-tuner-tool,Tuner>> tool.
|Show SPICE Netlist... | Open a dialog showing the generated netlist for the
simulated circuit.
|Settings... | Open the <<sim-settings,simulation settings dialog>>.
|====

[[sim-menu-view]]
===== View
[width="90%", cols="30%,70%"]
|====
|Zoom In | Zoom in the active plot.
|Zoom Out | Zoom out the active plot.
|Fit on Screen | Adjust the zoom setting to display all plots.
|Show grid | Toggle grid visibility.
|Show legend | Toggle plot legend visibility.
|====

[[sim-toolbar]]
==== Toolbar
image::images/sim_main_toolbar.png[alt="Simulation dialog top toolbar"]
The top toolbar provides access to the most frequently performed actions.

[width="90%", cols="30%,70%"]
|====
|Run/Stop Simulation | Start or stop the simulation.
|Add Signals | Open a dialog to select signals to be plotted.
|Probe | Start the schematics <<sim-probe-tool,Probe>> tool.
|Tune | Start the <<sim-tuner-tool,Tuner>> tool.
|Settings | Open the <<sim-settings,simulation settings dialog>>.
|====

[[sim-plot-panel]]
==== Plot panel
Visualizes the simulation results as plots. One can have multiple plots opened in separate tabs, but only the active one is updated when a simulation is executed. This way it is possible to compare simulation results for different runs.

Plots might be customized by toggling grid and legend visibility using <<sim-menu-view,View>> menu. When a legend is visible, it can be dragged to change its position.

Plot panel interaction:

* scroll mouse wheel to zoom in/out
* right click to open a context menu to adjust the view
* draw a selection rectangle to zoom in the selected area
* drag a cursor to change its coordinates

[[sim-output-console]]
==== Output console
Output console displays messages from the simulator. It is advised to check the console output to verify there are no errors or warnings.

[[sim-signals-list]]
==== Signals list
Shows the list of signals displayed in the active plot.

Signals list interaction:

* right click to open a context menu to hide signal or toggle cursor
* double click to hide signal

[[sim-cursors-list]]
==== Cursors list
Shows the list of cursors and their coordinates. Each signal may have one cursor displayed. Cursors visibility is set using the <<sim-signals-list,Signals>> list.

[[sim-tune-panel]]
==== Tune panel
Displays components picked with the <<sim-tuner-tool,Tuner>> tool. Tune panel allows the user to quickly modify component values and observe their influence on the simulation results - every time a component value is changed, the simulation is rerun and plots are updated.

For each component there a few controls associated:

* The top text field sets the maximum component value.
* The middle text field sets the actual component value.
* The bottom text field sets the minimum component value.
* Slider allows the user to modify the component value in a smooth way.
* _Save_ button modifies component value on the schematics to the one selected with the slider.
* _X_ button removes component from the Tune panel and restores its original value.

The three text fields recognize Spice unit prefixes.

[[sim-tuner-tool]]
==== Tuner tool
Tuner tool lets the user pick components for tuning.

To select a component for tuning, click on one in the schematics editor when the tool is active. Selected components will appear in the <<sim-tune-panel,Tune>> panel. Only passive components might be tuned.

[[sim-probe-tool]]
==== Probe tool
Probe tool provides an user-friendly way of selecting signals for plotting.

To add a signal to plot, click on a corresponding wire in the schematics editor when the tool is active.

[[sim-settings]]
==== Simulation settings

image::images/sim_settings.png[alt="Simulation settings dialog"]

Simulation settings dialog lets the user set the simulation type and parameters. There are four tabs:

* AC
* DC Transfer
* Transient
* Custom

The first three tabs provide forms where simulation parameters might be specified. The last tab allows the user to type in custom Spice directives to set up a simulation. You can find more information about simulation types and parameters in the http://ngspice.sourceforge.net/docs/ngspice-27-manual.pdf[ngspice documentation], chapter 1.2.

An alternative way to configure a simulation is to type <<sim-directives,Spice directives>> into text fields on schematics. Any text field directives related to simulation type are overridden by the settings selected in the dialog. It means that once you start using the simulation dialog, the dialog overriddes the schematics directives until the simulator is reopened.

There are two options common to all simulation types:
[width="90%", cols="30%,70%"]
|====
|Adjust passive symbol values | Replace passive symbol values to convert common
component values notation to Spice notation.
|Add full path for .include library directives | Prepend Spice model library
file names with full path. Normally full path is required by ngspice to access
a library file.
|====