# DP: updates from the 12 branch upto 20230611 (a7739a073a8).

LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \
	8fc1a49c9312b05d925b7d21f1d2145d70818151 a7739a073a8620495c87acfa37596aaea3ca5e04 \
	| awk '/^diff .*\.texi/ {skip=1; next} /^diff / { skip=0 } skip==0' \
	| grep -v -E '^(diff|index)'

--- a/src/gcc/ChangeLog
+++ b/src/gcc/ChangeLog
@@ -1,3 +1,723 @@
+2023-06-10  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/109650
+	PR target/92729
+	Backport from 2023-05-10 master r14-1688.
+	* config/avr/avr-passes.def (avr_pass_ifelse): Insert new pass.
+	* config/avr/avr.cc (avr_pass_ifelse): New RTL pass.
+	(avr_pass_data_ifelse): New pass_data for it.
+	(make_avr_pass_ifelse, avr_redundant_compare, avr_cbranch_cost)
+	(avr_canonicalize_comparison, avr_out_plus_set_ZN)
+	(avr_out_cmp_ext): New functions.
+	(compare_condtition): Make sure REG_CC dies in the branch insn.
+	(avr_rtx_costs_1): Add computation of cbranch costs.
+	(avr_adjust_insn_length) [ADJUST_LEN_ADD_SET_ZN, ADJUST_LEN_CMP_ZEXT]:
+	[ADJUST_LEN_CMP_SEXT]Handle them.
+	(TARGET_CANONICALIZE_COMPARISON): New define.
+	(avr_simplify_comparison_p, compare_diff_p, avr_compare_pattern)
+	(avr_reorg_remove_redundant_compare, avr_reorg): Remove functions.
+	(TARGET_MACHINE_DEPENDENT_REORG): Remove define.
+	* config/avr/avr-protos.h (avr_simplify_comparison_p): Remove proto.
+	(make_avr_pass_ifelse, avr_out_plus_set_ZN, cc_reg_rtx)
+	(avr_out_cmp_zext): New Protos
+	* config/avr/avr.md (branch, difficult_branch): Don't split insns.
+	(*cbranchhi.zero-extend.0", *cbranchhi.zero-extend.1")
+	(*swapped_tst<mode>, *add.for.eqne.<mode>): New insns.
+	(*cbranch<mode>4): Rename to cbranch<mode>4_insn.
+	(define_peephole): Add dead_or_set_regno_p(insn,REG_CC) as needed.
+	(define_deephole2): Add peep2_regno_dead_p(*,REG_CC) as needed.
+	Add new RTL peepholes for decrement-and-branch and *swapped_tst<mode>.
+	Rework signtest-and-branch peepholes for *sbrx_branch<mode>.
+	(adjust_len) [add_set_ZN, cmp_zext]: New.
+	(QIPSI): New mode iterator.
+	(ALLs1, ALLs2, ALLs4, ALLs234): New mode iterators.
+	(gelt): New code iterator.
+	(gelt_eqne): New code attribute.
+	(rvbranch, *rvbranch, difficult_rvbranch, *difficult_rvbranch)
+	(branch_unspec, *negated_tst<mode>, *reversed_tst<mode>)
+	(*cmpqi_sign_extend): Remove insns.
+	(define_c_enum "unspec") [UNSPEC_IDENTITY]: Remove.
+	* config/avr/avr-dimode.md (cbranch<mode>4): Canonicalize comparisons.
+	* config/avr/predicates.md (scratch_or_d_register_operand): New.
+	* config/avr/constraints.md (Yxx): New constraint.
+
+2023-06-09  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>
+
+	Backported from master:
+	2023-06-06  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>
+
+	PR target/106907
+	* config/rs6000/rs6000.cc (vec_const_128bit_to_bytes): Remove
+	duplicate expression.
+
+2023-06-09  Iain Sandoe  <iain@sandoe.co.uk>
+
+	Backported from master:
+	2023-06-02  Iain Sandoe  <iain@sandoe.co.uk>
+
+	PR target/110044
+	* config/rs6000/rs6000.cc (darwin_rs6000_special_round_type_align):
+	Make sure that we do not have a cap on field alignment before altering
+	the struct layout based on the type alignment of the first entry.
+
+2023-06-09  liuhongt  <hongtao.liu@intel.com>
+
+	PR target/110108
+	* config/i386/i386.cc (ix86_gimple_fold_builtin): Explicitly
+	view_convert_expr mask to signed type when folding pblendvb
+	builtins.
+
+2023-06-08  Alex Coplan  <alex.coplan@arm.com>
+
+	Backported from master:
+	2023-05-25  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/109800
+	* config/arm/arm.md (movdf): Generate temporary pseudo in DImode
+	instead of DFmode.
+	* config/arm/vfp.md (no_literal_pool_df_immediate): Rather than punning an
+	lvalue DFmode pseudo into DImode, use a DImode pseudo and pun it into
+	DFmode as an rvalue.
+
+2023-06-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2023-05-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/109939
+	* config/arm/arm-builtins.cc (SAT_BINOP_UNSIGNED_IMM_QUALIFIERS): Use
+	qualifier_none for the return operand.
+
+2023-06-02  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/110088
+	* config/avr/avr.md: Add an RTL peephole to optimize operations on
+	non-LD_REGS after a move from LD_REGS.
+	(piaop): New code iterator.
+
+2023-06-01  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2023-06-01  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR target/109954
+	* doc/invoke.texi (x86 Options): Fix description of -m32 option.
+
+2023-05-30  Andreas Schwab  <schwab@suse.de>
+
+	PR target/110036
+	* config/riscv/riscv.cc (riscv_asan_shadow_offset): Update to
+	match libsanitizer.
+
+2023-05-25  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/104327
+	* config/avr/avr.cc (avr_can_inline_p): New static function.
+	(TARGET_CAN_INLINE_P): Define to that function.
+
+2023-05-25  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/82931
+	* config/avr/avr.md (*movbitqi.0): Rename to *movbit<mode>.0-6.
+	Handle any bit position and use mode QISI.
+	* config/avr/avr.cc (avr_rtx_costs_1) [IOR]: Return a cost
+	of 2 insns for bit-transfer of respective style.
+
+2023-05-23  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr.cc (avr_insn_cost): New static function.
+	(TARGET_INSN_COST): Define to that function.
+
+2023-05-22   Michael Meissner  <meissner@linux.ibm.com>
+
+	PR target/70243
+	* config/rs6000/vsx.md (vsx_fmav4sf4): Do not generate vmaddfp.
+	(vsx_nfmsv4sf4): Do not generate vnmsubfp.  Back port from master
+	04/10/2023 change.
+
+2023-05-22  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-21  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/109505
+	* match.pd ((x | CST1) & CST2 -> (x & CST2) | (CST1 & CST2),
+	Combine successive equal operations with constants,
+	(A +- CST1) +- CST2 -> A + CST3, (CST1 - A) +- CST2 -> CST3 - A,
+	CST1 - (CST2 - A) -> CST3 + A): Use ! on ops with 2 CONSTANT_CLASS_P
+	operands.
+
+2023-05-22  Kewen Lin  <linkw@linux.ibm.com>
+
+	Backported from master:
+	2023-05-17  Kewen Lin  <linkw@linux.ibm.com>
+
+	* tree-vect-loop.cc (vect_analyze_loop_1): Don't retry analysis with
+	suggested unroll factor once the previous analysis fails.
+
+2023-05-20  Triffid Hunter  <triffid.hunter@gmail.com>
+
+	PR target/105753
+	Backport from 2023-05-20 https://gcc.gnu.org/r14-1016
+	* config/avr/avr.md (divmodpsi, udivmodpsi, divmodsi, udivmodsi):
+	Remove superfluous "parallel" in insn pattern.
+	([u]divmod<mode>4): Tidy code.  Use gcc_unreachable() instead of
+	printing error text to assembly.
+
+2023-05-18  Alexandre Oliva  <oliva@adacore.com>
+
+	* config/arm/vfp.md (*thumb2_movsi_vfp): Drop blank after tab
+	after vmsr and vmrs, and lower the case of P0.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* config/arm/arm_mve.h: (__ARM_mve_typeid): Add more pointer types.
+	(__ARM_mve_coerce1): Remove.
+	(__ARM_mve_coerce2): Remove.
+	(__ARM_mve_coerce3): Remove.
+	(__ARM_mve_coerce_i_scalar): New.
+	(__ARM_mve_coerce_s8_ptr): New.
+	(__ARM_mve_coerce_u8_ptr): New.
+	(__ARM_mve_coerce_s16_ptr): New.
+	(__ARM_mve_coerce_u16_ptr): New.
+	(__ARM_mve_coerce_s32_ptr): New.
+	(__ARM_mve_coerce_u32_ptr): New.
+	(__ARM_mve_coerce_s64_ptr): New.
+	(__ARM_mve_coerce_u64_ptr): New.
+	(__ARM_mve_coerce_f_scalar): New.
+	(__ARM_mve_coerce_f16_ptr): New.
+	(__ARM_mve_coerce_f32_ptr): New.
+	(__arm_vst4q): Change _coerce_ overloads.
+	(__arm_vbicq): Change _coerce_ overloads.
+	(__arm_vmulq): Change _coerce_ overloads.
+	(__arm_vcmpeqq): Change _coerce_ overloads.
+	(__arm_vcmpneq): Change _coerce_ overloads.
+	(__arm_vmaxnmavq): Change _coerce_ overloads.
+	(__arm_vmaxnmvq): Change _coerce_ overloads.
+	(__arm_vminnmavq): Change _coerce_ overloads.
+	(__arm_vsubq): Change _coerce_ overloads.
+	(__arm_vminnmvq): Change _coerce_ overloads.
+	(__arm_vrshlq): Change _coerce_ overloads.
+	(__arm_vqsubq): Change _coerce_ overloads.
+	(__arm_vqdmulltq): Change _coerce_ overloads.
+	(__arm_vqdmullbq): Change _coerce_ overloads.
+	(__arm_vqdmulhq): Change _coerce_ overloads.
+	(__arm_vqaddq): Change _coerce_ overloads.
+	(__arm_vhaddq): Change _coerce_ overloads.
+	(__arm_vhsubq): Change _coerce_ overloads.
+	(__arm_vqdmlashq): Change _coerce_ overloads.
+	(__arm_vqrdmlahq): Change _coerce_ overloads.
+	(__arm_vmlasq): Change _coerce_ overloads.
+	(__arm_vqdmlahq): Change _coerce_ overloads.
+	(__arm_vmaxnmavq_p): Change _coerce_ overloads.
+	(__arm_vmaxnmvq_p): Change _coerce_ overloads.
+	(__arm_vminnmavq_p): Change _coerce_ overloads.
+	(__arm_vminnmvq_p): Change _coerce_ overloads.
+	(__arm_vfmasq_m): Change _coerce_ overloads.
+	(__arm_vld1q): Change _coerce_ overloads.
+	(__arm_vld1q_z): Change _coerce_ overloads.
+	(__arm_vld2q): Change _coerce_ overloads.
+	(__arm_vld4q): Change _coerce_ overloads.
+	(__arm_vldrhq_gather_offset): Change _coerce_ overloads.
+	(__arm_vldrhq_gather_offset_z): Change _coerce_ overloads.
+	(__arm_vldrhq_gather_shifted_offset): Change _coerce_ overloads.
+	(__arm_vldrhq_gather_shifted_offset_z): Change _coerce_ overloads.
+	(__arm_vldrwq_gather_offset): Change _coerce_ overloads.
+	(__arm_vldrwq_gather_offset_z): Change _coerce_ overloads.
+	(__arm_vldrwq_gather_shifted_offset): Change _coerce_ overloads.
+	(__arm_vldrwq_gather_shifted_offset_z): Change _coerce_ overloads.
+	(__arm_vst1q_p): Change _coerce_ overloads.
+	(__arm_vst2q): Change _coerce_ overloads.
+	(__arm_vst1q): Change _coerce_ overloads.
+	(__arm_vstrhq): Change _coerce_ overloads.
+	(__arm_vstrhq_p): Change _coerce_ overloads.
+	(__arm_vstrhq_scatter_offset_p): Change _coerce_ overloads.
+	(__arm_vstrhq_scatter_offset): Change _coerce_ overloads.
+	(__arm_vstrhq_scatter_shifted_offset_p): Change _coerce_ overloads.
+	(__arm_vstrhq_scatter_shifted_offset): Change _coerce_ overloads.
+	(__arm_vstrwq_p): Change _coerce_ overloads.
+	(__arm_vstrwq): Change _coerce_ overloads.
+	(__arm_vstrwq_scatter_offset): Change _coerce_ overloads.
+	(__arm_vstrwq_scatter_offset_p): Change _coerce_ overloads.
+	(__arm_vstrwq_scatter_shifted_offset): Change _coerce_ overloads.
+	(__arm_vstrwq_scatter_shifted_offset_p): Change _coerce_ overloads.
+	(__arm_vsetq_lane): Change _coerce_ overloads.
+	(__arm_vcmpneq_m): Change _coerce_ overloads.
+	(__arm_vldrbq_gather_offset): Change _coerce_ overloads.
+	(__arm_vdwdupq_x_u8): Change _coerce_ overloads.
+	(__arm_vdwdupq_x_u16): Change _coerce_ overloads.
+	(__arm_vdwdupq_x_u32): Change _coerce_ overloads.
+	(__arm_viwdupq_x_u8): Change _coerce_ overloads.
+	(__arm_viwdupq_x_u16): Change _coerce_ overloads.
+	(__arm_viwdupq_x_u32): Change _coerce_ overloads.
+	(__arm_vidupq_x_u8): Change _coerce_ overloads.
+	(__arm_vddupq_x_u8): Change _coerce_ overloads.
+	(__arm_vidupq_x_u16): Change _coerce_ overloads.
+	(__arm_vddupq_x_u16): Change _coerce_ overloads.
+	(__arm_vidupq_x_u32): Change _coerce_ overloads.
+	(__arm_vddupq_x_u32): Change _coerce_ overloads.
+	(__arm_vhaddq_x): Change _coerce_ overloads.
+	(__arm_vhsubq_x): Change _coerce_ overloads.
+	(__arm_vldrdq_gather_offset): Change _coerce_ overloads.
+	(__arm_vldrdq_gather_offset_z): Change _coerce_ overloads.
+	(__arm_vldrdq_gather_shifted_offset): Change _coerce_ overloads.
+	(__arm_vldrdq_gather_shifted_offset_z): Change _coerce_ overloads.
+	(__arm_vldrbq_gather_offset_z): Change _coerce_ overloads.
+	(__arm_vqrdmlahq_m): Change _coerce_ overloads.
+	(__arm_vqrdmlashq_m): Change _coerce_ overloads.
+	(__arm_vqdmlashq_m): Change _coerce_ overloads.
+	(__arm_vmlaldavaxq_p): Change _coerce_ overloads.
+	(__arm_vmlasq_m): Change _coerce_ overloads.
+	(__arm_vqdmulhq_m): Change _coerce_ overloads.
+	(__arm_vqdmulltq_m): Change _coerce_ overloads.
+	(__arm_vidupq_u16): Change _coerce_ overloads.
+	(__arm_vidupq_u32): Change _coerce_ overloads.
+	(__arm_vidupq_u8): Change _coerce_ overloads.
+	(__arm_vddupq_u16): Change _coerce_ overloads.
+	(__arm_vddupq_u32): Change _coerce_ overloads.
+	(__arm_vddupq_u8): Change _coerce_ overloads.
+	(__arm_viwdupq_m): Change _coerce_ overloads.
+	(__arm_viwdupq_u16): Change _coerce_ overloads.
+	(__arm_viwdupq_u32): Change _coerce_ overloads.
+	(__arm_viwdupq_u8): Change _coerce_ overloads.
+	(__arm_vdwdupq_m): Change _coerce_ overloads.
+	(__arm_vdwdupq_u16): Change _coerce_ overloads.
+	(__arm_vdwdupq_u32): Change _coerce_ overloads.
+	(__arm_vdwdupq_u8): Change _coerce_ overloads.
+	(__arm_vaddlvaq): Change _coerce_ overloads.
+	(__arm_vaddlvaq_p): Change _coerce_ overloads.
+	(__arm_vaddvaq): Change _coerce_ overloads.
+	(__arm_vaddvaq_p): Change _coerce_ overloads.
+	(__arm_vcmphiq_m): Change _coerce_ overloads.
+	(__arm_vmladavaq_p): Change _coerce_ overloads.
+	(__arm_vmladavaxq): Change _coerce_ overloads.
+	(__arm_vmlaldavaxq): Change _coerce_ overloads.
+	(__arm_vstrbq): Change _coerce_ overloads.
+	(__arm_vstrbq_p): Change _coerce_ overloads.
+	(__arm_vrmlaldavhaq_p): Change _coerce_ overloads.
+	(__arm_vstrbq_scatter_offset): Change _coerce_ overloads.
+	(__arm_vstrbq_scatter_offset_p): Change _coerce_ overloads.
+	(__arm_vstrdq_scatter_offset_p): Change _coerce_ overloads.
+	(__arm_vstrdq_scatter_offset): Change _coerce_ overloads.
+	(__arm_vstrdq_scatter_shifted_offset_p): Change _coerce_ overloads.
+	(__arm_vstrdq_scatter_shifted_offset): Change _coerce_ overloads.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* config/arm/arm_mve.h (__arm_vbicq): Change coerce on
+	scalar constant.
+	(__arm_vmvnq_m): Likewise.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* config/arm/arm_mve.h (__arm_vorrq): Add _n variant.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic.
+	(__arm_vadcq_u32): Likewise.
+	(__arm_vadcq_m_s32): Likewise.
+	(__arm_vadcq_m_u32): Likewise.
+	(__arm_vsbcq_s32): Likewise.
+	(__arm_vsbcq_u32): Likewise.
+	(__arm_vsbcq_m_s32): Likewise.
+	(__arm_vsbcq_m_u32): Likewise.
+	* config/arm/mve.md (get_fpscr_nzcvqc): Make unspec_volatile.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vrndq_m_f<mode>, mve_vrev64q_f<mode>)
+	(mve_vrev32q_fv8hf, mve_vcvttq_f32_f16v4sf)
+	(mve_vcvtbq_f32_f16v4sf, mve_vcvtq_to_f_<supf><mode>)
+	(mve_vrev64q_<supf><mode>, mve_vcvtq_from_f_<supf><mode>)
+	(mve_vmovltq_<supf><mode>, mve_vmovlbq_<supf><mode>)
+	(mve_vcvtpq_<supf><mode>, mve_vcvtnq_<supf><mode>)
+	(mve_vcvtmq_<supf><mode>, mve_vcvtaq_<supf><mode>)
+	(mve_vmvnq_n_<supf><mode>, mve_vrev16q_<supf>v16qi)
+	(mve_vctp<mode1>qhi, mve_vbrsrq_n_f<mode>)
+	(mve_vbrsrq_n_<supf><mode>, mve_vandq_f<mode>, mve_vbicq_f<mode>)
+	(mve_vbicq_n_<supf><mode>, mve_vctp<mode1>q_mhi)
+	(mve_vcvtbq_f16_f32v8hf, mve_vcvttq_f16_f32v8hf)
+	(mve_veorq_f<mode>, mve_vmlaldavxq_s<mode>, mve_vmlsldavq_s<mode>)
+	(mve_vmlsldavxq_s<mode>, mve_vornq_f<mode>, mve_vorrq_f<mode>)
+	(mve_vrmlaldavhxq_sv4si, mve_vbicq_m_n_<supf><mode>)
+	(mve_vcvtq_m_to_f_<supf><mode>, mve_vshlcq_<supf><mode>)
+	(mve_vmvnq_m_<supf><mode>, mve_vpselq_<supf><mode>)
+	(mve_vcvtbq_m_f16_f32v8hf, mve_vcvtbq_m_f32_f16v4sf)
+	(mve_vcvttq_m_f16_f32v8hf, mve_vcvttq_m_f32_f16v4sf)
+	(mve_vmlaldavq_p_<supf><mode>, mve_vmlsldavaq_s<mode>)
+	(mve_vmlsldavaxq_s<mode>, mve_vmlsldavq_p_s<mode>)
+	(mve_vmlsldavxq_p_s<mode>, mve_vmvnq_m_n_<supf><mode>)
+	(mve_vorrq_m_n_<supf><mode>, mve_vpselq_f<mode>)
+	(mve_vrev32q_m_fv8hf, mve_vrev32q_m_<supf><mode>)
+	(mve_vrev64q_m_f<mode>, mve_vrmlaldavhaxq_sv4si)
+	(mve_vrmlaldavhxq_p_sv4si, mve_vrmlsldavhaxq_sv4si)
+	(mve_vrmlsldavhq_p_sv4si, mve_vrmlsldavhxq_p_sv4si)
+	(mve_vrev16q_m_<supf>v16qi, mve_vrmlaldavhq_p_<supf>v4si)
+	(mve_vrmlsldavhaq_sv4si, mve_vandq_m_<supf><mode>)
+	(mve_vbicq_m_<supf><mode>, mve_veorq_m_<supf><mode>)
+	(mve_vornq_m_<supf><mode>, mve_vorrq_m_<supf><mode>)
+	(mve_vandq_m_f<mode>, mve_vbicq_m_f<mode>, mve_veorq_m_f<mode>)
+	(mve_vornq_m_f<mode>, mve_vorrq_m_f<mode>)
+	(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn)
+	(mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn)
+	(mve_vstrdq_scatter_base_wb_p_<supf>v2di) : Fix spacing and
+	capitalization in the emitted asm.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/constraints.md (mve_vldrd_immediate): Move it to
+	predicates.md.
+	(Ri): Move constraint definition from predicates.md.
+	(Rl): Define new constraint.
+	* config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Add
+	missing constraint.
+	(mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint
+	for op 1, use mve_vstrw_immediate predicate and Rl constraint for
+	op 2. Fix asm output spacing.
+	(mve_vstrdq_scatter_base_wb_p_<supf>v2di): Add missing constraint.
+	* config/arm/predicates.md (Ri) Move constraint to constraints.md
+	(mve_vldrd_immediate): Move it from
+	constraints.md.
+	(mve_vstrw_immediate): New predicate.
+
+2023-05-18  Murray Steele  <murray.steele@arm.com>
+
+	Backported from master:
+	2023-01-18  Murray Steele  <murray.steele@arm.com>
+
+	PR target/108442
+	* config/arm/arm_mve.h (__arm_vst1q_p_u8): Use prefixed intrinsic
+	function.
+	(__arm_vst1q_p_s8): Likewise.
+	(__arm_vld1q_z_u8): Likewise.
+	(__arm_vld1q_z_s8): Likewise.
+	(__arm_vst1q_p_u16): Likewise.
+	(__arm_vst1q_p_s16): Likewise.
+	(__arm_vld1q_z_u16): Likewise.
+	(__arm_vld1q_z_s16): Likewise.
+	(__arm_vst1q_p_u32): Likewise.
+	(__arm_vst1q_p_s32): Likewise.
+	(__arm_vld1q_z_u32): Likewise.
+	(__arm_vld1q_z_s32): Likewise.
+	(__arm_vld1q_z_f16): Likewise.
+	(__arm_vst1q_p_f16): Likewise.
+	(__arm_vld1q_z_f32): Likewise.
+	(__arm_vst1q_p_f32): Likewise.
+
+2023-05-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backported from master:
+	2023-01-24  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	PR target/108177
+	* config/arm/mve.md (mve_vstrbq_p_<supf><mode>, mve_vstrhq_p_fv8hf,
+	mve_vstrhq_p_<supf><mode>, mve_vstrwq_p_<supf>v4si): Add memory operand
+	as input operand.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-04-04  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* config/arm/mve.md (mve_vcvtq_n_to_f_<supf><mode>): Swap operands.
+	(mve_vcreateq_f<mode>): Swap operands.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/96795
+	PR target/107515
+	* config/arm/arm_mve.h (__ARM_mve_coerce2): Split types.
+	(__ARM_mve_coerce3): Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vqnegq_s<mode>): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vqabsq_s<mode>): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vnegq_f<mode>, mve_vnegq_s<mode>):
+	Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (@mve_vclzq_s<mode>): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vclsq_s<mode>): Fix spacing.
+
+2023-05-18  Christophe Lyon  <christophe.lyon@arm.com>
+
+	Backported from master:
+	2023-02-03  Christophe Lyon  <christophe.lyon@arm.com>
+
+	* config/arm/mve.md (mve_vabavq_p_<supf><mode>): Add length
+	attribute.
+	(mve_vqshluq_m_n_s<mode>): Likewise.
+	(mve_vshlq_m_<supf><mode>): Likewise.
+	(mve_vsriq_m_n_<supf><mode>): Likewise.
+	(mve_vsubq_m_<supf><mode>): Likewise.
+
+2023-05-18  Christophe Lyon  <christophe.lyon@arm.com>
+
+	Backported from master:
+	2022-10-03  Christophe Lyon  <christophe.lyon@arm.com>
+
+	* config/arm/mve.md (mve_vrev64q_m_<supf><mode>): Add early
+	clobber.
+	(mve_vrev64q_m_f<mode>): Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vrmlaldavhq_<supf>v4si,
+	mve_vrmlaldavhaq_<supf>v4si): Fix spacing vs tabs.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vmlaldavaq_<supf><mode>)
+	(mve_vmlaldavaxq_s<mode>, mve_vmlaldavaxq_p_<supf><mode>): Fix
+	spacing vs tabs.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vsubq_n_f<mode>): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vaddlvq_p_<supf>v4si)
+	(mve_vaddq_n_<supf><mode>, mve_vaddvaq_<supf><mode>)
+	(mve_vaddlvaq_<supf>v4si, mve_vaddq_n_f<mode>)
+	(mve_vaddlvaq_p_<supf>v4si, mve_vaddq<mode>, mve_vaddq_f<mode>):
+	Fix spacing.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2022-11-28  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* config/arm/arm_mve.h (__arm_vsubq_x FP): New overloads.
+	(__arm_vsubq_x Integer): New.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2022-11-28  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/107515
+	* config/arm/arm_mve.h (__ARM_mve_typeid): Add float types.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2022-11-28  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/96795
+	* config/arm/arm_mve.h (__arm_vaddq): Fix Overloading.
+	(__arm_vmulq): Likewise.
+	(__arm_vcmpeqq): Likewise.
+	(__arm_vcmpneq): Likewise.
+	(__arm_vmaxnmavq): Likewise.
+	(__arm_vmaxnmvq): Likewise.
+	(__arm_vminnmavq): Likewise.
+	(__arm_vsubq): Likewise.
+	(__arm_vminnmvq): Likewise.
+	(__arm_vrshlq): Likewise.
+	(__arm_vqsubq): Likewise.
+	(__arm_vqdmulltq): Likewise.
+	(__arm_vqdmullbq): Likewise.
+	(__arm_vqdmulhq): Likewise.
+	(__arm_vqaddq): Likewise.
+	(__arm_vhaddq): Likewise.
+	(__arm_vhsubq): Likewise.
+	(__arm_vqdmlashq): Likewise.
+	(__arm_vqrdmlahq): Likewise.
+	(__arm_vmlasq): Likewise.
+	(__arm_vqdmlahq): Likewise.
+	(__arm_vmaxnmavq_p): Likewise.
+	(__arm_vmaxnmvq_p): Likewise.
+	(__arm_vminnmavq_p): Likewise.
+	(__arm_vminnmvq_p): Likewise.
+	(__arm_vfmasq_m): Likewise.
+	(__arm_vsetq_lane): Likewise.
+	(__arm_vcmpneq_m): Likewise.
+	(__arm_vhaddq_x): Likewise.
+	(__arm_vhsubq_x): Likewise.
+	(__arm_vqrdmlashq_m): Likewise.
+	(__arm_vqdmlashq_m): Likewise.
+	(__arm_vmlaldavaxq_p): Likewise.
+	(__arm_vmlasq_m): Likewise.
+	(__arm_vqdmulhq_m): Likewise.
+	(__arm_vqdmulltq_m): Likewise.
+	(__arm_viwdupq_m): Likewise.
+	(__arm_viwdupq_u16): Likewise.
+	(__arm_viwdupq_u32): Likewise.
+	(__arm_viwdupq_u8): Likewise.
+	(__arm_vdwdupq_m): Likewise.
+	(__arm_vdwdupq_u16): Likewise.
+	(__arm_vdwdupq_u32): Likewise.
+	(__arm_vdwdupq_u8): Likewise.
+	(__arm_vaddlvaq): Likewise.
+	(__arm_vaddlvaq_p): Likewise.
+	(__arm_vaddvaq): Likewise.
+	(__arm_vaddvaq_p): Likewise.
+	(__arm_vcmphiq_m): Likewise.
+	(__arm_vmladavaq_p): Likewise.
+	(__arm_vmladavaxq): Likewise.
+	(__arm_vmlaldavaxq): Likewise.
+	(__arm_vrmlaldavhaq_p): Likewise.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2022-11-28  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/96795
+	* config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Change types.
+	(__arm_vaddq_m_n_s32): Likewise.
+	(__arm_vaddq_m_n_s16): Likewise.
+	(__arm_vaddq_m_n_u8): Likewise.
+	(__arm_vaddq_m_n_u32): Likewise.
+	(__arm_vaddq_m_n_u16): Likewise.
+	(__arm_vaddq_m): Fix Overloading.
+	(__ARM_mve_coerce3): New.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vabsq_f<mode>): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (@mve_vcmp<mve_cmp_op>q_<mode>): Fix
+	spacing.
+	* config/arm/arm_mve.h (__arm_vcmpgtq_m, __arm_vcmpleq_m)
+	(__arm_vcmpltq_m, __arm_vcmpneq_m): Add missing defines.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vdupq_n_f<mode>)
+	(mve_vdupq_n_<supf><mode>, mve_vdupq_m_n_<supf><mode>)
+	(mve_vdupq_m_n_f<mode>): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vdwdupq_m_wb_u<mode>_insn): Fix spacing.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/mve.md (mve_vddupq_u<mode>_insn): Fix 'vddup.u'
+	spacing.
+	(mve_vddupq_m_wb_u<mode>_insn): Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* config/arm/vfp.md (*thumb2_movhi_vfp, *thumb2_movhi_fp16): Fix
+	'vmsr' spacing and reg capitalization.
+
+2023-05-15  liuhongt  <hongtao.liu@intel.com>
+
+	* config/i386/cygwin.h (ENDFILE_SPEC): Link crtfastmath.o
+	whenever -mdaz-ftz is specified. Don't link crtfastmath.o
+	when -mno-daz-ftz is specified.
+	* config/i386/darwin.h (ENDFILE_SPEC): Ditto.
+	* config/i386/gnu-user-common.h
+	(GNU_USER_TARGET_MATHFILE_SPEC): Ditto.
+	* config/i386/mingw32.h (ENDFILE_SPEC): Ditto.
+	* config/i386/i386.opt (mdaz-ftz): New option.
+	* doc/invoke.texi (x86 options): Document mftz-daz.
+
+2023-05-09  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-09  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/109778
+	* wide-int.h (wi::lrotate, wi::rrotate): Call wi::lrshift on
+	wi::zext (x, width) rather than x if width != precision, rather
+	than using wi::zext (right, width) after the shift.
+	* tree-ssa-ccp.cc (bit_value_binop): Call wi::ext on the results
+	of wi::lrotate or wi::rrotate.
+
+2023-05-09  Kewen Lin  <linkw@linux.ibm.com>
+
+	Backported from master:
+	2023-04-26  Kewen Lin  <linkw@linux.ibm.com>
+
+	PR target/108758
+	* config/rs6000/rs6000-builtins.def
+	(__builtin_vsx_scalar_cmp_exp_qp_eq, __builtin_vsx_scalar_cmp_exp_qp_gt
+	__builtin_vsx_scalar_cmp_exp_qp_lt,
+	__builtin_vsx_scalar_cmp_exp_qp_unordered): Move from stanza ieee128-hw
+	to power9-vector.
+
+2023-05-09  Kewen Lin  <linkw@linux.ibm.com>
+
+	Backported from master:
+	2023-04-26  Kewen Lin  <linkw@linux.ibm.com>
+
+	PR target/109069
+	* config/rs6000/altivec.md (sldoi_to_mov<mode>): Replace predicate
+	easy_vector_constant with const_vector_each_byte_same, add
+	handlings in preparation for !easy_vector_constant, and update
+	VECTOR_UNIT_ALTIVEC_OR_VSX_P with VECTOR_MEM_ALTIVEC_OR_VSX_P.
+	* config/rs6000/predicates.md (const_vector_each_byte_same): New
+	predicate.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
--- a/src/gcc/DATESTAMP
+++ b/src/gcc/DATESTAMP
@@ -1 +1 @@
-20230508
+20230611
--- a/src/gcc/c-family/ChangeLog
+++ b/src/gcc/c-family/ChangeLog
@@ -1,3 +1,22 @@
+2023-05-19  Patrick Palka  <ppalka@redhat.com>
+
+	Backported from master:
+	2023-05-15  Patrick Palka  <ppalka@redhat.com>
+
+	* c-cppbuiltin.cc (c_cpp_builtins): Predefine __cpp_auto_cast
+	for C++23.
+
+2023-05-09  Martin Uecker  <uecker@tugraz.at>
+
+	Backported from master:
+	2023-02-18  Martin Uecker  <uecker@tugraz.at>
+
+	PR c/105660
+	* c-attribs.cc (append_access_attr): Use order of arguments when
+	construction string.
+	(append_access_attr_idxs): Rename and make static.
+	* c-warn.cc (warn_parm_array_mismatch): Add assertion.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
--- a/src/gcc/c-family/c-attribs.cc
+++ b/src/gcc/c-family/c-attribs.cc
@@ -4624,22 +4624,27 @@ append_access_attr (tree node[3], tree attrs, const char *attrstr,
   rdwr_map cur_idxs;
   init_attr_rdwr_indices (&cur_idxs, attrs);
 
+  tree args = TYPE_ARG_TYPES (node[0]);
+  int argpos = 0;
   std::string spec;
-  for (auto it = new_idxs.begin (); it != new_idxs.end (); ++it)
+  for (tree arg = args; arg; arg = TREE_CHAIN (arg), argpos++)
     {
-      const auto &newaxsref = *it;
+      const attr_access* const newa = new_idxs.get (argpos);
+
+      if (!newa)
+	continue;
 
       /* The map has two equal entries for each pointer argument that
 	 has an associated size argument.  Process just the entry for
 	 the former.  */
-      if ((unsigned)newaxsref.first != newaxsref.second.ptrarg)
+      if ((unsigned)argpos != newa->ptrarg)
 	continue;
 
-      const attr_access* const cura = cur_idxs.get (newaxsref.first);
+      const attr_access* const cura = cur_idxs.get (argpos);
       if (!cura)
 	{
 	  /* The new attribute needs to be added.  */
-	  tree str = newaxsref.second.to_internal_string ();
+	  tree str = newa->to_internal_string ();
 	  spec += TREE_STRING_POINTER (str);
 	  continue;
 	}
@@ -4647,7 +4652,6 @@ append_access_attr (tree node[3], tree attrs, const char *attrstr,
       /* The new access spec refers to an array/pointer argument for
 	 which an access spec already exists.  Check and diagnose any
 	 conflicts.  If no conflicts are found, merge the two.  */
-      const attr_access* const newa = &newaxsref.second;
 
       if (!attrstr)
 	{
@@ -4782,7 +4786,7 @@ append_access_attr (tree node[3], tree attrs, const char *attrstr,
 	continue;
 
       /* Merge the CURA and NEWA.  */
-      attr_access merged = newaxsref.second;
+      attr_access merged = *newa;
 
       /* VLA seen in a declaration takes precedence.  */
       if (cura->minsize == HOST_WIDE_INT_M1U)
@@ -4808,9 +4812,9 @@ append_access_attr (tree node[3], tree attrs, const char *attrstr,
 
 /* Convenience wrapper for the above.  */
 
-tree
-append_access_attr (tree node[3], tree attrs, const char *attrstr,
-		    char code, HOST_WIDE_INT idxs[2])
+static tree
+append_access_attr_idxs (tree node[3], tree attrs, const char *attrstr,
+			 char code, HOST_WIDE_INT idxs[2])
 {
   char attrspec[80];
   int n = sprintf (attrspec, "%c%u", code, (unsigned) idxs[0] - 1);
@@ -5101,7 +5105,7 @@ handle_access_attribute (tree node[3], tree name, tree args, int flags,
      attributes specified on previous declarations of the same type
      and if not, concatenate the two.  */
   const char code = attr_access::mode_chars[mode];
-  tree new_attrs = append_access_attr (node, attrs, attrstr, code, idxs);
+  tree new_attrs = append_access_attr_idxs (node, attrs, attrstr, code, idxs);
   if (!new_attrs)
     return NULL_TREE;
 
@@ -5114,7 +5118,7 @@ handle_access_attribute (tree node[3], tree name, tree args, int flags,
     {
       /* Repeat for the previously declared type.  */
       attrs = TYPE_ATTRIBUTES (TREE_TYPE (node[1]));
-      new_attrs = append_access_attr (node, attrs, attrstr, code, idxs);
+      new_attrs = append_access_attr_idxs (node, attrs, attrstr, code, idxs);
       if (!new_attrs)
 	return NULL_TREE;
 
--- a/src/gcc/c-family/c-cppbuiltin.cc
+++ b/src/gcc/c-family/c-cppbuiltin.cc
@@ -1080,6 +1080,7 @@ c_cpp_builtins (cpp_reader *pfile)
 	  cpp_define (pfile, "__cpp_if_consteval=202106L");
 	  cpp_define (pfile, "__cpp_constexpr=202110L");
 	  cpp_define (pfile, "__cpp_multidimensional_subscript=202110L");
+	  cpp_define (pfile, "__cpp_auto_cast=202110L");
 	}
       if (flag_concepts)
         {
--- a/src/gcc/c-family/c-warn.cc
+++ b/src/gcc/c-family/c-warn.cc
@@ -3628,6 +3628,8 @@ warn_parm_array_mismatch (location_t origloc, tree fndecl, tree newparms)
       for (tree newvbl = newa->size, curvbl = cura->size; newvbl;
 	   newvbl = TREE_CHAIN (newvbl), curvbl = TREE_CHAIN (curvbl))
 	{
+	  gcc_assert (curvbl);
+
 	  tree newpos = TREE_PURPOSE (newvbl);
 	  tree curpos = TREE_PURPOSE (curvbl);
 
--- a/src/gcc/config/arm/arm-builtins.cc
+++ b/src/gcc/config/arm/arm-builtins.cc
@@ -97,7 +97,7 @@ arm_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
 /* T (T, unsigned immediate).  */
 static enum arm_type_qualifiers
 arm_sat_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-  = { qualifier_unsigned, qualifier_none, qualifier_unsigned_immediate };
+  = { qualifier_none, qualifier_none, qualifier_unsigned_immediate };
 #define SAT_BINOP_UNSIGNED_IMM_QUALIFIERS \
   (arm_sat_binop_imm_qualifiers)
 
--- a/src/gcc/config/arm/arm.md
+++ b/src/gcc/config/arm/arm.md
@@ -7466,7 +7466,7 @@ (define_expand "movdf"
       && !arm_const_double_rtx (operands[1])
       && !(TARGET_VFP_DOUBLE && vfp3_const_double_rtx (operands[1])))
     {
-      rtx clobreg = gen_reg_rtx (DFmode);
+      rtx clobreg = gen_reg_rtx (DImode);
       emit_insn (gen_no_literal_pool_df_immediate (operands[0], operands[1],
 						   clobreg));
       DONE;
--- a/src/gcc/config/arm/arm_mve.h
+++ b/src/gcc/config/arm/arm_mve.h
@@ -9675,42 +9675,42 @@ __arm_vabdq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pr
 
 __extension__ extern __inline int8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p)
 {
   return __builtin_mve_vaddq_m_n_sv16qi (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
 {
   return __builtin_mve_vaddq_m_n_sv4si (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p)
 {
   return __builtin_mve_vaddq_m_n_sv8hi (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
 {
   return __builtin_mve_vaddq_m_n_uv16qi (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
 {
   return __builtin_mve_vaddq_m_n_uv4si (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
 {
   return __builtin_mve_vaddq_m_n_uv8hi (__inactive, __a, __b, __p);
 }
@@ -16055,7 +16055,7 @@ __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vadcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   int32x4_t __res = __builtin_mve_vadcq_sv4si (__a, __b);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16065,7 +16065,7 @@ __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vadcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   uint32x4_t __res = __builtin_mve_vadcq_uv4si (__a, __b);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16075,7 +16075,7 @@ __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vadcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   int32x4_t __res = __builtin_mve_vadcq_m_sv4si (__inactive, __a, __b, __p);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16085,7 +16085,7 @@ __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vadcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   uint32x4_t __res =  __builtin_mve_vadcq_m_uv4si (__inactive, __a, __b, __p);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16131,7 +16131,7 @@ __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vsbcq_s32 (int32x4_t __a, int32x4_t __b, unsigned * __carry)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   int32x4_t __res = __builtin_mve_vsbcq_sv4si (__a, __b);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16141,7 +16141,7 @@ __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vsbcq_u32 (uint32x4_t __a, uint32x4_t __b, unsigned * __carry)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   uint32x4_t __res =  __builtin_mve_vsbcq_uv4si (__a, __b);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16151,7 +16151,7 @@ __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vsbcq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, unsigned * __carry, mve_pred16_t __p)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   int32x4_t __res = __builtin_mve_vsbcq_m_sv4si (__inactive, __a, __b, __p);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16161,7 +16161,7 @@ __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vsbcq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, unsigned * __carry, mve_pred16_t __p)
 {
-  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | (*__carry << 29));
+  __builtin_arm_set_fpscr_nzcvqc((__builtin_arm_get_fpscr_nzcvqc () & ~0x20000000u) | ((*__carry & 0x1u) << 29));
   uint32x4_t __res = __builtin_mve_vsbcq_m_uv4si (__inactive, __a, __b, __p);
   *__carry = (__builtin_arm_get_fpscr_nzcvqc () >> 29) & 0x1u;
   return __res;
@@ -16171,14 +16171,14 @@ __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_u8 (uint8_t * __addr, uint8x16_t __value, mve_pred16_t __p)
 {
-  return vstrbq_p_u8 (__addr, __value, __p);
+  return __arm_vstrbq_p_u8 (__addr, __value, __p);
 }
 
 __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_s8 (int8_t * __addr, int8x16_t __value, mve_pred16_t __p)
 {
-  return vstrbq_p_s8 (__addr, __value, __p);
+  return __arm_vstrbq_p_s8 (__addr, __value, __p);
 }
 
 __extension__ extern __inline void
@@ -16203,14 +16203,14 @@ __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_u8 (uint8_t const *__base, mve_pred16_t __p)
 {
-  return vldrbq_z_u8 ( __base, __p);
+  return __arm_vldrbq_z_u8 ( __base, __p);
 }
 
 __extension__ extern __inline int8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_s8 (int8_t const *__base, mve_pred16_t __p)
 {
-  return vldrbq_z_s8 ( __base, __p);
+  return __arm_vldrbq_z_s8 ( __base, __p);
 }
 
 __extension__ extern __inline int8x16x2_t
@@ -16253,14 +16253,14 @@ __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_u16 (uint16_t * __addr, uint16x8_t __value, mve_pred16_t __p)
 {
-  return vstrhq_p_u16 (__addr, __value, __p);
+  return __arm_vstrhq_p_u16 (__addr, __value, __p);
 }
 
 __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_s16 (int16_t * __addr, int16x8_t __value, mve_pred16_t __p)
 {
-  return vstrhq_p_s16 (__addr, __value, __p);
+  return __arm_vstrhq_p_s16 (__addr, __value, __p);
 }
 
 __extension__ extern __inline void
@@ -16285,14 +16285,14 @@ __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_u16 (uint16_t const *__base, mve_pred16_t __p)
 {
-  return vldrhq_z_u16 ( __base, __p);
+  return __arm_vldrhq_z_u16 ( __base, __p);
 }
 
 __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_s16 (int16_t const *__base, mve_pred16_t __p)
 {
-  return vldrhq_z_s16 ( __base, __p);
+  return __arm_vldrhq_z_s16 ( __base, __p);
 }
 
 __extension__ extern __inline int16x8x2_t
@@ -16335,14 +16335,14 @@ __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_u32 (uint32_t * __addr, uint32x4_t __value, mve_pred16_t __p)
 {
-  return vstrwq_p_u32 (__addr, __value, __p);
+  return __arm_vstrwq_p_u32 (__addr, __value, __p);
 }
 
 __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_s32 (int32_t * __addr, int32x4_t __value, mve_pred16_t __p)
 {
-  return vstrwq_p_s32 (__addr, __value, __p);
+  return __arm_vstrwq_p_s32 (__addr, __value, __p);
 }
 
 __extension__ extern __inline void
@@ -16367,14 +16367,14 @@ __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_u32 (uint32_t const *__base, mve_pred16_t __p)
 {
-  return vldrwq_z_u32 ( __base, __p);
+  return __arm_vldrwq_z_u32 ( __base, __p);
 }
 
 __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_s32 (int32_t const *__base, mve_pred16_t __p)
 {
-  return vldrwq_z_s32 ( __base, __p);
+  return __arm_vldrwq_z_s32 ( __base, __p);
 }
 
 __extension__ extern __inline int32x4x2_t
@@ -19837,7 +19837,7 @@ __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_f16 (float16_t const *__base, mve_pred16_t __p)
 {
-  return vldrhq_z_f16 (__base, __p);
+  return __arm_vldrhq_z_f16 (__base, __p);
 }
 
 __extension__ extern __inline void
@@ -19853,7 +19853,7 @@ __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_f16 (float16_t * __addr, float16x8_t __value, mve_pred16_t __p)
 {
-  return vstrhq_p_f16 (__addr, __value, __p);
+  return __arm_vstrhq_p_f16 (__addr, __value, __p);
 }
 
 __extension__ extern __inline float32x4x4_t
@@ -19878,7 +19878,7 @@ __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vld1q_z_f32 (float32_t const *__base, mve_pred16_t __p)
 {
-  return vldrwq_z_f32 (__base, __p);
+  return __arm_vldrwq_z_f32 (__base, __p);
 }
 
 __extension__ extern __inline void
@@ -19894,7 +19894,7 @@ __extension__ extern __inline void
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vst1q_p_f32 (float32_t * __addr, float32x4_t __value, mve_pred16_t __p)
 {
-  return vstrwq_p_f32 (__addr, __value, __p);
+  return __arm_vstrwq_p_f32 (__addr, __value, __p);
 }
 
 __extension__ extern __inline float16x8_t
@@ -26417,42 +26417,42 @@ __arm_vabdq_m (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16
 
 __extension__ extern __inline int8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m (int8x16_t __inactive, int8x16_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p)
 {
  return __arm_vaddq_m_n_s8 (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m (int32x4_t __inactive, int32x4_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p)
 {
  return __arm_vaddq_m_n_s32 (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m (int16x8_t __inactive, int16x8_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p)
 {
  return __arm_vaddq_m_n_s16 (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m (uint8x16_t __inactive, uint8x16_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
 {
  return __arm_vaddq_m_n_u8 (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m (uint32x4_t __inactive, uint32x4_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
 {
  return __arm_vaddq_m_n_u32 (__inactive, __a, __b, __p);
 }
 
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m (uint16x8_t __inactive, uint16x8_t __a, int __b, mve_pred16_t __p)
+__arm_vaddq_m (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
 {
  return __arm_vaddq_m_n_u16 (__inactive, __a, __b, __p);
 }
@@ -35582,13 +35582,29 @@ enum {
 	short: __ARM_mve_type_int_n, \
 	int: __ARM_mve_type_int_n, \
 	long: __ARM_mve_type_int_n, \
-	double: __ARM_mve_type_fp_n, \
 	long long: __ARM_mve_type_int_n, \
+	_Float16: __ARM_mve_type_fp_n, \
+	__fp16: __ARM_mve_type_fp_n, \
+	float: __ARM_mve_type_fp_n, \
+	double: __ARM_mve_type_fp_n, \
 	unsigned char: __ARM_mve_type_int_n, \
 	unsigned short: __ARM_mve_type_int_n, \
 	unsigned int: __ARM_mve_type_int_n, \
 	unsigned long: __ARM_mve_type_int_n, \
 	unsigned long long: __ARM_mve_type_int_n, \
+	signed char*: __ARM_mve_type_int8_t_ptr, \
+	short*: __ARM_mve_type_int16_t_ptr, \
+	int*: __ARM_mve_type_int32_t_ptr, \
+	long*: __ARM_mve_type_int32_t_ptr, \
+	long long*: __ARM_mve_type_int64_t_ptr, \
+	_Float16*: __ARM_mve_type_float16_t_ptr, \
+	__fp16*: __ARM_mve_type_float16_t_ptr, \
+	float*: __ARM_mve_type_float32_t_ptr, \
+	unsigned char*: __ARM_mve_type_uint8_t_ptr, \
+	unsigned short*: __ARM_mve_type_uint16_t_ptr, \
+	unsigned int*: __ARM_mve_type_uint32_t_ptr, \
+	unsigned long*: __ARM_mve_type_uint32_t_ptr, \
+	unsigned long long*: __ARM_mve_type_uint64_t_ptr, \
 	default: __ARM_mve_unsupported_type))
 #else
 #define __ARM_mve_typeid(x) _Generic(x, \
@@ -35647,30 +35663,67 @@ enum {
 	unsigned int: __ARM_mve_type_int_n, \
 	unsigned long: __ARM_mve_type_int_n, \
 	unsigned long long: __ARM_mve_type_int_n, \
+	signed char*: __ARM_mve_type_int8_t_ptr, \
+	short*: __ARM_mve_type_int16_t_ptr, \
+	int*: __ARM_mve_type_int32_t_ptr, \
+	long*: __ARM_mve_type_int32_t_ptr, \
+	long long*: __ARM_mve_type_int64_t_ptr, \
+	unsigned char*: __ARM_mve_type_uint8_t_ptr, \
+	unsigned short*: __ARM_mve_type_uint16_t_ptr, \
+	unsigned int*: __ARM_mve_type_uint32_t_ptr, \
+	unsigned long*: __ARM_mve_type_uint32_t_ptr, \
+	unsigned long long*: __ARM_mve_type_uint64_t_ptr, \
 	default: __ARM_mve_unsupported_type))
 #endif /* MVE Floating point.  */
 
 extern void *__ARM_undef;
 #define __ARM_mve_coerce(param, type) \
     _Generic(param, type: param, default: *(type *)__ARM_undef)
-#define __ARM_mve_coerce1(param, type) \
-    _Generic(param, type: param, const type: param, default: *(type *)__ARM_undef)
-#define __ARM_mve_coerce2(param, type) \
-    _Generic(param, type: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef)
+#define __ARM_mve_coerce_i_scalar(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef))
+
+#define __ARM_mve_coerce_s8_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, signed char*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_u8_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, unsigned char*: param, default: *(type *)__ARM_undef))
+
+#define __ARM_mve_coerce_s16_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, short*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_u16_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, unsigned short*: param, default: *(type *)__ARM_undef))
+
+#define __ARM_mve_coerce_s32_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, int*: param, long*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_u32_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, unsigned int*: param, unsigned long*: param, default: *(type *)__ARM_undef))
+
+#define __ARM_mve_coerce_s64_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, long long*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_u64_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, unsigned long long*: param, default: *(type *)__ARM_undef))
+
+#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */
+#define __ARM_mve_coerce_f_scalar(param, type) \
+    _Generic(param, type: param, const type: param, __fp16: param, default: _Generic (param, _Float16: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_f16_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, __fp16*: param, _Float16*: param, default: *(type *)__ARM_undef))
+#define __ARM_mve_coerce_f32_ptr(param, type) \
+    _Generic(param, type: param, const type: param, default: _Generic (param, float*: param, default: *(type *)__ARM_undef))
+#endif
 
 #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */
 
 #define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce_f16_ptr(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));})
 
 #define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -35847,6 +35900,10 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));})
 
@@ -35871,16 +35928,16 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_f16 (__ARM_mve_coerce(p0, float16x8_t), __ARM_mve_coerce(p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_f32 (__ARM_mve_coerce(p0, float32x4_t), __ARM_mve_coerce(p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
 
 #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -35897,10 +35954,10 @@ extern void *__ARM_undef;
 #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1 (__p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1 (__p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1 (__p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1 (__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -35925,14 +35982,14 @@ extern void *__ARM_undef;
 #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -35957,14 +36014,14 @@ extern void *__ARM_undef;
 #define __arm_vcmpeqq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -35995,16 +36052,16 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));})
 
 #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36012,13 +36069,13 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
 
 #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36028,11 +36085,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
 
 #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36040,25 +36097,25 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
 
 #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36113,8 +36170,8 @@ extern void *__ARM_undef;
 #define __arm_vmaxnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vmaxnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36125,14 +36182,14 @@ extern void *__ARM_undef;
 #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vminnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36143,8 +36200,8 @@ extern void *__ARM_undef;
 #define __arm_vminnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -36166,14 +36223,14 @@ extern void *__ARM_undef;
 #define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36186,8 +36243,8 @@ extern void *__ARM_undef;
 #define __arm_vminnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -36242,12 +36299,12 @@ extern void *__ARM_undef;
 #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36278,12 +36335,12 @@ extern void *__ARM_undef;
 #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36334,12 +36391,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36347,9 +36404,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vmlaldavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36382,8 +36439,8 @@ extern void *__ARM_undef;
 #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
 
@@ -36396,17 +36453,17 @@ extern void *__ARM_undef;
 #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
 
 #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
@@ -36414,12 +36471,12 @@ extern void *__ARM_undef;
 #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36452,12 +36509,12 @@ extern void *__ARM_undef;
 #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36482,12 +36539,12 @@ extern void *__ARM_undef;
 #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -36630,12 +36687,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36714,44 +36771,44 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-	    int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+	    int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-	    int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+	    int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36941,11 +36998,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
@@ -36957,11 +37014,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));})
 
 #define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36971,11 +37028,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));})
 
 #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -36988,14 +37045,14 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpneq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpneq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2));})
 
 #define __arm_vcvtbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37049,8 +37106,8 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double)), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));})
 
@@ -37065,8 +37122,8 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double)));})
 
 #define __arm_vmaxnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37089,14 +37146,14 @@ extern void *__ARM_undef;
 #define __arm_vmaxnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vmaxnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vminnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37107,14 +37164,14 @@ extern void *__ARM_undef;
 #define __arm_vminnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vminnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vrndnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37176,13 +37233,13 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double)), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double)));})
 
 #define __arm_vrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37283,11 +37340,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce_f_scalar(__p1, double), p2), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
@@ -37316,14 +37373,14 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vandq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37464,15 +37521,15 @@ extern void *__ARM_undef;
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vfmasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vfmsq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37507,14 +37564,14 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37541,14 +37598,14 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vorrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -37565,236 +37622,236 @@ extern void *__ARM_undef;
 
 #define __arm_vld1q(p0) (\
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \
-  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce1(p0, float32_t *))))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \
+  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *))))
 
 #define __arm_vld1q_z(p0,p1) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \
-  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce1(p0, float16_t *), p1), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1)))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \
+  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), p1), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1)))
 
 #define __arm_vld2q(p0) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \
-  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32 (__ARM_mve_coerce1(p0, float32_t *))))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \
+  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld2q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld2q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *))))
 
 #define __arm_vld4q(p0) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \
-  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32 (__ARM_mve_coerce1(p0, float32_t *))))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *)), \
+  int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld4q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *)), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld4q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *))))
 
 #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));})
 
 #define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
 
 #define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t)));})
 
 #define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce1(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2));})
 
 #define __arm_vldrwq_gather_offset(p0,p1) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32 (__ARM_mve_coerce1(p0, float32_t *), p1)))
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1)))
 
 #define __arm_vldrwq_gather_offset_z(p0,p1,p2) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1, p2), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1, p2)))
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1, p2), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_offset_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1, p2)))
 
 #define __arm_vldrwq_gather_shifted_offset(p0,p1) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce1(p0, float32_t *), p1)))
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1)))
 
 #define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ( \
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1, p2), \
-  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1, p2)))
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1, p2), \
+  int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), p1, p2)))
 
 #define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_p_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __arm_vst2q_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x2_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __arm_vst2q_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x2_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x2_t]: __arm_vst2q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x2_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x2_t]: __arm_vst2q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x2_t)));})
 
 #define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vst1q_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vst1q_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t)));})
 
 #define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8_t]: __arm_vstrhq_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, float16x8_t), p2));})
 
 #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
 
 #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
 
 #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
 
 #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
 
 #define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_p_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __ARM_mve_coerce(__p1, float32x4_t)));})
 
 #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
 
 #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
 
 #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t)));})
 
 #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_f16 (__ARM_mve_coerce_f16_ptr(p0, float16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3));})
 
 #define __arm_vstrwq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
@@ -37811,44 +37868,44 @@ extern void *__ARM_undef;
 #define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t)));})
 
 #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce_f32_ptr(__p0, float32_t *), p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
 
 #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
 
 #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
 
 #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
 
 #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
-  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)), \
+  int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_shifted_offset_f32 (__ARM_mve_coerce_f32_ptr(p0, float32_t *), __p1, __ARM_mve_coerce(__p2, float32x4_t)));})
 
 #define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -38021,19 +38078,19 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vandq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
@@ -38156,19 +38213,19 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
@@ -38254,10 +38311,22 @@ extern void *__ARM_undef;
 #define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));})
+  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce_f_scalar(__p2, double), p3), \
+  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce_f_scalar(__p2, double), p3));})
 
 #define __arm_vcmulq_rot90_x(p1,p2,p3)  ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
@@ -38281,16 +38350,16 @@ extern void *__ARM_undef;
 #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce(__p0, int8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce(__p0, int16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int64x2_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint64x2_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
+  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce_f_scalar(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
 #else /* MVE Integer.  */
 
@@ -38306,12 +38375,12 @@ extern void *__ARM_undef;
 
 #define __arm_vst4q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vst4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_vst4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x4_t)), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_vst4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_vst4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));})
 
 #define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -38408,12 +38477,12 @@ extern void *__ARM_undef;
 #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38440,12 +38509,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -38459,12 +38528,12 @@ extern void *__ARM_undef;
 #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38495,12 +38564,12 @@ extern void *__ARM_undef;
 #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38569,12 +38638,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38582,16 +38651,16 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
@@ -38599,12 +38668,12 @@ extern void *__ARM_undef;
 #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38620,7 +38689,11 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vorrq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vornq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38635,12 +38708,12 @@ extern void *__ARM_undef;
 #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38715,12 +38788,12 @@ extern void *__ARM_undef;
 #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38745,12 +38818,12 @@ extern void *__ARM_undef;
 #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38800,10 +38873,10 @@ extern void *__ARM_undef;
 #define __arm_vbicq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1 (__p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1 (__p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1 (__p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1 (__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vbicq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar (__p1, int)), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
@@ -38820,12 +38893,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int)));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38856,12 +38929,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vqmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38942,16 +39015,16 @@ extern void *__ARM_undef;
 #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
 
 #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
 
@@ -38961,9 +39034,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38971,9 +39044,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38981,9 +39054,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -38991,20 +39064,20 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
@@ -39029,12 +39102,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
 
 #define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -39144,25 +39217,25 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39225,9 +39298,56 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
+
+
+#define __arm_vcmpgtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
+
+#define __arm_vcmpleq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
+
+#define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
+
+#define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+  __typeof(p1) __p1 = (p1); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
 
 #define __arm_vdupq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39250,23 +39370,23 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39291,9 +39411,9 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int)), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int)));})
 
 #define __arm_vqdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39456,12 +39576,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -39561,12 +39681,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -39594,12 +39714,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -39611,12 +39731,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -39631,12 +39751,12 @@ extern void *__ARM_undef;
 
 #define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vstrwq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
@@ -39645,144 +39765,144 @@ extern void *__ARM_undef;
 
 #define __arm_vld1q(p0) (\
   _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *))))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *))))
 
 #define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vldrwq_gather_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vldrwq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_offset_z_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_offset_z_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vldrwq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vldrwq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce1(__p0, int32_t *), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce1(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vldrwq_gather_shifted_offset_z_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vst1q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vst1q_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vst1q_p_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vst1q_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vst1q_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vst1q_p_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vst1q_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vst1q_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vst2q(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x2_t]: __arm_vst2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x2_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x2_t]: __arm_vst2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8x2_t)), \
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x2_t]: __arm_vst2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4x2_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x2_t]: __arm_vst2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16x2_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x2_t]: __arm_vst2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x2_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x2_t]: __arm_vst2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x2_t)));})
 
 #define __arm_vstrhq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vstrhq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrhq_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrhq_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 
 #define __arm_vstrwq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vstrwq_p(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vstrdq_scatter_base_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
@@ -39797,58 +39917,58 @@ extern void *__ARM_undef;
 #define __arm_vstrhq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vstrhq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrhq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vstrhq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrhq_scatter_shifted_offset_p_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrhq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce_s32_ptr(__p0, int32_t *), p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrwq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vstrwq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), __p1, __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_shifted_offset_p_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), __p1, __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vuninitializedq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -39953,15 +40073,15 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
@@ -40055,15 +40175,15 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
@@ -40147,29 +40267,45 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
 
 #define __arm_vld1q_z(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1)))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), p1), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *), p1), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *), p1), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), p1), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *), p1), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *), p1)))
 
 #define __arm_vld2q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce1(p0, uint32_t *))))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld2q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld2q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld2q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *))))
 
 
 #define __arm_vld4q(p0) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \
-  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \
-  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \
-  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce1(p0, uint32_t *))))
+  int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld4q_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *)), \
+  int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld4q_s16 (__ARM_mve_coerce_s16_ptr(p0, int16_t *)), \
+  int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld4q_s32 (__ARM_mve_coerce_s32_ptr(p0, int32_t *)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld4q_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *)), \
+  int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 (__ARM_mve_coerce_u16_ptr(p0, uint16_t *)), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 (__ARM_mve_coerce_u32_ptr(p0, uint32_t *))))
+
+#define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+  __typeof(p2) __p2 = (p2); \
+  _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vgetq_lane(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -40185,14 +40321,14 @@ extern void *__ARM_undef;
 #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce(__p0, int8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce(__p0, int16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int64x2_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint64x2_t), p2));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2));})
 
 #endif /* MVE Integer.  */
 
@@ -40303,62 +40439,62 @@ extern void *__ARM_undef;
 #define __arm_vdwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_vdwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u16 ((uint32_t) __p1, p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_vdwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_x_n_u32 ((uint32_t) __p1, p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_viwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u8 ((uint32_t) __p1, p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_viwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u16 ((uint32_t) __p1, p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_viwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_x_n_u32 ((uint32_t) __p1, p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_vidupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u8 ((uint32_t) __p1, p2, p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vddupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u8 ((uint32_t) __p1, p2, p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vidupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u16 ((uint32_t) __p1, p2, p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vddupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u16 ((uint32_t) __p1, p2, p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vidupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vidupq_x_n_u32 ((uint32_t) __p1, p2, p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vddupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vddupq_x_n_u32 ((uint32_t) __p1, p2, p3), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vshrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
@@ -40372,12 +40508,12 @@ extern void *__ARM_undef;
 #define __arm_vhaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40402,12 +40538,12 @@ extern void *__ARM_undef;
 #define __arm_vhsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40447,20 +40583,20 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_base_wb_u64 (p0, p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
 
 #define __arm_vldrdq_gather_offset(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64 (__ARM_mve_coerce1(p0, int64_t *), p1), \
-  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1)))
+  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1), \
+  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1)))
 
 #define __arm_vldrdq_gather_offset_z(p0,p1,p2) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64 (__ARM_mve_coerce1(p0, int64_t *), p1, p2), \
-  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1, p2)))
+  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_offset_z_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \
+  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2)))
 
 #define __arm_vldrdq_gather_shifted_offset(p0,p1) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce1(p0, int64_t *), p1), \
-  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1)))
+  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1), \
+  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1)))
 
 #define __arm_vldrdq_gather_shifted_offset_z(p0,p1,p2) ( _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce1(p0, int64_t *), p1, p2), \
-  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce1(p0, uint64_t *), p1, p2)))
+  int (*)[__ARM_mve_type_int64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_s64 (__ARM_mve_coerce_s64_ptr(p0, int64_t *), p1, p2), \
+  int (*)[__ARM_mve_type_uint64_t_ptr]: __arm_vldrdq_gather_shifted_offset_z_u64 (__ARM_mve_coerce_u64_ptr(p0, uint64_t *), p1, p2)))
 
 #define __arm_vadciq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -40516,36 +40652,36 @@ extern void *__ARM_undef;
 
 #define __arm_vldrbq_gather_offset_z(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_z_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vqrdmlahq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vqrdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vqdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vqrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -40646,12 +40782,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40666,9 +40802,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vqrdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -40794,17 +40930,17 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vmlaldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
 
 #define __arm_vmlsldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -40874,10 +41010,10 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmvnq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmvnq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmvnq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce1(__p1, int) , p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1(__p1, int) , p2));})
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int) , p2));})
 
 #define __arm_vorrq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -40943,12 +41079,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -40982,12 +41118,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vmaxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41015,23 +41151,23 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vmlasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41077,12 +41213,12 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
@@ -41094,17 +41230,17 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vqdmulhq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
-  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+  int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
@@ -41115,15 +41251,15 @@ extern void *__ARM_undef;
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));})
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3));})
 
 #define __arm_vqdmulltq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
-  int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+  int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
+  int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_m_n_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce_i_scalar(__p2, int), p3), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_m_s16 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
   int (*)[__ARM_mve_type_int64x2_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_m_s32 (__ARM_mve_coerce(__p0, int64x2_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
 
@@ -41189,9 +41325,9 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
 
 #define __arm_vmullbq_poly_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41202,12 +41338,12 @@ extern void *__ARM_undef;
 
 #define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce1(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_s8(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_s16(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_s32(__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vldrbq_gather_offset_u8(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_u16(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_u32(__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vidupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
  __typeof(p1) __p1 = (p1); \
@@ -41215,9 +41351,9 @@ extern void *__ARM_undef;
  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t) __p1, p2, p3), \
  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t) __p1, p2, p3), \
  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vidupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t) __p1, p2, p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vddupq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
  __typeof(p1) __p1 = (p1); \
@@ -41225,89 +41361,89 @@ extern void *__ARM_undef;
  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), (uint32_t) __p1, p2, p3), \
  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint32_t) __p1, p2, p3), \
  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vddupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t) __p1, p2, p3), \
- int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
- int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3), \
- int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3));})
 
 #define __arm_vidupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u16 ((uint32_t) __p0, p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vidupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u32 ((uint32_t) __p0, p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vidupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vidupq_n_u8 ((uint32_t) __p0, p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vddupq_u16(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u16 ((uint32_t) __p0, p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vddupq_u32(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u32 ((uint32_t) __p0, p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_vddupq_u8(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int_n]: __arm_vddupq_n_u8 ((uint32_t) __p0, p1), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1));})
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1));})
 
 #define __arm_viwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_viwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_viwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce(__p0, uint32_t), p1, (const int) p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, (const int) p2));})
+  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u16 (__ARM_mve_coerce_i_scalar(__p0, int), p1, (const int) p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, (const int) p2));})
 
 #define __arm_viwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u32 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_viwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int_n]: __arm_viwdupq_n_u8 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vdwdupq_m(p0,p1,p2,p3,p4) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdwdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_m_wb_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_u32_ptr(__p1, uint32_t *), p2, p3, p4));})
 
 #define __arm_vdwdupq_u16(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u16 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u16 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vdwdupq_u32(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u32 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u32 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vdwdupq_u8(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \
-  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
+  int (*)[__ARM_mve_type_int_n]: __arm_vdwdupq_n_u8 (__ARM_mve_coerce_i_scalar(__p0, int), p1, p2), \
+  int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8 (__ARM_mve_coerce_u32_ptr(__p0, uint32_t *), p1, p2));})
 
 #define __arm_vshlcq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -41343,14 +41479,14 @@ extern void *__ARM_undef;
 #define __arm_vaddlvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vaddlvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddlvaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddlvaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vaddlvq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -41365,22 +41501,22 @@ extern void *__ARM_undef;
 #define __arm_vaddvaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vaddvaq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vaddvaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vaddvaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vaddvaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vaddvaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vaddvaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vaddvaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vaddvq(p0) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
@@ -41406,9 +41542,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vcmpcsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41416,9 +41552,9 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpcsq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpcsq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2));})
 
 #define __arm_vcmphiq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41426,16 +41562,16 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));})
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int)), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int)));})
 
 #define __arm_vcmphiq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \
+  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
+  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmphiq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce_i_scalar(__p1, int), p2), \
   int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmphiq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
@@ -41532,34 +41668,34 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vmladavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vmladavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaxq_s8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaxq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaxq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaxq_u8 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaxq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaxq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vmladavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41602,17 +41738,17 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_u16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vmlaldavaxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_s16 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));})
 
 #define __arm_vmlaldavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
@@ -41776,22 +41912,22 @@ extern void *__ARM_undef;
 
 #define __arm_vstrbq(p0,p1) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce(p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_s8 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_s16 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_s32 (__ARM_mve_coerce_s8_ptr(p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_u8 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_u16 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_u32 (__ARM_mve_coerce_u8_ptr(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
 #define __arm_vstrbq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16_t]: __arm_vstrbq_p_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16_t), p2), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int16x8_t]: __arm_vstrbq_p_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int16x8_t), p2), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int32x4_t]: __arm_vstrbq_p_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_p_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_p_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_p_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
 #define __arm_vstrdq_scatter_base(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
@@ -41807,61 +41943,61 @@ extern void *__ARM_undef;
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vrmlaldavhaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmlaldavhaq_p_s32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmlaldavhaq_p_u32 (__ARM_mve_coerce_i_scalar(__p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrbq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t)), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t)));})
 
 #define __arm_vstrbq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
-  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
-  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vstrbq_scatter_offset_p_s8 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vstrbq_scatter_offset_p_s16 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+  int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vstrbq_scatter_offset_p_s32 (__ARM_mve_coerce_s8_ptr(__p0, int8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vstrbq_scatter_offset_p_u8 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vstrbq_scatter_offset_p_u16 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+  int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vstrbq_scatter_offset_p_u32 (__ARM_mve_coerce_u8_ptr(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
 
 #define __arm_vstrdq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
-  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
+  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_p_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
+  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_p_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
 
 #define __arm_vstrdq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
+  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_offset_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
+  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_offset_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
 
 #define __arm_vstrdq_scatter_shifted_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
-  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
+  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t), p3), \
+  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_p_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t), p3));})
 
 #define __arm_vstrdq_scatter_shifted_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
+  int (*)[__ARM_mve_type_int64_t_ptr][__ARM_mve_type_int64x2_t]: __arm_vstrdq_scatter_shifted_offset_s64 (__ARM_mve_coerce_s64_ptr(__p0, int64_t *), p1, __ARM_mve_coerce(__p2, int64x2_t)), \
+  int (*)[__ARM_mve_type_uint64_t_ptr][__ARM_mve_type_uint64x2_t]: __arm_vstrdq_scatter_shifted_offset_u64 (__ARM_mve_coerce_u64_ptr(__p0, uint64_t *), p1, __ARM_mve_coerce(__p2, uint64x2_t)));})
 
 #endif /* __cplusplus  */
 #endif /* __ARM_FEATURE_MVE  */
--- a/src/gcc/config/arm/constraints.md
+++ b/src/gcc/config/arm/constraints.md
@@ -102,10 +102,6 @@ (define_constraint "Rg"
        (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2)
 				       || (ival == 4) || (ival == 8))")))
 
-;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
-(define_predicate "mve_vldrd_immediate"
-  (match_test "satisfies_constraint_Ri (op)"))
-
 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
  "The VFP registers @code{s0}-@code{s31}.")
 
@@ -566,6 +562,22 @@ (define_constraint "US"
  (match_code "symbol_ref")
 )
 
+;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
+(define_constraint "Ri"
+  "@internal In Thumb-2 state a constant is multiple of 8 and in range
+   of -/+ 1016 for MVE"
+  (and (match_code "const_int")
+       (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
+		    && ((ival % 8) == 0)")))
+
+;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
+(define_constraint "Rl"
+  "@internal In Thumb-2 state a constant is multiple of 2 and in range
+   of -/+ 252 for MVE"
+  (and (match_code "const_int")
+       (match_test "TARGET_HAVE_MVE && (-252 <= ival) && (ival <= 252)
+		    && ((ival % 2) == 0)")))
+
 (define_memory_constraint "Uz"
  "@internal
   A memory access that is accessible as an LDC/STC operand"
--- a/src/gcc/config/arm/mve.md
+++ b/src/gcc/config/arm/mve.md
@@ -134,7 +134,7 @@ (define_insn "mve_vrndq_m_f<mode>"
 	 VRNDQ_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vrintzt.f%#<V_sz_elem> %q0, %q2"
+  "vpst\;vrintzt.f%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -232,7 +232,7 @@ (define_insn "mve_vrev64q_f<mode>"
 	 VREV64Q_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vrev64.%#<V_sz_elem> %q0, %q1"
+  "vrev64.%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -245,7 +245,7 @@ (define_insn "mve_vnegq_f<mode>"
 	(neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vneg.f%#<V_sz_elem>  %q0, %q1"
+  "vneg.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -259,7 +259,7 @@ (define_insn "mve_vdupq_n_f<mode>"
 	 VDUPQ_N_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vdup.%#<V_sz_elem>   %q0, %1"
+  "vdup.%#<V_sz_elem>\t%q0, %1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -272,7 +272,7 @@ (define_insn "mve_vabsq_f<mode>"
 	(abs:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vabs.f%#<V_sz_elem>  %q0, %q1"
+  "vabs.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -286,7 +286,7 @@ (define_insn "mve_vrev32q_fv8hf"
 	 VREV32Q_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vrev32.16 %q0, %q1"
+  "vrev32.16\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 ;;
@@ -299,7 +299,7 @@ (define_insn "mve_vcvttq_f32_f16v4sf"
 	 VCVTTQ_F32_F16))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtt.f32.f16 %q0, %q1"
+  "vcvtt.f32.f16\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -313,7 +313,7 @@ (define_insn "mve_vcvtbq_f32_f16v4sf"
 	 VCVTBQ_F32_F16))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtb.f32.f16 %q0, %q1"
+  "vcvtb.f32.f16\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -327,7 +327,7 @@ (define_insn "mve_vcvtq_to_f_<supf><mode>"
 	 VCVTQ_TO_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>       %q0, %q1"
+  "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -341,7 +341,7 @@ (define_insn "mve_vrev64q_<supf><mode>"
 	 VREV64Q))
   ]
   "TARGET_HAVE_MVE"
-  "vrev64.%#<V_sz_elem> %q0, %q1"
+  "vrev64.%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -355,7 +355,7 @@ (define_insn "mve_vcvtq_from_f_<supf><mode>"
 	 VCVTQ_FROM_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>       %q0, %q1"
+  "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 ;; [vqnegq_s])
@@ -367,7 +367,7 @@ (define_insn "mve_vqnegq_s<mode>"
 	 VQNEGQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vqneg.s%#<V_sz_elem> %q0, %q1"
+  "vqneg.s%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -381,7 +381,7 @@ (define_insn "mve_vqabsq_s<mode>"
 	 VQABSQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vqabs.s%#<V_sz_elem> %q0, %q1"
+  "vqabs.s%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -394,7 +394,7 @@ (define_insn "mve_vnegq_s<mode>"
 	(neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "vneg.s%#<V_sz_elem>  %q0, %q1"
+  "vneg.s%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -428,7 +428,7 @@ (define_insn "mve_vdupq_n_<supf><mode>"
 	 VDUPQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vdup.%#<V_sz_elem>   %q0, %1"
+  "vdup.%#<V_sz_elem>\t%q0, %1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -441,7 +441,7 @@ (define_insn "@mve_vclzq_s<mode>"
 	(clz:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "vclz.i%#<V_sz_elem>  %q0, %q1"
+  "vclz.i%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 (define_expand "mve_vclzq_u<mode>"
@@ -462,7 +462,7 @@ (define_insn "mve_vclsq_s<mode>"
 	 VCLSQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vcls.s%#<V_sz_elem>  %q0, %q1"
+  "vcls.s%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -517,7 +517,7 @@ (define_insn "mve_vmovltq_<supf><mode>"
 	 VMOVLTQ))
   ]
   "TARGET_HAVE_MVE"
-  "vmovlt.<supf>%#<V_sz_elem>   %q0, %q1"
+  "vmovlt.<supf>%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -531,7 +531,7 @@ (define_insn "mve_vmovlbq_<supf><mode>"
 	 VMOVLBQ))
   ]
   "TARGET_HAVE_MVE"
-  "vmovlb.<supf>%#<V_sz_elem>   %q0, %q1"
+  "vmovlb.<supf>%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -545,7 +545,7 @@ (define_insn "mve_vcvtpq_<supf><mode>"
 	 VCVTPQ))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem>      %q0, %q1"
+  "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -559,7 +559,7 @@ (define_insn "mve_vcvtnq_<supf><mode>"
 	 VCVTNQ))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem>      %q0, %q1"
+  "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -573,7 +573,7 @@ (define_insn "mve_vcvtmq_<supf><mode>"
 	 VCVTMQ))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem>      %q0, %q1"
+  "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -587,7 +587,7 @@ (define_insn "mve_vcvtaq_<supf><mode>"
 	 VCVTAQ))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem>      %q0, %q1"
+  "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -601,7 +601,7 @@ (define_insn "mve_vmvnq_n_<supf><mode>"
 	 VMVNQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vmvn.i%#<V_sz_elem>  %q0, %1"
+  "vmvn.i%#<V_sz_elem>\t%q0, %1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -615,7 +615,7 @@ (define_insn "mve_vrev16q_<supf>v16qi"
 	 VREV16Q))
   ]
   "TARGET_HAVE_MVE"
-  "vrev16.8 %q0, %q1"
+  "vrev16.8\t%q0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -629,7 +629,7 @@ (define_insn "mve_vaddlvq_<supf>v4si"
 	 VADDLVQ))
   ]
   "TARGET_HAVE_MVE"
-  "vaddlv.<supf>32 %Q0, %R0, %q1"
+  "vaddlv.<supf>32\t%Q0, %R0, %q1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -643,7 +643,7 @@ (define_insn "mve_vctp<mode1>qhi"
 	VCTPQ))
   ]
   "TARGET_HAVE_MVE"
-  "vctp.<mode1> %1"
+  "vctp.<mode1>\t%1"
   [(set_attr "type" "mve_move")
 ])
 
@@ -672,7 +672,7 @@ (define_insn "mve_vsubq_n_f<mode>"
 	 VSUBQ_N_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vsub.f<V_sz_elem>  %q0, %q1, %2"
+  "vsub.f<V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -687,7 +687,7 @@ (define_insn "mve_vbrsrq_n_f<mode>"
 	 VBRSRQ_N_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vbrsr.<V_sz_elem>  %q0, %q1, %2"
+  "vbrsr.<V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -716,7 +716,7 @@ (define_insn "mve_vcreateq_f<mode>"
 	 VCREATEQ_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
+  "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -731,7 +731,7 @@ (define_insn "mve_vcreateq_<supf><mode>"
 	 VCREATEQ))
   ]
   "TARGET_HAVE_MVE"
-  "vmov %q0[2], %q0[0], %Q2, %Q1\;vmov %q0[3], %q0[1], %R2, %R1"
+  "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -810,7 +810,7 @@ (define_insn "mve_vaddlvq_p_<supf>v4si"
 	 VADDLVQ_P))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vaddlvt.<supf>32 %Q0, %R0, %q1"
+  "vpst\;vaddlvt.<supf>32\t%Q0, %R0, %q1"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -824,7 +824,7 @@ (define_insn "@mve_vcmp<mve_cmp_op>q_<mode>"
 		    (match_operand:MVE_2 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "vcmp.<mve_cmp_type>%#<V_sz_elem>  <mve_cmp_op>, %q1, %q2"
+  "vcmp.<mve_cmp_type>%#<V_sz_elem>\t<mve_cmp_op>, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -873,7 +873,7 @@ (define_insn "mve_vaddq_n_<supf><mode>"
 	 VADDQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vadd.i%#<V_sz_elem>	%q0, %q1, %2"
+  "vadd.i%#<V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -888,7 +888,7 @@ (define_insn "mve_vaddvaq_<supf><mode>"
 	 VADDVAQ))
   ]
   "TARGET_HAVE_MVE"
-  "vaddva.<supf>%#<V_sz_elem>	%0, %q2"
+  "vaddva.<supf>%#<V_sz_elem>\t%0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -969,7 +969,7 @@ (define_insn "mve_vbrsrq_n_<supf><mode>"
 	 VBRSRQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vbrsr.%#<V_sz_elem>	%q0, %q1, %2"
+  "vbrsr.%#<V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1828,7 +1828,7 @@ (define_insn "mve_vaddlvaq_<supf>v4si"
 	 VADDLVAQ))
   ]
   "TARGET_HAVE_MVE"
-  "vaddlva.<supf>32 %Q0, %R0, %q2"
+  "vaddlva.<supf>32\t%Q0, %R0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1843,7 +1843,7 @@ (define_insn "mve_vaddq_n_f<mode>"
 	 VADDQ_N_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vadd.f%#<V_sz_elem>	%q0, %q1, %2"
+  "vadd.f%#<V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1857,7 +1857,7 @@ (define_insn "mve_vandq_f<mode>"
 		   (match_operand:MVE_0 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vand %q0, %q1, %q2"
+  "vand\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1871,7 +1871,7 @@ (define_insn "mve_vbicq_f<mode>"
 			      (match_operand:MVE_0 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vbic %q0, %q1, %q2"
+  "vbic\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1886,7 +1886,7 @@ (define_insn "mve_vbicq_n_<supf><mode>"
 	 VBICQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vbic.i%#<V_sz_elem>	%q0, %2"
+  "vbic.i%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1960,7 +1960,7 @@ (define_insn "mve_vctp<mode1>q_mhi"
 	 VCTPQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vctpt.<mode1> %1"
+  "vpst\;vctpt.<mode1>\t%1"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -1975,7 +1975,7 @@ (define_insn "mve_vcvtbq_f16_f32v8hf"
 	 VCVTBQ_F16_F32))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtb.f16.f32 %q0, %q2"
+  "vcvtb.f16.f32\t%q0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1990,7 +1990,7 @@ (define_insn "mve_vcvttq_f16_f32v8hf"
 	 VCVTTQ_F16_F32))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vcvtt.f16.f32 %q0, %q2"
+  "vcvtt.f16.f32\t%q0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2004,7 +2004,7 @@ (define_insn "mve_veorq_f<mode>"
 		   (match_operand:MVE_0 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "veor %q0, %q1, %q2"
+  "veor\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2152,7 +2152,7 @@ (define_insn "mve_vmlaldavxq_s<mode>"
 	 VMLALDAVXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vmlaldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "vmlaldavx.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2167,7 +2167,7 @@ (define_insn "mve_vmlsldavq_s<mode>"
 	 VMLSLDAVQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vmlsldav.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "vmlsldav.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2182,7 +2182,7 @@ (define_insn "mve_vmlsldavxq_s<mode>"
 	 VMLSLDAVXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vmlsldavx.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "vmlsldavx.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2255,7 +2255,7 @@ (define_insn "mve_vornq_f<mode>"
 		   (match_operand:MVE_0 1 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vorn %q0, %q1, %q2"
+  "vorn\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2269,7 +2269,7 @@ (define_insn "mve_vorrq_f<mode>"
 		   (match_operand:MVE_0 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vorr %q0, %q1, %q2"
+  "vorr\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2419,7 +2419,7 @@ (define_insn "mve_vrmlaldavhxq_sv4si"
 	 VRMLALDAVHXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2"
+  "vrmlaldavhx.s32\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2538,7 +2538,7 @@ (define_insn "mve_vrmlaldavhq_<supf>v4si"
 	 VRMLALDAVHQ))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2"
+  "vrmlaldavh.<supf>32\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2554,7 +2554,7 @@ (define_insn "mve_vbicq_m_n_<supf><mode>"
 	 VBICQ_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vbict.i%#<V_sz_elem>	%q0, %2"
+  "vpst\;vbict.i%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 ;;
@@ -2599,7 +2599,7 @@ (define_insn "mve_vcvtq_m_to_f_<supf><mode>"
 	 VCVTQ_M_TO_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>	 %q0, %q2"
+  "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 ;;
@@ -2644,7 +2644,7 @@ (define_insn "mve_vrmlaldavhaq_<supf>v4si"
 	 VRMLALDAVHAQ))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlaldavha.<supf>32 %Q0, %R0, %q2, %q3"
+  "vrmlaldavha.<supf>32\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2707,7 +2707,7 @@ (define_insn "mve_vshlcq_<supf><mode>"
 		   (match_dup 4)]
 	VSHLCQ))]
  "TARGET_HAVE_MVE"
- "vshlc %q0, %1, %4")
+ "vshlc\t%q0, %1, %4")
 
 ;;
 ;; [vabsq_m_s])
@@ -3041,7 +3041,7 @@ (define_insn "mve_vdupq_m_n_<supf><mode>"
 	 VDUPQ_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vdupt.%#<V_sz_elem>	%q0, %2"
+  "vpst\;vdupt.%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3265,7 +3265,7 @@ (define_insn "mve_vmvnq_m_<supf><mode>"
 	 VMVNQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmvnt %q0, %q2"
+  "vpst\;vmvnt\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3297,7 +3297,7 @@ (define_insn "@mve_vpselq_<supf><mode>"
 	 VPSELQ))
   ]
   "TARGET_HAVE_MVE"
-  "vpsel %q0, %q1, %q2"
+  "vpsel\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -3498,7 +3498,7 @@ (define_insn "mve_vqshlq_m_r_<supf><mode>"
 ;;
 (define_insn "mve_vrev64q_m_<supf><mode>"
   [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_2 0 "s_register_operand" "=&w")
 	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
 		       (match_operand:MVE_2 2 "s_register_operand" "w")
 		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
@@ -3712,7 +3712,7 @@ (define_insn "mve_vaddlvaq_p_<supf>v4si"
 	 VADDLVAQ_P))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vaddlvat.<supf>32 %Q0, %R0, %q2"
+  "vpst\;vaddlvat.<supf>32\t%Q0, %R0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 ;;
@@ -3922,7 +3922,7 @@ (define_insn "mve_vcvtbq_m_f16_f32v8hf"
 	 VCVTBQ_M_F16_F32))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvtbt.f16.f32 %q0, %q2"
+  "vpst\;vcvtbt.f16.f32\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3938,7 +3938,7 @@ (define_insn "mve_vcvtbq_m_f32_f16v4sf"
 	 VCVTBQ_M_F32_F16))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvtbt.f32.f16 %q0, %q2"
+  "vpst\;vcvtbt.f32.f16\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3954,7 +3954,7 @@ (define_insn "mve_vcvttq_m_f16_f32v8hf"
 	 VCVTTQ_M_F16_F32))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvttt.f16.f32 %q0, %q2"
+  "vpst\;vcvttt.f16.f32\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3970,7 +3970,7 @@ (define_insn "mve_vcvttq_m_f32_f16v4sf"
 	 VCVTTQ_M_F32_F16))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vcvttt.f32.f16 %q0, %q2"
+  "vpst\;vcvttt.f32.f16\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3986,7 +3986,7 @@ (define_insn "mve_vdupq_m_n_f<mode>"
 	 VDUPQ_M_N_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vdupt.%#<V_sz_elem>	%q0, %2"
+  "vpst\;vdupt.%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4158,7 +4158,7 @@ (define_insn "mve_vmlaldavaq_<supf><mode>"
 	 VMLALDAVAQ))
   ]
   "TARGET_HAVE_MVE"
-  "vmlaldava.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+  "vmlaldava.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4174,7 +4174,7 @@ (define_insn "mve_vmlaldavaxq_s<mode>"
 	 VMLALDAVAXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vmlaldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+  "vmlaldavax.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4190,7 +4190,7 @@ (define_insn "mve_vmlaldavq_p_<supf><mode>"
 	 VMLALDAVQ_P))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmlaldavt.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "vpst\;vmlaldavt.<supf>%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4221,7 +4221,7 @@ (define_insn "mve_vmlsldavaq_s<mode>"
 	 VMLSLDAVAQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vmlsldava.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+  "vmlsldava.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4237,7 +4237,7 @@ (define_insn "mve_vmlsldavaxq_s<mode>"
 	 VMLSLDAVAXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vmlsldavax.s%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+  "vmlsldavax.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4253,7 +4253,7 @@ (define_insn "mve_vmlsldavq_p_s<mode>"
 	 VMLSLDAVQ_P_S))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmlsldavt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "vpst\;vmlsldavt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4269,7 +4269,7 @@ (define_insn "mve_vmlsldavxq_p_s<mode>"
 	 VMLSLDAVXQ_P_S))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmlsldavxt.s%#<V_sz_elem> %Q0, %R0, %q1, %q2"
+  "vpst\;vmlsldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 ;;
@@ -4346,7 +4346,7 @@ (define_insn "mve_vmvnq_m_n_<supf><mode>"
 	 VMVNQ_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmvnt.i%#<V_sz_elem>	%q0, %2"
+  "vpst\;vmvnt.i%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 ;;
@@ -4377,7 +4377,7 @@ (define_insn "mve_vorrq_m_n_<supf><mode>"
 	 VORRQ_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vorrt.i%#<V_sz_elem>	%q0, %2"
+  "vpst\;vorrt.i%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 ;;
@@ -4392,7 +4392,7 @@ (define_insn "@mve_vpselq_f<mode>"
 	 VPSELQ_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpsel %q0, %q1, %q2"
+  "vpsel\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4568,7 +4568,7 @@ (define_insn "mve_vrev32q_m_fv8hf"
 	 VREV32Q_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vrev32t.16 %q0, %q2"
+  "vpst\;vrev32t.16\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4584,7 +4584,7 @@ (define_insn "mve_vrev32q_m_<supf><mode>"
 	 VREV32Q_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrev32t.%#<V_sz_elem>	%q0, %q2"
+  "vpst\;vrev32t.%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4593,14 +4593,14 @@ (define_insn "mve_vrev32q_m_<supf><mode>"
 ;;
 (define_insn "mve_vrev64q_m_f<mode>"
   [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+   (set (match_operand:MVE_0 0 "s_register_operand" "=&w")
 	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
 		       (match_operand:MVE_0 2 "s_register_operand" "w")
 		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
 	 VREV64Q_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vrev64t.%#<V_sz_elem>	%q0, %q2"
+  "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4616,7 +4616,7 @@ (define_insn "mve_vrmlaldavhaxq_sv4si"
 	 VRMLALDAVHAXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlaldavhax.s32 %Q0, %R0, %q2, %q3"
+  "vrmlaldavhax.s32\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4632,7 +4632,7 @@ (define_insn "mve_vrmlaldavhxq_p_sv4si"
 	 VRMLALDAVHXQ_P_S))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2"
+  "vpst\;vrmlaldavhxt.s32\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4648,7 +4648,7 @@ (define_insn "mve_vrmlsldavhaxq_sv4si"
 	 VRMLSLDAVHAXQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlsldavhax.s32 %Q0, %R0, %q2, %q3"
+  "vrmlsldavhax.s32\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4664,7 +4664,7 @@ (define_insn "mve_vrmlsldavhq_p_sv4si"
 	 VRMLSLDAVHQ_P_S))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2"
+  "vpst\;vrmlsldavht.s32\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4680,7 +4680,7 @@ (define_insn "mve_vrmlsldavhxq_p_sv4si"
 	 VRMLSLDAVHXQ_P_S))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2"
+  "vpst\;vrmlsldavhxt.s32\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4905,7 +4905,7 @@ (define_insn "mve_vrev16q_m_<supf>v16qi"
 	 VREV16Q_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrev16t.8 %q0, %q2"
+  "vpst\;vrev16t.8\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4937,7 +4937,7 @@ (define_insn "mve_vrmlaldavhq_p_<supf>v4si"
 	 VRMLALDAVHQ_P))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vrmlaldavht.<supf>32 %Q0, %R0, %q1, %q2"
+  "vpst\;vrmlaldavht.<supf>32\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -4953,7 +4953,7 @@ (define_insn "mve_vrmlsldavhaq_sv4si"
 	 VRMLSLDAVHAQ_S))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlsldavha.s32 %Q0, %R0, %q2, %q3"
+  "vrmlsldavha.s32\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -4972,7 +4972,7 @@ (define_insn "mve_vabavq_p_<supf><mode>"
   "TARGET_HAVE_MVE"
   "vpst\;vabavt.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
   [(set_attr "type" "mve_move")
-])
+   (set_attr "length" "8")])
 
 ;;
 ;; [vqshluq_m_n_s])
@@ -4988,7 +4988,8 @@ (define_insn "mve_vqshluq_m_n_s<mode>"
   ]
   "TARGET_HAVE_MVE"
   "vpst\n\tvqshlut.s%#<V_sz_elem>\t%q0, %q2, %3"
-  [(set_attr "type" "mve_move")])
+  [(set_attr "type" "mve_move")
+   (set_attr "length" "8")])
 
 ;;
 ;; [vshlq_m_s, vshlq_m_u])
@@ -5004,7 +5005,8 @@ (define_insn "mve_vshlq_m_<supf><mode>"
   ]
   "TARGET_HAVE_MVE"
   "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
-  [(set_attr "type" "mve_move")])
+  [(set_attr "type" "mve_move")
+   (set_attr "length" "8")])
 
 ;;
 ;; [vsriq_m_n_s, vsriq_m_n_u])
@@ -5020,7 +5022,8 @@ (define_insn "mve_vsriq_m_n_<supf><mode>"
   ]
   "TARGET_HAVE_MVE"
   "vpst\;vsrit.%#<V_sz_elem>\t%q0, %q2, %3"
-  [(set_attr "type" "mve_move")])
+  [(set_attr "type" "mve_move")
+   (set_attr "length" "8")])
 
 ;;
 ;; [vsubq_m_u, vsubq_m_s])
@@ -5036,7 +5039,8 @@ (define_insn "mve_vsubq_m_<supf><mode>"
   ]
   "TARGET_HAVE_MVE"
   "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %q3"
-  [(set_attr "type" "mve_move")])
+  [(set_attr "type" "mve_move")
+   (set_attr "length" "8")])
 
 ;;
 ;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s])
@@ -5118,7 +5122,7 @@ (define_insn "mve_vandq_m_<supf><mode>"
 	 VANDQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vandt %q0, %q2, %q3"
+  "vpst\;vandt\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -5135,7 +5139,7 @@ (define_insn "mve_vbicq_m_<supf><mode>"
 	 VBICQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vbict %q0, %q2, %q3"
+  "vpst\;vbict\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -5203,7 +5207,7 @@ (define_insn "mve_veorq_m_<supf><mode>"
 	 VEORQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;veort %q0, %q2, %q3"
+  "vpst\;veort\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -5458,7 +5462,7 @@ (define_insn "mve_vornq_m_<supf><mode>"
 	 VORNQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vornt %q0, %q2, %q3"
+  "vpst\;vornt\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -5475,7 +5479,7 @@ (define_insn "mve_vorrq_m_<supf><mode>"
 	 VORRQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vorrt %q0, %q2, %q3"
+  "vpst\;vorrt\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -6121,7 +6125,7 @@ (define_insn "mve_vmlaldavaxq_p_<supf><mode>"
 	 VMLALDAVAXQ_P))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmlaldavaxt.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3"
+  "vpst\;vmlaldavaxt.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -6647,7 +6651,7 @@ (define_insn "mve_vandq_m_f<mode>"
 	 VANDQ_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vandt %q0, %q2, %q3"
+  "vpst\;vandt\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -6664,7 +6668,7 @@ (define_insn "mve_vbicq_m_f<mode>"
 	 VBICQ_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vbict %q0, %q2, %q3"
+  "vpst\;vbict\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -6868,7 +6872,7 @@ (define_insn "mve_veorq_m_f<mode>"
 	 VEORQ_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;veort %q0, %q2, %q3"
+  "vpst\;veort\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -7021,7 +7025,7 @@ (define_insn "mve_vornq_m_f<mode>"
 	 VORNQ_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vornt %q0, %q2, %q3"
+  "vpst\;vornt\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -7038,7 +7042,7 @@ (define_insn "mve_vorrq_m_f<mode>"
 	 VORRQ_M_F))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vorrt %q0, %q2, %q3"
+  "vpst\;vorrt\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -7265,15 +7269,13 @@ (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si"
 }
   [(set_attr "length" "8")])
 
-;;
-;; [vstrbq_p_s vstrbq_p_u]
-;;
 (define_insn "mve_vstrbq_p_<supf><mode>"
   [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux")
-	(unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")
-			      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
-	 VSTRBQ))
-  ]
+	(unspec:<MVE_B_ELEM>
+	 [(match_operand:MVE_2 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRBQ))]
   "TARGET_HAVE_MVE"
 {
    rtx ops[2];
@@ -8072,10 +8074,11 @@ (define_insn "mve_vstrhq_fv8hf"
 ;;
 (define_insn "mve_vstrhq_p_fv8hf"
   [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux")
-	(unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")
-		      (match_operand:V8BI 2 "vpr_register_operand" "Up")]
-	 VSTRHQ_F))
-  ]
+	(unspec:V8HI
+	 [(match_operand:V8HF 1 "s_register_operand" "w")
+	  (match_operand:V8BI 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRHQ_F))]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 {
    rtx ops[2];
@@ -8092,8 +8095,10 @@ (define_insn "mve_vstrhq_p_fv8hf"
 ;;
 (define_insn "mve_vstrhq_p_<supf><mode>"
   [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux")
-	(unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")
-			      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
+	(unspec:<MVE_H_ELEM>
+	 [(match_operand:MVE_6 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
 	 VSTRHQ))
   ]
   "TARGET_HAVE_MVE"
@@ -8271,10 +8276,11 @@ (define_insn "mve_vstrwq_fv4sf"
 ;;
 (define_insn "mve_vstrwq_p_fv4sf"
   [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
-	(unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")
-		      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
-	 VSTRWQ_F))
-  ]
+	(unspec:V4SI
+	 [(match_operand:V4SF 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRWQ_F))]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 {
    rtx ops[2];
@@ -8291,10 +8297,11 @@ (define_insn "mve_vstrwq_p_fv4sf"
 ;;
 (define_insn "mve_vstrwq_p_<supf>v4si"
   [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
-	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
-		      (match_operand:V4BI 2 "vpr_register_operand" "Up")]
-	 VSTRWQ))
-  ]
+	(unspec:V4SI
+	 [(match_operand:V4SI 1 "s_register_operand" "w")
+	  (match_operand:V4BI 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRWQ))]
   "TARGET_HAVE_MVE"
 {
    rtx ops[2];
@@ -8478,7 +8485,7 @@ (define_insn "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn"
 	   (match_operand:HI 3 "vpr_register_operand" "Up")]
 	  VSTRDSSOQ))]
   "TARGET_HAVE_MVE"
-  "vpst\;vstrdt.64\t%q2, [%0, %q1, UXTW #3]"
+  "vpst\;vstrdt.64\t%q2, [%0, %q1, uxtw #3]"
   [(set_attr "length" "8")])
 
 ;;
@@ -8507,7 +8514,7 @@ (define_insn "mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn"
 	   (match_operand:V2DI 2 "s_register_operand" "w")]
 	  VSTRDSSOQ))]
   "TARGET_HAVE_MVE"
-  "vstrd.64\t%q2, [%0, %q1, UXTW #3]"
+  "vstrd.64\t%q2, [%0, %q1, uxtw #3]"
   [(set_attr "length" "4")])
 
 ;;
@@ -8923,7 +8930,7 @@ (define_insn "mve_vaddq<mode>"
 		    (match_operand:MVE_2 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "vadd.i%#<V_sz_elem>  %q0, %q1, %q2"
+  "vadd.i%#<V_sz_elem>\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -8937,7 +8944,7 @@ (define_insn "mve_vaddq_f<mode>"
 		    (match_operand:MVE_0 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vadd.f%#<V_sz_elem> %q0, %q1, %q2"
+  "vadd.f%#<V_sz_elem>\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -9038,7 +9045,7 @@ (define_insn "mve_vddupq_u<mode>_insn"
        (minus:SI (match_dup 2)
 		 (match_operand:SI 4 "immediate_operand" "i")))]
  "TARGET_HAVE_MVE"
- "vddup.u%#<V_sz_elem>  %q0, %1, %3")
+ "vddup.u%#<V_sz_elem>\t%q0, %1, %3")
 
 ;;
 ;; [vddupq_m_n_u])
@@ -9074,7 +9081,7 @@ (define_insn "mve_vddupq_m_wb_u<mode>_insn"
        (minus:SI (match_dup 3)
 		 (match_operand:SI 6 "immediate_operand" "i")))]
  "TARGET_HAVE_MVE"
- "vpst\;\tvddupt.u%#<V_sz_elem>\t%q0, %2, %4"
+ "vpst\;vddupt.u%#<V_sz_elem>\t%q0, %2, %4"
  [(set_attr "length""8")])
 
 ;;
@@ -9190,7 +9197,7 @@ (define_insn "mve_vdwdupq_m_wb_u<mode>_insn"
 	 VDWDUPQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;\tvdwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5"
+  "vpst\;vdwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -9345,7 +9352,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si"
 		[(match_operand:V4SI 1 "s_register_operand" "0")
 		 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
 		 (match_operand:V4SI 3 "s_register_operand" "w")
-		 (match_operand:V4BI 4 "vpr_register_operand")]
+		 (match_operand:V4BI 4 "vpr_register_operand" "Up")]
 	VSTRWSBWBQ))
    (set (match_operand:V4SI 0 "s_register_operand" "=w")
 	(unspec:V4SI [(match_dup 1) (match_dup 2)]
@@ -9394,9 +9401,9 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf"
  [(set (mem:BLK (scratch))
        (unspec:BLK
 		[(match_operand:V4SI 1 "s_register_operand" "0")
-		 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
+		 (match_operand:SI 2 "mve_vstrw_immediate" "Rl")
 		 (match_operand:V4SF 3 "s_register_operand" "w")
-		 (match_operand:V4BI 4 "vpr_register_operand")]
+		 (match_operand:V4BI 4 "vpr_register_operand" "Up")]
 	VSTRWQSBWB_F))
    (set (match_operand:V4SI 0 "s_register_operand" "=w")
 	(unspec:V4SI [(match_dup 1) (match_dup 2)]
@@ -9408,7 +9415,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf"
    ops[0] = operands[1];
    ops[1] = operands[2];
    ops[2] = operands[3];
-   output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops);
+   output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops);
    return "";
 }
   [(set_attr "length" "8")])
@@ -9447,7 +9454,7 @@ (define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di"
 		[(match_operand:V2DI 1 "s_register_operand" "0")
 		 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
 		 (match_operand:V2DI 3 "s_register_operand" "w")
-		 (match_operand:HI 4 "vpr_register_operand")]
+		 (match_operand:HI 4 "vpr_register_operand" "Up")]
 	 VSTRDSBWBQ))
    (set (match_operand:V2DI 0 "s_register_operand" "=w")
 	(unspec:V2DI [(match_dup 1) (match_dup 2)]
@@ -9459,7 +9466,7 @@ (define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di"
    ops[0] = operands[1];
    ops[1] = operands[2];
    ops[2] = operands[3];
-   output_asm_insn ("vpst;vstrdt.u64\t%q2, [%q0, %1]!",ops);
+   output_asm_insn ("vpst\;vstrdt.u64\t%q2, [%q0, %1]!",ops);
    return "";
 }
   [(set_attr "length" "8")])
@@ -9768,7 +9775,7 @@ (define_expand "mve_vldrdq_gather_base_nowb_z_<supf>v2di"
 
 (define_insn "get_fpscr_nzcvqc"
  [(set (match_operand:SI 0 "register_operand" "=r")
-   (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))]
+   (unspec_volatile:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))]
  "TARGET_HAVE_MVE"
  "vmrs\\t%0, FPSCR_nzcvqc"
   [(set_attr "type" "mve_move")])
--- a/src/gcc/config/arm/predicates.md
+++ b/src/gcc/config/arm/predicates.md
@@ -73,13 +73,13 @@ (define_predicate "mve_imm_32"
 (define_predicate "mve_imm_selective_upto_8"
   (match_test "satisfies_constraint_Rg (op)"))
 
-;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
-(define_constraint "Ri"
-  "@internal In Thumb-2 state a constant is multiple of 8 and in range
-   of -/+ 1016 for MVE"
-  (and (match_code "const_int")
-       (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
-		    && ((ival % 8) == 0)")))
+;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
+(define_predicate "mve_vldrd_immediate"
+  (match_test "satisfies_constraint_Ri (op)"))
+
+;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
+(define_predicate "mve_vstrw_immediate"
+  (match_test "satisfies_constraint_Rl (op)"))
 
 ; Predicate for stack protector guard's address in
 ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns
--- a/src/gcc/config/arm/vfp.md
+++ b/src/gcc/config/arm/vfp.md
@@ -105,9 +105,9 @@ (define_insn "*thumb2_movhi_vfp"
     case 8:
       return "vmov%?.f32\t%0, %1\t%@ int";
     case 9:
-      return "vmsr%?\t P0, %1\t@ movhi";
+      return "vmsr%?\tp0, %1\t@ movhi";
     case 10:
-      return "vmrs%?\t %0, P0\t@ movhi";
+      return "vmrs%?\t%0, p0\t@ movhi";
     default:
       gcc_unreachable ();
     }
@@ -209,9 +209,9 @@ (define_insn "*thumb2_movhi_fp16"
     case 8:
       return "vmov%?.f32\t%0, %1\t%@ int";
     case 9:
-      return "vmsr%?\t P0, %1\t%@ movhi";
+      return "vmsr%?\tp0, %1\t%@ movhi";
     case 10:
-      return "vmrs%?\t%0, P0\t%@ movhi";
+      return "vmrs%?\t%0, p0\t%@ movhi";
     default:
       gcc_unreachable ();
     }
@@ -312,9 +312,9 @@ (define_insn "*thumb2_movsi_vfp"
     case 12: case 13:
       return output_move_vfp (operands);
     case 14:
-      return \"vmsr\\t P0, %1\";
+      return \"vmsr\\tp0, %1\";
     case 15:
-      return \"vmrs\\t %0, P0\";
+      return \"vmrs\\t%0, p0\";
     case 16:
       return \"mcr\\tp10, 7, %1, cr1, cr0, 0\\t @SET_FPSCR\";
     case 17:
@@ -2138,7 +2138,7 @@ (define_insn "get_fpscr"
 (define_insn_and_split "no_literal_pool_df_immediate"
   [(set (match_operand:DF 0 "s_register_operand" "=w")
 	(match_operand:DF 1 "const_double_operand" "F"))
-   (clobber (match_operand:DF 2 "s_register_operand" "=r"))]
+   (clobber (match_operand:DI 2 "s_register_operand" "=r"))]
   "arm_disable_literal_pool
    && TARGET_VFP_BASE
    && !arm_const_double_rtx (operands[1])
@@ -2153,8 +2153,9 @@ (define_insn_and_split "no_literal_pool_df_immediate"
   unsigned HOST_WIDE_INT ival = zext_hwi (buf[order], 32);
   ival |= (zext_hwi (buf[1 - order], 32) << 32);
   rtx cst = gen_int_mode (ival, DImode);
-  emit_move_insn (simplify_gen_subreg (DImode, operands[2], DFmode, 0), cst);
-  emit_move_insn (operands[0], operands[2]);
+  emit_move_insn (operands[2], cst);
+  emit_move_insn (operands[0],
+		  simplify_gen_subreg (DFmode, operands[2], DImode, 0));
   DONE;
 }
 )
--- a/src/gcc/config/avr/avr-dimode.md
+++ b/src/gcc/config/avr/avr-dimode.md
@@ -455,12 +455,18 @@ (define_expand "conditional_jump"
 (define_expand "cbranch<mode>4"
   [(set (pc)
         (if_then_else (match_operator 0 "ordered_comparison_operator"
-                        [(match_operand:ALL8 1 "register_operand"  "")
-                         (match_operand:ALL8 2 "nonmemory_operand" "")])
-         (label_ref (match_operand 3 "" ""))
-         (pc)))]
+                        [(match_operand:ALL8 1 "register_operand")
+                         (match_operand:ALL8 2 "nonmemory_operand")])
+                      (label_ref (match_operand 3))
+                      (pc)))]
   "avr_have_dimode"
    {
+    int icode = (int) GET_CODE (operands[0]);
+
+    targetm.canonicalize_comparison (&icode, &operands[1], &operands[2], false);
+    operands[0] = gen_rtx_fmt_ee ((enum rtx_code) icode,
+                                  VOIDmode, operands[1], operands[2]);
+
     rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
 
     avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
@@ -490,8 +496,8 @@ (define_insn_and_split "cbranch_<mode>2_split"
         (if_then_else (match_operator 0 "ordered_comparison_operator"
                         [(reg:ALL8 ACC_A)
                          (reg:ALL8 ACC_B)])
-         (label_ref (match_operand 1 "" ""))
-         (pc)))]
+                      (label_ref (match_operand 1))
+                      (pc)))]
   "avr_have_dimode"
   "#"
   "&& reload_completed"
@@ -544,8 +550,8 @@ (define_insn_and_split "cbranch_const_<mode>2_split"
         (if_then_else (match_operator 0 "ordered_comparison_operator"
                         [(reg:ALL8 ACC_A)
                          (match_operand:ALL8 1 "const_operand" "n Ynn")])
-         (label_ref (match_operand 2 "" ""))
-         (pc)))
+                      (label_ref (match_operand 2 "" ""))
+                      (pc)))
    (clobber (match_scratch:QI 3 "=&d"))]
   "avr_have_dimode
    && !s8_operand (operands[1], VOIDmode)"
--- a/src/gcc/config/avr/avr-passes.def
+++ b/src/gcc/config/avr/avr-passes.def
@@ -43,3 +43,23 @@ INSERT_PASS_BEFORE (pass_free_cfg, 1, avr_pass_recompute_notes);
    insns withaout any insns in between.  */
 
 INSERT_PASS_AFTER (pass_expand, 1, avr_pass_casesi);
+
+/* If-else decision trees generated for switch / case may produce sequences
+   like
+
+      SREG = compare (reg, val);
+	  if (SREG == 0)  goto label1;
+      SREG = compare (reg, 1 + val);
+	  if (SREG >= 0)  goto label2;
+
+   which can be optimized to
+
+      SREG = compare (reg, val);
+	  if (SREG == 0)  goto label1;
+	  if (SREG >= 0)  goto label2;
+
+   The optimal place for such a pass would be directly after expand, but
+   it's not possible for a jump insn to target more than one code label.
+   Hence, run a mini pass right before split2 which introduces REG_CC.  */
+
+INSERT_PASS_BEFORE (pass_split_after_reload, 1, avr_pass_ifelse);
--- a/src/gcc/config/avr/avr-protos.h
+++ b/src/gcc/config/avr/avr-protos.h
@@ -58,6 +58,8 @@ extern const char *ret_cond_branch (rtx x, int len, int reverse);
 extern const char *avr_out_movpsi (rtx_insn *, rtx*, int*);
 extern const char *avr_out_sign_extend (rtx_insn *, rtx*, int*);
 extern const char *avr_out_insert_notbit (rtx_insn *, rtx*, rtx, int*);
+extern const char *avr_out_plus_set_ZN (rtx*, int*);
+extern const char *avr_out_cmp_ext (rtx*, enum rtx_code, int*);
 
 extern const char *ashlqi3_out (rtx_insn *insn, rtx operands[], int *len);
 extern const char *ashlhi3_out (rtx_insn *insn, rtx operands[], int *len);
@@ -112,8 +114,6 @@ extern int jump_over_one_insn_p (rtx_insn *insn, rtx dest);
 
 extern void avr_final_prescan_insn (rtx_insn *insn, rtx *operand,
 				    int num_operands);
-extern int avr_simplify_comparison_p (machine_mode mode,
-				      RTX_CODE op, rtx x);
 extern RTX_CODE avr_normalize_condition (RTX_CODE condition);
 extern void out_shift_with_cnt (const char *templ, rtx_insn *insn,
 				rtx operands[], int *len, int t_len);
@@ -145,6 +145,7 @@ extern rtx tmp_reg_rtx;
 extern rtx zero_reg_rtx;
 extern rtx all_regs_rtx[32];
 extern rtx rampz_rtx;
+extern rtx cc_reg_rtx;
 
 #endif /* RTX_CODE */
 
@@ -160,6 +161,7 @@ class rtl_opt_pass;
 extern rtl_opt_pass *make_avr_pass_pre_proep (gcc::context *);
 extern rtl_opt_pass *make_avr_pass_recompute_notes (gcc::context *);
 extern rtl_opt_pass *make_avr_pass_casesi (gcc::context *);
+extern rtl_opt_pass *make_avr_pass_ifelse (gcc::context *);
 
 /* From avr-log.cc */
 
--- a/src/gcc/config/avr/avr.cc
+++ b/src/gcc/config/avr/avr.cc
@@ -359,6 +359,41 @@ public:
   }
 }; // avr_pass_casesi
 
+
+static const pass_data avr_pass_data_ifelse =
+{
+  RTL_PASS,      // type
+  "",            // name (will be patched)
+  OPTGROUP_NONE, // optinfo_flags
+  TV_DF_SCAN,    // tv_id
+  0,             // properties_required
+  0,             // properties_provided
+  0,             // properties_destroyed
+  0,             // todo_flags_start
+  TODO_df_finish | TODO_df_verify // todo_flags_finish
+};
+
+class avr_pass_ifelse : public rtl_opt_pass
+{
+public:
+  avr_pass_ifelse (gcc::context *ctxt, const char *name)
+    : rtl_opt_pass (avr_pass_data_ifelse, ctxt)
+  {
+    this->name = name;
+  }
+
+  void avr_rest_of_handle_ifelse (function*);
+
+  virtual bool gate (function*) { return optimize > 0; }
+
+  virtual unsigned int execute (function *func)
+  {
+    avr_rest_of_handle_ifelse (func);
+
+    return 0;
+  }
+}; // avr_pass_ifelse
+
 } // anon namespace
 
 rtl_opt_pass*
@@ -373,6 +408,12 @@ make_avr_pass_casesi (gcc::context *ctxt)
   return new avr_pass_casesi (ctxt, "avr-casesi");
 }
 
+rtl_opt_pass*
+make_avr_pass_ifelse (gcc::context *ctxt)
+{
+  return new avr_pass_ifelse (ctxt, "avr-ifelse");
+}
+
 
 /* Make one parallel insn with all the patterns from insns i[0]..i[5].  */
 
@@ -686,6 +727,304 @@ avr_pass_casesi::avr_rest_of_handle_casesi (function *func)
 }
 
 
+/* A helper for the next method.  Suppose we have two conditional branches
+
+      if (reg <cond1> xval1) goto label1;
+      if (reg <cond2> xval2) goto label2;
+
+   If the second comparison is redundant and there is a code <cond> such
+   that the sequence can be performed as
+
+      REG_CC = compare (reg, xval1);
+      if (REG_CC <cond1> 0)  goto label1;
+      if (REG_CC <cond> 0)   goto label2;
+
+   then return <cond>.  Otherwise, return UNKNOWN.
+   xval1 and xval2 are CONST_INT, and mode is the scalar int mode in which
+   the comparison will be carried out.  reverse_cond1 can be set to reverse
+   condition cond1.  This is useful if the second comparison does not follow
+   the first one, but is located after label1 like in:
+
+      if (reg <cond1> xval1) goto label1;
+      ...
+      label1:
+      if (reg <cond2> xval2) goto label2;  */
+
+static enum rtx_code
+avr_redundant_compare (enum rtx_code cond1, rtx xval1,
+		       enum rtx_code cond2, rtx xval2,
+		       machine_mode mode, bool reverse_cond1)
+{
+  HOST_WIDE_INT ival1 = INTVAL (xval1);
+  HOST_WIDE_INT ival2 = INTVAL (xval2);
+
+  unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
+  unsigned HOST_WIDE_INT uval1 = mask & UINTVAL (xval1);
+  unsigned HOST_WIDE_INT uval2 = mask & UINTVAL (xval2);
+
+  if (reverse_cond1)
+    cond1 = reverse_condition (cond1);
+
+  if (cond1 == EQ)
+    {
+      ////////////////////////////////////////////////
+      // A sequence like
+      //    if (reg == val)  goto label1;
+      //    if (reg > val)   goto label2;
+      // can be re-written using the same, simple comparison like in:
+      //    REG_CC = compare (reg, val)
+      //    if (REG_CC == 0)  goto label1;
+      //    if (REG_CC >= 0)  goto label2;
+      if (ival1 == ival2
+	  && (cond2 == GT || cond2 == GTU))
+	return avr_normalize_condition (cond2);
+
+      // Similar, but the input sequence is like
+      //    if (reg == val)  goto label1;
+      //    if (reg >= val)  goto label2;
+      if (ival1 == ival2
+	  && (cond2 == GE || cond2 == GEU))
+	return cond2;
+
+      // Similar, but the input sequence is like
+      //    if (reg == val)      goto label1;
+      //    if (reg >= val + 1)  goto label2;
+      if ((cond2 == GE && ival2 == 1 + ival1)
+	  || (cond2 == GEU && uval2 == 1 + uval1))
+	return cond2;
+
+      // Similar, but the input sequence is like
+      //    if (reg == val)      goto label1;
+      //    if (reg >  val - 1)  goto label2;
+      if ((cond2 == GT && ival2 == ival1 - 1)
+	  || (cond2 == GTU && uval2 == uval1 - 1))
+	return avr_normalize_condition (cond2);
+
+      /////////////////////////////////////////////////////////
+      // A sequence like
+      //    if (reg == val)      goto label1;
+      //    if (reg < 1 + val)   goto label2;
+      // can be re-written as
+      //    REG_CC = compare (reg, val)
+      //    if (REG_CC == 0)  goto label1;
+      //    if (REG_CC < 0)   goto label2;
+      if ((cond2 == LT && ival2 == 1 + ival1)
+	  || (cond2 == LTU && uval2 == 1 + uval1))
+	return cond2;
+
+      // Similar, but with an input sequence like
+      //    if (reg == val)   goto label1;
+      //    if (reg <= val)   goto label2;
+      if (ival1 == ival2
+	  && (cond2 == LE || cond2 == LEU))
+	return avr_normalize_condition (cond2);
+
+      // Similar, but with an input sequence like
+      //    if (reg == val)  goto label1;
+      //    if (reg < val)   goto label2;
+      if (ival1 == ival2
+	  && (cond2 == LT || cond2 == LTU))
+	return cond2;
+
+      // Similar, but with an input sequence like
+      //    if (reg == val)      goto label1;
+      //    if (reg <= val - 1)  goto label2;
+      if ((cond2 == LE && ival2 == ival1 - 1)
+	  || (cond2 == LEU && uval2 == uval1 - 1))
+	return avr_normalize_condition (cond2);
+
+    } // cond1 == EQ
+
+  return UNKNOWN;
+}
+
+
+/* If-else decision trees generated for switch / case may produce sequences
+   like
+
+      SREG = compare (reg, val);
+	  if (SREG == 0)  goto label1;
+      SREG = compare (reg, 1 + val);
+	  if (SREG >= 0)  goto label2;
+
+   which can be optimized to
+
+      SREG = compare (reg, val);
+	  if (SREG == 0)  goto label1;
+	  if (SREG >= 0)  goto label2;
+
+   The optimal place for such a pass would be directly after expand, but
+   it's not possible for a jump insn to target more than one code label.
+   Hence, run a mini pass right before split2 which introduces REG_CC.  */
+
+void
+avr_pass_ifelse::avr_rest_of_handle_ifelse (function*)
+{
+  rtx_insn *next_insn;
+
+  for (rtx_insn *insn = get_insns(); insn; insn = next_insn)
+    {
+      next_insn = next_nonnote_nondebug_insn (insn);
+
+      if (! next_insn)
+	break;
+
+      // Search for two cbranch insns.  The first one is a cbranch.
+      // Filter for "cbranch<mode>4_insn" with mode in QI, HI, PSI, SI.
+
+      if (! JUMP_P (insn))
+	continue;
+
+      int icode1 = recog_memoized (insn);
+
+      if (icode1 != CODE_FOR_cbranchqi4_insn
+	  && icode1 != CODE_FOR_cbranchhi4_insn
+	  && icode1 != CODE_FOR_cbranchpsi4_insn
+	  && icode1 != CODE_FOR_cbranchsi4_insn)
+	continue;
+
+      rtx_jump_insn *insn1 = as_a<rtx_jump_insn *> (insn);
+      rtx_jump_insn *insn2 = nullptr;
+      bool follow_label1 = false;
+
+      // Extract the operands of the first insn:
+      // $0 = comparison operator ($1, $2)
+      // $1 = reg
+      // $2 = reg or const_int
+      // $3 = code_label
+      // $4 = optional SCRATCH for HI, PSI, SI cases.
+
+      const auto &op = recog_data.operand;
+
+      extract_insn (insn1);
+      rtx xop1[5] = { op[0], op[1], op[2], op[3], op[4] };
+      int n_operands = recog_data.n_operands;
+
+      // For now, we can optimize cbranches that follow an EQ cbranch,
+      // and cbranches that follow the label of a NE cbranch.
+
+      if (GET_CODE (xop1[0]) == EQ
+	  && JUMP_P (next_insn)
+	  && recog_memoized (next_insn) == icode1)
+	{
+	  // The 2nd cbranch insn follows insn1, i.e. is located in the
+	  // fallthrough path of insn1.
+
+	  insn2 = as_a<rtx_jump_insn *> (next_insn);
+	}
+      else if (GET_CODE (xop1[0]) == NE)
+	{
+	  // insn1 might branch to a label followed by a cbranch.
+
+	  rtx target1 = JUMP_LABEL (insn1);
+	  rtx_insn *code_label1 = JUMP_LABEL_AS_INSN (insn1);
+	  rtx_insn *next = next_nonnote_nondebug_insn (code_label1);
+	  rtx_insn *barrier = prev_nonnote_nondebug_insn (code_label1);
+
+	  if (// Target label of insn1 is used exactly once and
+	      // is not a fallthru, i.e. is preceded by a barrier.
+	      LABEL_NUSES (target1) == 1
+	      && barrier
+	      && BARRIER_P (barrier)
+	      // Following the target label is a cbranch of the same kind.
+	      && next
+	      && JUMP_P (next)
+	      && recog_memoized (next) == icode1)
+	    {
+	      follow_label1 = true;
+	      insn2 = as_a<rtx_jump_insn *> (next);
+	    }
+	}
+
+      if (! insn2)
+	continue;
+
+      // Also extract operands of insn2, and filter for REG + CONST_INT
+      // comparsons against the same register.
+
+      extract_insn (insn2);
+      rtx xop2[5] = { op[0], op[1], op[2], op[3], op[4] };
+
+      if (! rtx_equal_p (xop1[1], xop2[1])
+	  || ! CONST_INT_P (xop1[2])
+	  || ! CONST_INT_P (xop2[2]))
+	continue;
+
+      machine_mode mode = GET_MODE (xop1[1]);
+      enum rtx_code code1 = GET_CODE (xop1[0]);
+      enum rtx_code code2 = GET_CODE (xop2[0]);
+
+      code2 = avr_redundant_compare (code1, xop1[2], code2, xop2[2],
+				     mode, follow_label1);
+      if (code2 == UNKNOWN)
+	continue;
+
+      //////////////////////////////////////////////////////
+      // Found a replacement.
+
+      if (dump_file)
+	{
+	  fprintf (dump_file, "\n;; Found chain of jump_insn %d and"
+		   " jump_insn %d, follow_label1=%d:\n",
+		   INSN_UID (insn1), INSN_UID (insn2), follow_label1);
+	  print_rtl_single (dump_file, PATTERN (insn1));
+	  print_rtl_single (dump_file, PATTERN (insn2));
+	}
+
+      if (! follow_label1)
+	next_insn = next_nonnote_nondebug_insn (insn2);
+
+      // Pop the new branch conditions and the new comparison.
+      // Prematurely split into compare + branch so that we can drop
+      // the 2nd comparison.  The following pass, split2, splits all
+      // insns for REG_CC, and it should still work as usual even when
+      // there are already some REG_CC insns around.
+
+      rtx xcond1 = gen_rtx_fmt_ee (code1, VOIDmode, cc_reg_rtx, const0_rtx);
+      rtx xcond2 = gen_rtx_fmt_ee (code2, VOIDmode, cc_reg_rtx, const0_rtx);
+      rtx xpat1 = gen_branch (xop1[3], xcond1);
+      rtx xpat2 = gen_branch (xop2[3], xcond2);
+      rtx xcompare = NULL_RTX;
+
+      if (mode == QImode)
+	{
+	  gcc_assert (n_operands == 4);
+	  xcompare = gen_cmpqi3 (xop1[1], xop1[2]);
+	}
+      else
+	{
+	  gcc_assert (n_operands == 5);
+	  rtx (*gen_cmp)(rtx,rtx,rtx)
+	    = mode == HImode  ? gen_gen_comparehi
+	    : mode == PSImode ? gen_gen_comparepsi
+	    : gen_gen_comparesi; // SImode
+	  xcompare = gen_cmp (xop1[1], xop1[2], xop1[4]);
+	}
+
+      // Emit that stuff.
+
+      rtx_insn *cmp = emit_insn_before (xcompare, insn1);
+      rtx_jump_insn *branch1 = emit_jump_insn_before (xpat1, insn1);
+      rtx_jump_insn *branch2 = emit_jump_insn_before (xpat2, insn2);
+
+      JUMP_LABEL (branch1) = xop1[3];
+      JUMP_LABEL (branch2) = xop2[3];
+      // delete_insn() decrements LABEL_NUSES when deleting a JUMP_INSN, but
+      // when we pop a new JUMP_INSN, do it by hand.
+      ++LABEL_NUSES (xop1[3]);
+      ++LABEL_NUSES (xop2[3]);
+
+      delete_insn (insn1);
+      delete_insn (insn2);
+
+      // As a side effect, also recog the new insns.
+      gcc_assert (valid_insn_p (cmp));
+      gcc_assert (valid_insn_p (branch1));
+      gcc_assert (valid_insn_p (branch2));
+    } // loop insns
+}
+
+
 /* Set `avr_arch' as specified by `-mmcu='.
    Return true on success.  */
 
@@ -1019,6 +1358,19 @@ avr_no_gccisr_function_p (tree func)
   return avr_lookup_function_attribute1 (func, "no_gccisr");
 }
 
+
+/* Implement `TARGET_CAN_INLINE_P'.  */
+/* Some options like -mgas_isr_prologues depend on optimization level,
+   and the inliner might think that due to different options, inlining
+   is not permitted; see PR104327.  */
+
+static bool
+avr_can_inline_p (tree /* caller */, tree /* callee */)
+{
+  // No restrictions whatsoever.
+  return true;
+}
+
 /* Implement `TARGET_SET_CURRENT_FUNCTION'.  */
 /* Sanity cheching for above function attributes.  */
 
@@ -3173,28 +3525,6 @@ avr_asm_final_postscan_insn (FILE *stream, rtx_insn *insn, rtx*, int)
 }
 
 
-/* Return 0 if undefined, 1 if always true or always false.  */
-
-int
-avr_simplify_comparison_p (machine_mode mode, RTX_CODE op, rtx x)
-{
-  unsigned int max = (mode == QImode ? 0xff :
-                      mode == HImode ? 0xffff :
-                      mode == PSImode ? 0xffffff :
-                      mode == SImode ? 0xffffffff : 0);
-  if (max && op && CONST_INT_P (x))
-    {
-      if (unsigned_condition (op) != op)
-        max >>= 1;
-
-      if (max != (INTVAL (x) & max)
-          && INTVAL (x) != 0xff)
-        return 1;
-    }
-  return 0;
-}
-
-
 /* Worker function for `FUNCTION_ARG_REGNO_P'.  */
 /* Returns nonzero if REGNO is the number of a hard
    register in which function arguments are sometimes passed.  */
@@ -5677,29 +6007,36 @@ avr_frame_pointer_required_p (void)
           || get_frame_size () > 0);
 }
 
-/* Returns the condition of compare insn INSN, or UNKNOWN.  */
+
+/* Returns the condition of the branch following INSN, where INSN is some
+   comparison.  If the next insn is not a branch or the condition code set
+   by INSN might be used by more insns than the next one, return UNKNOWN.
+   For now, just look at the next insn, which misses some opportunities like
+   following jumps.  */
 
 static RTX_CODE
 compare_condition (rtx_insn *insn)
 {
-  rtx_insn *next = next_real_insn (insn);
+  rtx set;
+  rtx_insn *next = next_real_nondebug_insn (insn);
 
-  if (next && JUMP_P (next))
+  if (next
+      && JUMP_P (next)
+      // If SREG does not die in the next insn, it is used in more than one
+      // branch.  This can happen due to pass .avr-ifelse optimizations.
+      && dead_or_set_regno_p (next, REG_CC)
+      // Branches are (set (pc) (if_then_else (COND (...)))).
+      && (set = single_set (next))
+      && GET_CODE (SET_SRC (set)) == IF_THEN_ELSE)
     {
-      rtx pat = PATTERN (next);
-      if (GET_CODE (pat) == PARALLEL)
-        pat = XVECEXP (pat, 0, 0);
-      rtx src = SET_SRC (pat);
-
-      if (IF_THEN_ELSE == GET_CODE (src))
-        return GET_CODE (XEXP (src, 0));
+      return GET_CODE (XEXP (SET_SRC (set), 0));
     }
 
   return UNKNOWN;
 }
 
 
-/* Returns true iff INSN is a tst insn that only tests the sign.  */
+/* Returns true if INSN is a tst insn that only tests the sign.  */
 
 static bool
 compare_sign_p (rtx_insn *insn)
@@ -5709,23 +6046,95 @@ compare_sign_p (rtx_insn *insn)
 }
 
 
-/* Returns true iff the next insn is a JUMP_INSN with a condition
-   that needs to be swapped (GT, GTU, LE, LEU).  */
+/* Returns true if INSN is a compare insn with the EQ or NE condition.  */
 
 static bool
-compare_diff_p (rtx_insn *insn)
+compare_eq_p (rtx_insn *insn)
 {
   RTX_CODE cond = compare_condition (insn);
-  return (cond == GT || cond == GTU || cond == LE || cond == LEU) ? cond : 0;
+  return (cond == EQ || cond == NE);
 }
 
-/* Returns true iff INSN is a compare insn with the EQ or NE condition.  */
 
-static bool
-compare_eq_p (rtx_insn *insn)
+/* Implement `TARGET_CANONICALIZE_COMPARISON'.  */
+/* Basically tries to convert "difficult" comparisons like GT[U]
+   and LE[U] to simple ones.  Some asymmetric comparisons can be
+   transformed to EQ or NE against zero.  */
+
+static void
+avr_canonicalize_comparison (int *icode, rtx *op0, rtx *op1, bool op0_fixed)
 {
-  RTX_CODE cond = compare_condition (insn);
-  return (cond == EQ || cond == NE);
+  enum rtx_code code = (enum rtx_code) *icode;
+  machine_mode mode = GET_MODE (*op0);
+
+  bool signed_p = code == GT || code == LE;
+  bool unsigned_p = code == GTU || code == LEU;
+  bool difficult_p = signed_p || unsigned_p;
+
+  if (// Only do integers and fixed-points.
+      (! SCALAR_INT_MODE_P (mode)
+       && ! ALL_SCALAR_FIXED_POINT_MODE_P (mode))
+      // Only do comparisons against a register.
+      || ! register_operand (*op0, mode))
+    return;
+
+  // Canonicalize "difficult" reg-reg comparisons.
+
+  if (! op0_fixed
+      && difficult_p
+      && register_operand (*op1, mode))
+    {
+      std::swap (*op0, *op1);
+      *icode = (int) swap_condition (code);
+      return;
+    }
+
+  // Canonicalize comparisons against compile-time constants.
+
+  if (CONST_INT_P (*op1)
+      || CONST_FIXED_P (*op1))
+    {
+      // INT_MODE of the same size.
+      scalar_int_mode imode = int_mode_for_mode (mode).require ();
+
+      unsigned HOST_WIDE_INT mask = GET_MODE_MASK (imode);
+      unsigned HOST_WIDE_INT maxval = signed_p ? mask >> 1 : mask;
+
+      // Convert value *op1 to imode.
+      rtx xval = simplify_gen_subreg (imode, *op1, mode, 0);
+
+      // Canonicalize difficult comparisons against const.
+      if (difficult_p
+	  && (UINTVAL (xval) & mask) != maxval)
+	{
+	  // Convert *op0 > *op1  to *op0 >= 1 + *op1.
+	  // Convert *op0 <= *op1 to *op0 <  1 + *op1.
+	  xval = simplify_binary_operation (PLUS, imode, xval, const1_rtx);
+
+	  // Convert value back to its original mode.
+	  *op1 = simplify_gen_subreg (mode, xval, imode, 0);
+
+	  // Map  >  to  >=  and  <=  to  <.
+	  *icode = (int) avr_normalize_condition (code);
+
+	  return;
+	}
+
+      // Some asymmetric comparisons can be turned into EQ or NE.
+      if (code == LTU && xval == const1_rtx)
+	{
+	  *icode = (int) EQ;
+	  *op1 = CONST0_RTX (mode);
+	  return;
+	}
+
+      if (code == GEU && xval == const1_rtx)
+	{
+	  *icode = (int) NE;
+	  *op1 = CONST0_RTX (mode);
+	  return;
+	}
+    }
 }
 
 
@@ -6018,6 +6427,68 @@ avr_out_tstsi (rtx_insn *insn, rtx *op, int *plen)
 }
 
 
+/* Output a comparison of a zero- or sign-extended register against a
+   plain register.  CODE is SIGN_EXTEND or ZERO_EXTEND.  Return "".
+
+   PLEN != 0: Set *PLEN to the code length in words. Don't output anything.
+   PLEN == 0: Print instructions.  */
+
+const char*
+avr_out_cmp_ext (rtx xop[], enum rtx_code code, int *plen)
+{
+  // The smaller reg is the one that's to be extended.  Get its index as z.
+  int z = GET_MODE_SIZE (GET_MODE (xop[1])) < GET_MODE_SIZE (GET_MODE (xop[0]));
+  rtx zreg = xop[z];
+  rtx reg = xop[1 - z];
+  machine_mode mode = GET_MODE (reg);
+  machine_mode zmode = GET_MODE (zreg);
+  rtx zex;
+
+  if (plen)
+    *plen = 0;
+
+  // zex holds the extended bytes above zreg.  This is 0 for ZERO_EXTEND,
+  // and 0 or -1 for SIGN_EXTEND.
+
+  if (code == SIGN_EXTEND)
+    {
+      // Sign-extend the high-byte of zreg to tmp_reg.
+      int zmsb = GET_MODE_SIZE (zmode) - 1;
+      rtx xzmsb = simplify_gen_subreg (QImode, zreg, zmode, zmsb);
+
+      avr_asm_len ("mov __tmp_reg__,%0" CR_TAB
+		   "rol __tmp_reg__"    CR_TAB
+		   "sbc __tmp_reg__,__tmp_reg__", &xzmsb, plen, 3);
+      zex = tmp_reg_rtx;
+    }
+  else if (code == ZERO_EXTEND)
+    {
+      zex = zero_reg_rtx;
+    }
+  else
+    gcc_unreachable();
+
+  // Now output n_bytes bytes of the very comparison.
+
+  int n_bytes = GET_MODE_SIZE (mode);
+
+  avr_asm_len ("cp %0,%1", xop, plen, 1);
+
+  for (int b = 1; b < n_bytes; ++b)
+    {
+      rtx regs[2];
+      regs[1 - z] = simplify_gen_subreg (QImode, reg, mode, b);
+      regs[z] = (b < GET_MODE_SIZE (zmode)
+		 ? simplify_gen_subreg (QImode, zreg, zmode, b)
+		 : zex);
+
+      avr_asm_len ("cpc %0,%1", regs, plen, 1);
+    }
+
+  return "";
+}
+
+
 /* Generate asm equivalent for various shifts.  This only handles cases
    that are not already carefully hand-optimized in ?sh??i3_out.
 
@@ -8160,6 +8631,122 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc, bool out_label)
 }
 
 
+/* Output an instruction sequence for addition of REG in XOP[0] and CONST_INT
+   in XOP[1] in such a way that SREG.Z and SREG.N are set according to the
+   result.  XOP[2] might be a d-regs clobber register.  If XOP[2] is SCRATCH,
+   then the addition can be performed without a clobber reg.  Return "".
+
+   If PLEN == NULL, then output the instructions.
+   If PLEN != NULL, then set *PLEN to the length of the sequence in words. */
+
+const char*
+avr_out_plus_set_ZN (rtx *xop, int *plen)
+{
+  if (plen)
+    *plen = 0;
+
+  // Register to compare and value to compare against.
+  rtx xreg = xop[0];
+  rtx xval = xop[1];
+
+  machine_mode mode = GET_MODE (xreg);
+
+  // Number of bytes to operate on.
+  int n_bytes = GET_MODE_SIZE (mode);
+
+  if (n_bytes == 1)
+    {
+      if (INTVAL (xval) == 1)
+	return avr_asm_len ("inc %0", xop, plen, 1);
+
+      if (INTVAL (xval) == -1)
+	return avr_asm_len ("dec %0", xop, plen, 1);
+    }
+
+  if (n_bytes == 2
+      && test_hard_reg_class (ADDW_REGS, xreg)
+      && IN_RANGE (INTVAL (xval), 1, 63))
+    {
+      // Add 16-bit value in [1..63] to a w register.
+      return avr_asm_len ("adiw %0, %1", xop, plen, 1);
+    }
+
+  // Addition won't work; subtract the negative of XVAL instead.
+  xval = simplify_unary_operation (NEG, mode, xval, mode);
+
+  // Value (0..0xff) held in clobber register xop[2] or -1 if unknown.
+  int clobber_val = -1;
+
+  // [0] = Current sub-register.
+  // [1] = Current partial xval.
+  // [2] = 8-bit clobber d-register or SCRATCH.
+  rtx op[3];
+  op[2] = xop[2];
+
+  // Work byte-wise from LSB to MSB.  The lower two bytes might be
+  // SBIW'ed in one go.
+  for (int i = 0; i < n_bytes; ++i)
+    {
+      op[0] = simplify_gen_subreg (QImode, xreg, mode, i);
+
+      if (i == 0
+	  && n_bytes >= 2
+	  && test_hard_reg_class (ADDW_REGS, op[0]))
+	{
+	  op[1] = simplify_gen_subreg (HImode, xval, mode, 0);
+	  if (IN_RANGE (INTVAL (op[1]), 0, 63))
+	    {
+	      // SBIW can handle the lower 16 bits.
+	      avr_asm_len ("sbiw %0, %1", op, plen, 1);
+
+	      // Next byte has already been handled: Skip it.
+	      ++i;
+	      continue;
+	    }
+	}
+
+      op[1] = simplify_gen_subreg (QImode, xval, mode, i);
+
+      if (test_hard_reg_class (LD_REGS, op[0]))
+	{
+	  // d-regs can subtract immediates.
+	  avr_asm_len (i == 0
+		       ? "subi %0, %1"
+		       : "sbci %0, %1", op, plen, 1);
+	}
+      else
+	{
+	  int val8 = 0xff & INTVAL (op[1]);
+	  if (val8 == 0)
+	    {
+	      // Any register can subtract 0.
+	      avr_asm_len (i == 0
+			   ? "sub %0, __zero_reg__"
+			   : "sbc %0, __zero_reg__", op, plen, 1);
+	    }
+	  else
+	    {
+	      // Use d-register to hold partial xval.
+
+	      if (val8 != clobber_val)
+		{
+		  // Load partial xval to QI clobber reg and memoize for later.
+		  gcc_assert (REG_P (op[2]));
+		  avr_asm_len ("ldi %2, %1", op, plen, 1);
+		  clobber_val = val8;
+		}
+
+	      avr_asm_len (i == 0
+			   ? "sub %0, %2"
+			   : "sbc %0, %2", op, plen, 1);
+	    }
+	}
+    } // Loop bytes.
+
+  return "";
+}
+
+
 /* Output bit operation (IOR, AND, XOR) with register XOP[0] and compile
    time constant XOP[2]:
 
@@ -9291,6 +9878,8 @@ avr_adjust_insn_length (rtx_insn *insn, int len)
     case ADJUST_LEN_TSTSI: avr_out_tstsi (insn, op, &len); break;
     case ADJUST_LEN_COMPARE: avr_out_compare (insn, op, &len); break;
     case ADJUST_LEN_COMPARE64: avr_out_compare64 (insn, op, &len); break;
+    case ADJUST_LEN_CMP_UEXT: avr_out_cmp_ext (op, ZERO_EXTEND, &len); break;
+    case ADJUST_LEN_CMP_SEXT: avr_out_cmp_ext (op, SIGN_EXTEND, &len); break;
 
     case ADJUST_LEN_LSHRQI: lshrqi3_out (insn, op, &len); break;
     case ADJUST_LEN_LSHRHI: lshrhi3_out (insn, op, &len); break;
@@ -9311,6 +9900,7 @@ avr_adjust_insn_length (rtx_insn *insn, int len)
     case ADJUST_LEN_CALL: len = AVR_HAVE_JMP_CALL ? 2 : 1; break;
 
     case ADJUST_LEN_INSERT_BITS: avr_out_insert_bits (op, &len); break;
+    case ADJUST_LEN_ADD_SET_ZN: avr_out_plus_set_ZN (op, &len); break;
 
     case ADJUST_LEN_INSV_NOTBIT:
       avr_out_insert_notbit (insn, op, NULL_RTX, &len);
@@ -10607,6 +11197,58 @@ avr_mul_highpart_cost (rtx x, int)
 }
 
 
+/* Return the expected cost of a conditional branch like
+   (set (pc)
+	(if_then_else (X)
+		      (label_ref *)
+		      (pc)))
+   where X is some comparison operator.  */
+
+static int
+avr_cbranch_cost (rtx x)
+{
+  bool difficult_p = difficult_comparison_operator (x, VOIDmode);
+
+  if (reload_completed)
+    {
+      // After reload, we basically just have plain branches.
+      return COSTS_N_INSNS (1 + difficult_p);
+    }
+
+  rtx xreg = XEXP (x, 0);
+  rtx xval = XEXP (x, 1);
+  machine_mode mode = GET_MODE (xreg);
+  if (mode == VOIDmode)
+    mode = GET_MODE (xval);
+  int size = GET_MODE_SIZE (mode);
+
+  if (GET_CODE (xreg) == ZERO_EXTEND
+      || GET_CODE (xval) == ZERO_EXTEND)
+    {
+      // *cbranch<HISI:mode>.<code><QIPSI:mode>.0/1, code = zero_extend.
+      return COSTS_N_INSNS (size + 1);
+    }
+
+  if (GET_CODE (xreg) == SIGN_EXTEND
+      || GET_CODE (xval) == SIGN_EXTEND)
+    {
+      // *cbranch<HISI:mode>.<code><QIPSI:mode>.0/1, code = sign_extend.
+      // Make it a bit cheaper than it actually is (less reg pressure).
+      return COSTS_N_INSNS (size + 1 + 1);
+    }
+
+  bool reg_p = register_operand (xreg, mode);
+  bool reg_or_0_p = reg_or_0_operand (xval, mode);
+
+  return COSTS_N_INSNS (size
+			// For the branch
+			+ 1 + difficult_p
+			// Combine might propagate constants other than zero
+			// into the 2nd operand.  Make that more expensive.
+			+ 1 * (!reg_p || !reg_or_0_p));
+}
+
+
 /* Mutually recursive subroutine of avr_rtx_cost for calculating the
    cost of an RTX operand given its context.  X is the rtx of the
    operand, MODE is its mode, and OUTER is the rtx_code of this
@@ -10844,6 +11486,15 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
             *total += COSTS_N_INSNS (1);
           return true;
         }
+      if (IOR == code
+          && AND == GET_CODE (XEXP (x, 0))
+          && AND == GET_CODE (XEXP (x, 1))
+          && single_zero_operand (XEXP (XEXP (x, 0), 1), mode))
+        {
+          // Open-coded bit transfer.
+          *total = COSTS_N_INSNS (2);
+          return true;
+        }
       *total = COSTS_N_INSNS (GET_MODE_SIZE (mode));
       *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, 0, speed);
       if (!CONST_INT_P (XEXP (x, 1)))
@@ -11490,6 +12141,15 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
         }
       break;
 
+    case IF_THEN_ELSE:
+      if (outer_code == SET
+	  && XEXP (x, 2) == pc_rtx
+	  && ordered_comparison_operator (XEXP (x, 0), VOIDmode))
+	{
+	  *total = avr_cbranch_cost (XEXP (x, 0));
+	  return true;
+	}
+
     default:
       break;
     }
@@ -11515,6 +12175,52 @@ avr_rtx_costs (rtx x, machine_mode mode, int outer_code,
 }
 
 
+/* Implement `TARGET_INSN_COST'.  */
+/* For some insns, it is not enough to look at the cost of the SET_SRC.
+   In that case, have a look at the entire insn, e.g. during insn combine.  */
+
+static int
+avr_insn_cost (rtx_insn *insn, bool speed)
+{
+  const int unknown_cost = -1;
+  int cost = unknown_cost;
+
+  rtx set = single_set (insn);
+
+  if (set
+      && ZERO_EXTRACT == GET_CODE (SET_DEST (set)))
+    {
+      // Try find anything that would flip the extracted bit.
+      bool not_bit_p = false;
+
+      subrtx_iterator::array_type array;
+      FOR_EACH_SUBRTX (iter, array, SET_SRC (set), NONCONST)
+	{
+	  enum rtx_code code = GET_CODE (*iter);
+	  not_bit_p |= code == NOT || code == XOR || code == GE;
+	}
+
+      // Don't go too deep into the analysis.  In almost all cases,
+      // using BLD/BST is the best we can do for single-bit moves,
+      // even considering CSE.
+      cost = COSTS_N_INSNS (2 + not_bit_p);
+    }
+
+  if (cost != unknown_cost)
+    {
+      if (avr_log.rtx_costs)
+	avr_edump ("\n%? (%s) insn_cost=%d\n%r\n",
+		   speed ? "speed" : "size", cost, insn);
+      return cost;
+    }
+
+  // Resort to what rtlanal.cc::insn_cost() implements as a default
+  // when targetm.insn_cost() is not implemented.
+
+  return pattern_cost (PATTERN (insn), speed);
+}
+
+
 /* Implement `TARGET_ADDRESS_COST'.  */
 
 static int
@@ -11602,281 +12308,6 @@ avr_normalize_condition (RTX_CODE condition)
     }
 }
 
-/* Helper function for `avr_reorg'.  */
-
-static rtx
-avr_compare_pattern (rtx_insn *insn)
-{
-  rtx pattern = single_set (insn);
-
-  if (pattern
-      && NONJUMP_INSN_P (insn)
-      && REG_P (SET_DEST (pattern))
-      && REGNO (SET_DEST (pattern)) == REG_CC
-      && GET_CODE (SET_SRC (pattern)) == COMPARE)
-    {
-      machine_mode mode0 = GET_MODE (XEXP (SET_SRC (pattern), 0));
-      machine_mode mode1 = GET_MODE (XEXP (SET_SRC (pattern), 1));
-
-      /* The 64-bit comparisons have fixed operands ACC_A and ACC_B.
-         They must not be swapped, thus skip them.  */
-
-      if ((mode0 == VOIDmode || GET_MODE_SIZE (mode0) <= 4)
-          && (mode1 == VOIDmode || GET_MODE_SIZE (mode1) <= 4))
-        return pattern;
-    }
-
-  return NULL_RTX;
-}
-
-/* Helper function for `avr_reorg'.  */
-
-/* Expansion of switch/case decision trees leads to code like
-
-       REG_CC = compare (Reg, Num)
-       if (REG_CC == 0)
-         goto L1
-
-       REG_CC = compare (Reg, Num)
-       if (REG_CC > 0)
-         goto L2
-
-   The second comparison is superfluous and can be deleted.
-   The second jump condition can be transformed from a
-   "difficult" one to a "simple" one because "REG_CC > 0" and
-   "REG_CC >= 0" will have the same effect here.
-
-   This function relies on the way switch/case is being expaned
-   as binary decision tree.  For example code see PR 49903.
-
-   Return TRUE if optimization performed.
-   Return FALSE if nothing changed.
-
-   INSN1 is a comparison, i.e. avr_compare_pattern != 0.
-
-   We don't want to do this in text peephole because it is
-   tedious to work out jump offsets there and the second comparison
-   might have been transormed by `avr_reorg'.
-
-   RTL peephole won't do because peephole2 does not scan across
-   basic blocks.  */
-
-static bool
-avr_reorg_remove_redundant_compare (rtx_insn *insn1)
-{
-  rtx comp1, ifelse1, xcond1;
-  rtx_insn *branch1;
-  rtx comp2, ifelse2, xcond2;
-  rtx_insn *branch2, *insn2;
-  enum rtx_code code;
-  rtx_insn *jump;
-  rtx target, cond;
-
-  /* Look out for:  compare1 - branch1 - compare2 - branch2  */
-
-  branch1 = next_nonnote_nondebug_insn (insn1);
-  if (!branch1 || !JUMP_P (branch1))
-    return false;
-
-  insn2 = next_nonnote_nondebug_insn (branch1);
-  if (!insn2 || !avr_compare_pattern (insn2))
-    return false;
-
-  branch2 = next_nonnote_nondebug_insn (insn2);
-  if (!branch2 || !JUMP_P (branch2))
-    return false;
-
-  comp1 = avr_compare_pattern (insn1);
-  comp2 = avr_compare_pattern (insn2);
-  xcond1 = single_set (branch1);
-  xcond2 = single_set (branch2);
-
-  if (!comp1 || !comp2
-      || !rtx_equal_p (comp1, comp2)
-      || !xcond1 || SET_DEST (xcond1) != pc_rtx
-      || !xcond2 || SET_DEST (xcond2) != pc_rtx
-      || IF_THEN_ELSE != GET_CODE (SET_SRC (xcond1))
-      || IF_THEN_ELSE != GET_CODE (SET_SRC (xcond2)))
-    {
-      return false;
-    }
-
-  comp1 = SET_SRC (comp1);
-  ifelse1 = SET_SRC (xcond1);
-  ifelse2 = SET_SRC (xcond2);
-
-  /* comp<n> is COMPARE now and ifelse<n> is IF_THEN_ELSE.  */
-
-  if (EQ != GET_CODE (XEXP (ifelse1, 0))
-      || !REG_P (XEXP (comp1, 0))
-      || !CONST_INT_P (XEXP (comp1, 1))
-      || XEXP (ifelse1, 2) != pc_rtx
-      || XEXP (ifelse2, 2) != pc_rtx
-      || LABEL_REF != GET_CODE (XEXP (ifelse1, 1))
-      || LABEL_REF != GET_CODE (XEXP (ifelse2, 1))
-      || !COMPARISON_P (XEXP (ifelse2, 0))
-      || REG_CC != REGNO (XEXP (XEXP (ifelse1, 0), 0))
-      || REG_CC != REGNO (XEXP (XEXP (ifelse2, 0), 0))
-      || const0_rtx != XEXP (XEXP (ifelse1, 0), 1)
-      || const0_rtx != XEXP (XEXP (ifelse2, 0), 1))
-    {
-      return false;
-    }
-
-  /* We filtered the insn sequence to look like
-
-        (set (reg:CC cc)
-             (compare (reg:M N)
-                      (const_int VAL)))
-        (set (pc)
-             (if_then_else (eq (reg:CC cc)
-                               (const_int 0))
-                           (label_ref L1)
-                           (pc)))
-
-        (set (reg:CC cc)
-             (compare (reg:M N)
-                      (const_int VAL)))
-        (set (pc)
-             (if_then_else (CODE (reg:CC cc)
-                                 (const_int 0))
-                           (label_ref L2)
-                           (pc)))
-  */
-
-  code = GET_CODE (XEXP (ifelse2, 0));
-
-  /* Map GT/GTU to GE/GEU which is easier for AVR.
-     The first two instructions compare/branch on EQ
-     so we may replace the difficult
-
-        if (x == VAL)   goto L1;
-        if (x > VAL)    goto L2;
-
-     with easy
-
-         if (x == VAL)   goto L1;
-         if (x >= VAL)   goto L2;
-
-     Similarly, replace LE/LEU by LT/LTU.  */
-
-  switch (code)
-    {
-    case EQ:
-    case LT:  case LTU:
-    case GE:  case GEU:
-      break;
-
-    case LE:  case LEU:
-    case GT:  case GTU:
-      code = avr_normalize_condition (code);
-      break;
-
-    default:
-      return false;
-    }
-
-  /* Wrap the branches into UNSPECs so they won't be changed or
-     optimized in the remainder.  */
-
-  target = XEXP (XEXP (ifelse1, 1), 0);
-  cond = XEXP (ifelse1, 0);
-  jump = emit_jump_insn_after (gen_branch_unspec (target, cond), insn1);
-
-  JUMP_LABEL (jump) = JUMP_LABEL (branch1);
-
-  target = XEXP (XEXP (ifelse2, 1), 0);
-  cond = gen_rtx_fmt_ee (code, VOIDmode, cc_reg_rtx, const0_rtx);
-  jump = emit_jump_insn_after (gen_branch_unspec (target, cond), insn2);
-
-  JUMP_LABEL (jump) = JUMP_LABEL (branch2);
-
-  /* The comparisons in insn1 and insn2 are exactly the same;
-     insn2 is superfluous so delete it.  */
-
-  delete_insn (insn2);
-  delete_insn (branch1);
-  delete_insn (branch2);
-
-  return true;
-}
-
-
-/* Implement `TARGET_MACHINE_DEPENDENT_REORG'.  */
-/* Optimize conditional jumps.  */
-
-static void
-avr_reorg (void)
-{
-  rtx_insn *insn = get_insns();
-
-  for (insn = next_real_insn (insn); insn; insn = next_real_insn (insn))
-    {
-      rtx pattern = avr_compare_pattern (insn);
-
-      if (!pattern)
-        continue;
-
-      if (optimize
-          && avr_reorg_remove_redundant_compare (insn))
-        {
-          continue;
-        }
-
-      if (compare_diff_p (insn))
-	{
-          /* Now we work under compare insn with difficult branch.  */
-
-	  rtx_insn *next = next_real_insn (insn);
-          rtx pat = PATTERN (next);
-          if (GET_CODE (pat) == PARALLEL)
-            pat = XVECEXP (pat, 0, 0);
-
-          pattern = SET_SRC (pattern);
-
-          if (true_regnum (XEXP (pattern, 0)) >= 0
-              && true_regnum (XEXP (pattern, 1)) >= 0)
-            {
-              rtx x = XEXP (pattern, 0);
-              rtx src = SET_SRC (pat);
-              rtx t = XEXP (src, 0);
-              PUT_CODE (t, swap_condition (GET_CODE (t)));
-              XEXP (pattern, 0) = XEXP (pattern, 1);
-              XEXP (pattern, 1) = x;
-              INSN_CODE (next) = -1;
-            }
-          else if (true_regnum (XEXP (pattern, 0)) >= 0
-                   && XEXP (pattern, 1) == const0_rtx)
-            {
-              /* This is a tst insn, we can reverse it.  */
-              rtx src = SET_SRC (pat);
-              rtx t = XEXP (src, 0);
-
-              PUT_CODE (t, swap_condition (GET_CODE (t)));
-              XEXP (pattern, 1) = XEXP (pattern, 0);
-              XEXP (pattern, 0) = const0_rtx;
-              INSN_CODE (next) = -1;
-              INSN_CODE (insn) = -1;
-            }
-          else if (true_regnum (XEXP (pattern, 0)) >= 0
-                   && CONST_INT_P (XEXP (pattern, 1)))
-            {
-              rtx x = XEXP (pattern, 1);
-              rtx src = SET_SRC (pat);
-              rtx t = XEXP (src, 0);
-              machine_mode mode = GET_MODE (XEXP (pattern, 0));
-
-              if (avr_simplify_comparison_p (mode, GET_CODE (t), x))
-                {
-                  XEXP (pattern, 1) = gen_int_mode (INTVAL (x) + 1, mode);
-                  PUT_CODE (t, avr_normalize_condition (GET_CODE (t)));
-                  INSN_CODE (next) = -1;
-                  INSN_CODE (insn) = -1;
-                }
-            }
-        }
-    }
-}
 
 /* Returns register number for function return value.*/
 
@@ -14572,6 +15003,8 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code)
 #undef  TARGET_ASM_FINAL_POSTSCAN_INSN
 #define TARGET_ASM_FINAL_POSTSCAN_INSN avr_asm_final_postscan_insn
 
+#undef  TARGET_INSN_COST
+#define TARGET_INSN_COST avr_insn_cost
 #undef  TARGET_REGISTER_MOVE_COST
 #define TARGET_REGISTER_MOVE_COST avr_register_move_cost
 #undef  TARGET_MEMORY_MOVE_COST
@@ -14580,8 +15013,6 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code)
 #define TARGET_RTX_COSTS avr_rtx_costs
 #undef  TARGET_ADDRESS_COST
 #define TARGET_ADDRESS_COST avr_address_cost
-#undef  TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG avr_reorg
 #undef  TARGET_FUNCTION_ARG
 #define TARGET_FUNCTION_ARG avr_function_arg
 #undef  TARGET_FUNCTION_ARG_ADVANCE
@@ -14711,6 +15142,12 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code)
 #undef  TARGET_MD_ASM_ADJUST
 #define TARGET_MD_ASM_ADJUST avr_md_asm_adjust
 
+#undef  TARGET_CAN_INLINE_P
+#define TARGET_CAN_INLINE_P avr_can_inline_p
+
+#undef  TARGET_CANONICALIZE_COMPARISON
+#define TARGET_CANONICALIZE_COMPARISON avr_canonicalize_comparison
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 
--- a/src/gcc/config/avr/avr.md
+++ b/src/gcc/config/avr/avr.md
@@ -77,7 +77,6 @@ (define_c_enum "unspec"
    UNSPEC_FMULS
    UNSPEC_FMULSU
    UNSPEC_COPYSIGN
-   UNSPEC_IDENTITY
    UNSPEC_INSERT_BITS
    UNSPEC_ROUND
    ])
@@ -165,6 +164,7 @@ (define_attr "adjust_len"
    ashlsi, ashrsi, lshrsi,
    ashlpsi, ashrpsi, lshrpsi,
    insert_bits, insv_notbit, insv_notbit_0, insv_notbit_7,
+   add_set_ZN, cmp_uext, cmp_sext,
    no"
   (const_string "no"))
 
@@ -251,11 +251,23 @@ (define_mode_iterator QIHI  [QI HI])
 (define_mode_iterator QIHI2 [QI HI])
 (define_mode_iterator QISI  [QI HI PSI SI])
 (define_mode_iterator QIDI  [QI HI PSI SI DI])
+(define_mode_iterator QIPSI [QI HI PSI])
 (define_mode_iterator HISI  [HI PSI SI])
 
+;; Ordered integral and fixed-point modes of specific sizes.
 (define_mode_iterator ALL1 [QI QQ UQQ])
 (define_mode_iterator ALL2 [HI HQ UHQ HA UHA])
 (define_mode_iterator ALL4 [SI SQ USQ SA USA])
+(define_mode_iterator ALL234 [HI SI PSI
+                              HQ UHQ HA UHA
+                              SQ USQ SA USA])
+
+;; Ordered signed integral and signed fixed-point modes of specific sizes.
+(define_mode_iterator ALLs1 [QI QQ])
+(define_mode_iterator ALLs2 [HI HQ HA])
+(define_mode_iterator ALLs4 [SI SQ SA])
+(define_mode_iterator ALLs234 [HI SI PSI
+                               HQ HA SQ SA])
 
 ;; All supported move-modes
 (define_mode_iterator MOVMODE [QI QQ UQQ
@@ -273,15 +285,17 @@ (define_mode_iterator SPLIT34 [SI SF PSI
                                SQ USQ SA USA])
 
 ;; Define code iterators
-;; Define two incarnations so that we can build the cross product.
+;; Define two incarnations so that we can build the cartesian product.
 (define_code_iterator any_extend  [sign_extend zero_extend])
 (define_code_iterator any_extend2 [sign_extend zero_extend])
 (define_code_iterator any_extract [sign_extract zero_extract])
 (define_code_iterator any_shiftrt [lshiftrt ashiftrt])
 
+(define_code_iterator piaop [plus ior and])
 (define_code_iterator bitop [xor ior and])
 (define_code_iterator xior [xor ior])
 (define_code_iterator eqne [eq ne])
+(define_code_iterator gelt [ge lt])
 
 (define_code_iterator ss_addsub [ss_plus ss_minus])
 (define_code_iterator us_addsub [us_plus us_minus])
@@ -309,6 +323,10 @@ (define_code_attr abelian
   [(ss_minus "") (us_minus "")
    (ss_plus "%") (us_plus "%")])
 
+(define_code_attr gelt_eqne
+  [(ge "eq")
+   (lt "ne")])
+
 ;; Map RTX code to its standard insn name
 (define_code_attr code_stdname
   [(ashift   "ashl")
@@ -1529,9 +1547,8 @@ (define_insn_and_split "*usum_widenqihi3_split"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0)
-                   (plus:HI
-                     (zero_extend:HI (match_dup 1))
-                     (zero_extend:HI (match_dup 2))))
+                   (plus:HI (zero_extend:HI (match_dup 1))
+                            (zero_extend:HI (match_dup 2))))
               (clobber (reg:CC REG_CC))])])
 
 
@@ -2152,7 +2169,8 @@ (define_insn "*mulqi3_enh"
 (define_expand "mulqi3_call"
   [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
    (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
-   (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
+   (parallel [(set (reg:QI 24)
+                   (mult:QI (reg:QI 24) (reg:QI 22)))
               (clobber (reg:QI 22))])
    (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
   ""
@@ -2166,12 +2184,14 @@ (define_insn_and_split "*mulqi3_call_split"
   "!AVR_HAVE_MUL"
   "#"
   "&& reload_completed"
-  [(parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
+  [(parallel [(set (reg:QI 24)
+                   (mult:QI (reg:QI 24) (reg:QI 22)))
               (clobber (reg:QI 22))
               (clobber (reg:CC REG_CC))])])
 
 (define_insn "*mulqi3_call"
-  [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
+  [(set (reg:QI 24)
+        (mult:QI (reg:QI 24) (reg:QI 22)))
    (clobber (reg:QI 22))
    (clobber (reg:CC REG_CC))]
   "!AVR_HAVE_MUL && reload_completed"
@@ -2307,7 +2327,7 @@ (define_insn "*addpsi3.lt0"
   [(set (match_operand:PSI 0 "register_operand"                         "=r")
         (plus:PSI (lshiftrt:PSI (match_operand:PSI 1 "register_operand"  "r")
                                 (const_int 23))
-                 (match_operand:PSI 2 "register_operand"                 "0")))
+                  (match_operand:PSI 2 "register_operand"                "0")))
    (clobber (reg:CC REG_CC))]
   "reload_completed"
   "mov __tmp_reg__,%C1\;lsl __tmp_reg__
@@ -2433,7 +2453,7 @@ (define_insn "*sumulqihi3"
   [(set (match_operand:HI 0 "register_operand"                         "=r")
         (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
                  (zero_extend:HI (match_operand:QI 2 "register_operand" "a"))))
-    (clobber (reg:CC REG_CC))]
+   (clobber (reg:CC REG_CC))]
   "AVR_HAVE_MUL && reload_completed"
   "mulsu %1,%2
 	movw %0,r0
@@ -3088,7 +3108,7 @@ (define_insn_and_split "muluqihi3"
   [(parallel [(set (match_dup 0)
                    (mult:HI (zero_extend:HI (match_dup 1))
                             (match_dup 2)))
-               (clobber (reg:CC REG_CC))])])
+              (clobber (reg:CC REG_CC))])])
 
 (define_insn "*muluqihi3"
   [(set (match_operand:HI 0 "register_operand"                        "=&r")
@@ -3706,17 +3726,17 @@ (define_insn "*mulohisi3_call"
 ;;    CSE has problems to operate on hard regs.
 ;;
 (define_insn_and_split "divmodqi4"
-  [(set (match_operand:QI 0 "pseudo_register_operand" "")
-        (div:QI (match_operand:QI 1 "pseudo_register_operand" "")
-                (match_operand:QI 2 "pseudo_register_operand" "")))
-   (set (match_operand:QI 3 "pseudo_register_operand" "")
+  [(set (match_operand:QI 0 "pseudo_register_operand")
+        (div:QI (match_operand:QI 1 "pseudo_register_operand")
+                (match_operand:QI 2 "pseudo_register_operand")))
+   (set (match_operand:QI 3 "pseudo_register_operand")
         (mod:QI (match_dup 1) (match_dup 2)))
    (clobber (reg:QI 22))
    (clobber (reg:QI 23))
    (clobber (reg:QI 24))
    (clobber (reg:QI 25))]
   ""
-  "this divmodqi4 pattern should have been splitted;"
+  { gcc_unreachable(); }
   ""
   [(set (reg:QI 24) (match_dup 1))
    (set (reg:QI 22) (match_dup 2))
@@ -3752,17 +3772,17 @@ (define_insn "*divmodqi4_call"
   [(set_attr "type" "xcall")])
 
 (define_insn_and_split "udivmodqi4"
- [(set (match_operand:QI 0 "pseudo_register_operand" "")
-       (udiv:QI (match_operand:QI 1 "pseudo_register_operand" "")
-                (match_operand:QI 2 "pseudo_register_operand" "")))
-       (set (match_operand:QI 3 "pseudo_register_operand" "")
-            (umod:QI (match_dup 1) (match_dup 2)))
-       (clobber (reg:QI 22))
-       (clobber (reg:QI 23))
-       (clobber (reg:QI 24))
-       (clobber (reg:QI 25))]
-  ""
-  "this udivmodqi4 pattern should have been splitted;"
+ [(set (match_operand:QI 0 "pseudo_register_operand")
+       (udiv:QI (match_operand:QI 1 "pseudo_register_operand")
+                (match_operand:QI 2 "pseudo_register_operand")))
+  (set (match_operand:QI 3 "pseudo_register_operand")
+       (umod:QI (match_dup 1) (match_dup 2)))
+  (clobber (reg:QI 22))
+  (clobber (reg:QI 23))
+  (clobber (reg:QI 24))
+  (clobber (reg:QI 25))]
+  ""
+  { gcc_unreachable(); }
   ""
   [(set (reg:QI 24) (match_dup 1))
    (set (reg:QI 22) (match_dup 2))
@@ -3794,17 +3814,17 @@ (define_insn "*udivmodqi4_call"
   [(set_attr "type" "xcall")])
 
 (define_insn_and_split "divmodhi4"
-  [(set (match_operand:HI 0 "pseudo_register_operand" "")
-        (div:HI (match_operand:HI 1 "pseudo_register_operand" "")
-                (match_operand:HI 2 "pseudo_register_operand" "")))
-   (set (match_operand:HI 3 "pseudo_register_operand" "")
+  [(set (match_operand:HI 0 "pseudo_register_operand")
+        (div:HI (match_operand:HI 1 "pseudo_register_operand")
+                (match_operand:HI 2 "pseudo_register_operand")))
+   (set (match_operand:HI 3 "pseudo_register_operand")
         (mod:HI (match_dup 1) (match_dup 2)))
    (clobber (reg:QI 21))
    (clobber (reg:HI 22))
    (clobber (reg:HI 24))
    (clobber (reg:HI 26))]
   ""
-  "this should have been splitted;"
+  { gcc_unreachable(); }
   ""
   [(set (reg:HI 24) (match_dup 1))
    (set (reg:HI 22) (match_dup 2))
@@ -3840,17 +3860,17 @@ (define_insn "*divmodhi4_call"
   [(set_attr "type" "xcall")])
 
 (define_insn_and_split "udivmodhi4"
-  [(set (match_operand:HI 0 "pseudo_register_operand" "")
-        (udiv:HI (match_operand:HI 1 "pseudo_register_operand" "")
-                 (match_operand:HI 2 "pseudo_register_operand" "")))
-   (set (match_operand:HI 3 "pseudo_register_operand" "")
+  [(set (match_operand:HI 0 "pseudo_register_operand")
+        (udiv:HI (match_operand:HI 1 "pseudo_register_operand")
+                 (match_operand:HI 2 "pseudo_register_operand")))
+   (set (match_operand:HI 3 "pseudo_register_operand")
         (umod:HI (match_dup 1) (match_dup 2)))
    (clobber (reg:QI 21))
    (clobber (reg:HI 22))
    (clobber (reg:HI 24))
    (clobber (reg:HI 26))]
   ""
-  "this udivmodhi4 pattern should have been splitted.;"
+  { gcc_unreachable(); }
   ""
   [(set (reg:HI 24) (match_dup 1))
    (set (reg:HI 22) (match_dup 2))
@@ -3925,7 +3945,7 @@ (define_insn_and_split "*umulqihipsi3_split"
   [(parallel [(set (match_dup 0)
                    (mult:PSI (zero_extend:PSI (match_dup 1))
                              (zero_extend:PSI (match_dup 2))))
-               (clobber (reg:CC REG_CC))])])
+              (clobber (reg:CC REG_CC))])])
 
 (define_insn "*umulqihipsi3"
   [(set (match_operand:PSI 0 "register_operand"                         "=&r")
@@ -4091,14 +4111,14 @@ (define_insn "*mulpsi3.libgcc"
 ;; implementation works the other way round.
 
 (define_insn_and_split "divmodpsi4"
-  [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
-                   (div:PSI (match_operand:PSI 1 "pseudo_register_operand" "")
-                            (match_operand:PSI 2 "pseudo_register_operand" "")))
-              (set (match_operand:PSI 3 "pseudo_register_operand" "")
-                   (mod:PSI (match_dup 1)
-                            (match_dup 2)))
-              (clobber (reg:DI 18))
-              (clobber (reg:QI 26))])]
+  [(set (match_operand:PSI 0 "pseudo_register_operand")
+        (div:PSI (match_operand:PSI 1 "pseudo_register_operand")
+                 (match_operand:PSI 2 "pseudo_register_operand")))
+   (set (match_operand:PSI 3 "pseudo_register_operand")
+        (mod:PSI (match_dup 1)
+                 (match_dup 2)))
+   (clobber (reg:DI 18))
+   (clobber (reg:QI 26))]
   ""
   { gcc_unreachable(); }
   ""
@@ -4140,14 +4160,14 @@ (define_insn "*divmodpsi4_call"
   [(set_attr "type" "xcall")])
 
 (define_insn_and_split "udivmodpsi4"
-  [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
-                   (udiv:PSI (match_operand:PSI 1 "pseudo_register_operand" "")
-                             (match_operand:PSI 2 "pseudo_register_operand" "")))
-              (set (match_operand:PSI 3 "pseudo_register_operand" "")
-                   (umod:PSI (match_dup 1)
-                             (match_dup 2)))
-              (clobber (reg:DI 18))
-              (clobber (reg:QI 26))])]
+  [(set (match_operand:PSI 0 "pseudo_register_operand")
+        (udiv:PSI (match_operand:PSI 1 "pseudo_register_operand")
+                  (match_operand:PSI 2 "pseudo_register_operand")))
+   (set (match_operand:PSI 3 "pseudo_register_operand")
+        (umod:PSI (match_dup 1)
+                  (match_dup 2)))
+   (clobber (reg:DI 18))
+   (clobber (reg:QI 26))]
   ""
   { gcc_unreachable(); }
   ""
@@ -4191,17 +4211,18 @@ (define_insn "*udivmodpsi4_call"
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (define_insn_and_split "divmodsi4"
-  [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
-                   (div:SI (match_operand:SI 1 "pseudo_register_operand" "")
-                           (match_operand:SI 2 "pseudo_register_operand" "")))
-              (set (match_operand:SI 3 "pseudo_register_operand" "")
-                   (mod:SI (match_dup 1) (match_dup 2)))
-              (clobber (reg:SI 18))
-              (clobber (reg:SI 22))
-              (clobber (reg:HI 26))
-              (clobber (reg:HI 30))])]
+  [(set (match_operand:SI 0 "pseudo_register_operand")
+        (div:SI (match_operand:SI 1 "pseudo_register_operand")
+                (match_operand:SI 2 "pseudo_register_operand")))
+   (set (match_operand:SI 3 "pseudo_register_operand")
+        (mod:SI (match_dup 1)
+	        (match_dup 2)))
+   (clobber (reg:SI 18))
+   (clobber (reg:SI 22))
+   (clobber (reg:HI 26))
+   (clobber (reg:HI 30))]
   ""
-  "this divmodsi4 pattern should have been splitted;"
+  { gcc_unreachable(); }
   ""
   [(set (reg:SI 22) (match_dup 1))
    (set (reg:SI 18) (match_dup 2))
@@ -4237,17 +4258,18 @@ (define_insn "*divmodsi4_call"
   [(set_attr "type" "xcall")])
 
 (define_insn_and_split "udivmodsi4"
-  [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
-                   (udiv:SI (match_operand:SI 1 "pseudo_register_operand" "")
-                           (match_operand:SI 2 "pseudo_register_operand" "")))
-              (set (match_operand:SI 3 "pseudo_register_operand" "")
-                   (umod:SI (match_dup 1) (match_dup 2)))
-              (clobber (reg:SI 18))
-              (clobber (reg:SI 22))
-              (clobber (reg:HI 26))
-              (clobber (reg:HI 30))])]
+  [(set (match_operand:SI 0 "pseudo_register_operand")
+        (udiv:SI (match_operand:SI 1 "pseudo_register_operand")
+                 (match_operand:SI 2 "pseudo_register_operand")))
+   (set (match_operand:SI 3 "pseudo_register_operand")
+        (umod:SI (match_dup 1)
+                 (match_dup 2)))
+   (clobber (reg:SI 18))
+   (clobber (reg:SI 22))
+   (clobber (reg:HI 26))
+   (clobber (reg:HI 30))]
   ""
-  "this udivmodsi4 pattern should have been splitted;"
+  { gcc_unreachable(); }
   ""
   [(set (reg:SI 22) (match_dup 1))
    (set (reg:SI 18) (match_dup 2))
@@ -4712,7 +4734,8 @@ (define_split
   [(parallel [(set (match_operand:HISI 0 "register_operand")
                    (bitop:HISI (match_dup 0)
                                (match_operand:HISI 1 "register_operand")))
-              (clobber (scratch:QI))])]
+              (clobber (scratch:QI))
+              (clobber (reg:CC REG_CC))])]
   "optimize
    && reload_completed"
   [(const_int 1)]
@@ -4726,6 +4749,43 @@ (define_split
     DONE;
   })
 
+;; If  $0 = $0 <op> const  requires a QI scratch, and d-reg $1 dies after
+;; the first insn, then we can replace
+;;    $0 = $1
+;;    $0 = $0 <op> const
+;; by
+;;    $1 = $1 <op> const
+;;    $0 = $1
+;; This transorms constraint alternative "r,0,n,&d" of the first operation
+;; to alternative "d,0,n,X".
+;; "*addhi3_clobber"  "*addpsi3"  "*addsi3"
+;; "*addhq3"  "*adduhq3"  "*addha3"  "*adduha3"
+;; "*addsq3"  "*addusq3"  "*addsa3"  "*addusa3"
+;; "*iorhi3"  "*iorpsi3"  "*iorsi3"
+;; "*andhi3"  "*andpsi3"  "*andsi3"
+(define_peephole2
+  [(parallel [(set (match_operand:ORDERED234 0 "register_operand")
+                   (match_operand:ORDERED234 1 "d_register_operand"))
+              (clobber (reg:CC REG_CC))])
+   (parallel [(set (match_dup 0)
+                   (piaop:ORDERED234 (match_dup 0)
+                                     (match_operand:ORDERED234 2 "const_operand")))
+              ; A d-reg as scratch tells that this insn is expensive, and
+              ; that $0 is not a d-register: l-reg or something like SI:14 etc.
+              (clobber (match_operand:QI 3 "d_register_operand"))
+              (clobber (reg:CC REG_CC))])]
+  "peep2_reg_dead_p (1, operands[1])"
+  [(parallel [(set (match_dup 1)
+                   (piaop:ORDERED234 (match_dup 1)
+                                     (match_dup 2)))
+              (clobber (scratch:QI))
+              (clobber (reg:CC REG_CC))])
+   ; Unfortunately, the following insn misses a REG_DEAD note for $1,
+   ; so this peep2 works only once.
+   (parallel [(set (match_dup 0)
+                   (match_dup 1))
+              (clobber (reg:CC REG_CC))])])
+
 
 ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
 ;; swap
@@ -5684,7 +5744,7 @@ (define_insn "*lshr<mode>3"
 ;; "lshrha3"  "lshruha3"
 (define_insn_and_split "lshr<mode>3"
   [(set (match_operand:ALL2 0 "register_operand"                "=r,r,r,r,r,r,r")
-        (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand"    "0,0,0,r,0,0,0")
+        (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand"  "0,0,0,r,0,0,0")
                        (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
   ""
   "#"
@@ -5696,7 +5756,7 @@ (define_insn_and_split "lshr<mode>3"
 
 (define_insn "*lshr<mode>3"
   [(set (match_operand:ALL2 0 "register_operand"                "=r,r,r,r,r,r,r")
-        (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand"    "0,0,0,r,0,0,0")
+        (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand"  "0,0,0,r,0,0,0")
                        (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
    (clobber (reg:CC REG_CC))]
   "reload_completed"
@@ -6449,80 +6509,41 @@ (define_insn_and_split "zero_extendsidi2"
 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
 ;; compare
 
-; Optimize negated tests into reverse compare if overflow is undefined.
-(define_insn "*negated_tstqi"
+;; "*swapped_tstqi"  "*swapped_tstqq"
+(define_insn "*swapped_tst<mode>"
   [(set (reg:CC REG_CC)
-        (compare:CC (neg:QI (match_operand:QI 0 "register_operand" "r"))
-                 (const_int 0)))]
-  "reload_completed && !flag_wrapv && !flag_trapv"
-  "cp __zero_reg__,%0"
-  [(set_attr "length" "1")])
-
-(define_insn "*reversed_tstqi"
-  [(set (reg:CC REG_CC)
-        (compare:CC (const_int 0)
-                 (match_operand:QI 0 "register_operand" "r")))]
+        (compare:CC (match_operand:ALLs1 0 "const0_operand"   "Y00")
+                    (match_operand:ALLs1 1 "register_operand" "r")))]
   "reload_completed"
-  "cp __zero_reg__,%0"
-[(set_attr "length" "2")])
+  "cp __zero_reg__,%1"
+[(set_attr "length" "1")])
 
-(define_insn "*negated_tsthi"
-  [(set (reg:CC REG_CC)
-        (compare:CC (neg:HI (match_operand:HI 0 "register_operand" "r"))
-                 (const_int 0)))]
-  "reload_completed && !flag_wrapv && !flag_trapv"
-  "cp __zero_reg__,%A0
-	cpc __zero_reg__,%B0"
-[(set_attr "length" "2")])
-
-;; Leave here the clobber used by the cmphi pattern for simplicity, even
-;; though it is unused, because this pattern is synthesized by avr_reorg.
-(define_insn "*reversed_tsthi"
+
+;; "*swapped_tsthi"  "*swapped_tsthq"  "*swapped_tstha"
+(define_insn "*swapped_tst<mode>"
   [(set (reg:CC REG_CC)
-        (compare:CC (const_int 0)
-                 (match_operand:HI 0 "register_operand" "r")))
-   (clobber (match_scratch:QI 1 "=X"))]
+        (compare:CC (match_operand:ALLs2 0 "const0_operand"   "Y00")
+                    (match_operand:ALLs2 1 "register_operand" "r")))]
   "reload_completed"
-  "cp __zero_reg__,%A0
-	cpc __zero_reg__,%B0"
-[(set_attr "length" "2")])
+  "cp __zero_reg__,%A1
+	cpc __zero_reg__,%B1"
+  [(set_attr "length" "2")])
 
-(define_insn "*negated_tstpsi"
-  [(set (reg:CC REG_CC)
-        (compare:CC (neg:PSI (match_operand:PSI 0 "register_operand" "r"))
-                 (const_int 0)))]
-  "reload_completed && !flag_wrapv && !flag_trapv"
-  "cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0"
-  [(set_attr "length" "3")])
 
-(define_insn "*reversed_tstpsi"
+(define_insn "*swapped_tstpsi"
   [(set (reg:CC REG_CC)
         (compare:CC (const_int 0)
-                 (match_operand:PSI 0 "register_operand" "r")))
-   (clobber (match_scratch:QI 1 "=X"))]
+                    (match_operand:PSI 0 "register_operand" "r")))]
   "reload_completed"
   "cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0"
   [(set_attr "length" "3")])
 
-(define_insn "*negated_tstsi"
-  [(set (reg:CC REG_CC)
-        (compare:CC (neg:SI (match_operand:SI 0 "register_operand" "r"))
-                 (const_int 0)))]
-  "reload_completed && !flag_wrapv && !flag_trapv"
-  "cp __zero_reg__,%A0
-	cpc __zero_reg__,%B0
-	cpc __zero_reg__,%C0
-	cpc __zero_reg__,%D0"
-  [(set_attr "length" "4")])
 
-;; "*reversed_tstsi"
-;; "*reversed_tstsq" "*reversed_tstusq"
-;; "*reversed_tstsa" "*reversed_tstusa"
-(define_insn "*reversed_tst<mode>"
+;; "*swapped_tstsi"  "*swapped_tstsq"  "*swapped_tstsa"
+(define_insn "*swapped_tst<mode>"
   [(set (reg:CC REG_CC)
-        (compare:CC (match_operand:ALL4 0 "const0_operand"   "Y00")
-                 (match_operand:ALL4 1 "register_operand" "r")))
-   (clobber (match_scratch:QI 2 "=X"))]
+        (compare:CC (match_operand:ALLs4 0 "const0_operand"   "Y00")
+                    (match_operand:ALLs4 1 "register_operand" "r")))]
   "reload_completed"
   "cp __zero_reg__,%A1
 	cpc __zero_reg__,%B1
@@ -6536,38 +6557,40 @@ (define_insn "*reversed_tst<mode>"
 (define_insn "cmp<mode>3"
   [(set (reg:CC REG_CC)
         (compare:CC (match_operand:ALL1 0 "register_operand"  "r  ,r,d")
-                 (match_operand:ALL1 1 "nonmemory_operand" "Y00,r,i")))]
+                    (match_operand:ALL1 1 "nonmemory_operand" "Y00,r,i")))]
   "reload_completed"
   "@
-	tst %0
+	cp %0, __zero_reg__
 	cp %0,%1
 	cpi %0,lo8(%1)"
   [(set_attr "length" "1,1,1")])
 
-(define_insn "*cmpqi_sign_extend"
-  [(set (reg:CC REG_CC)
-        (compare:CC (sign_extend:HI (match_operand:QI 0 "register_operand" "d"))
-                 (match_operand:HI 1 "s8_operand"                       "n")))]
-  "reload_completed"
-  "cpi %0,lo8(%1)"
-  [(set_attr "length" "1")])
 
-
-(define_insn "*cmphi.zero-extend.0"
+;; May be generated by "*cbranch<HISI:mode>.<code><QIPSI:mode>.0/1".
+(define_insn "*cmp<HISI:mode>.<code><QIPSI:mode>.0"
   [(set (reg:CC REG_CC)
-        (compare:CC (zero_extend:HI (match_operand:QI 0 "register_operand" "r"))
-                 (match_operand:HI 1 "register_operand" "r")))]
-  "reload_completed"
-  "cp %0,%A1\;cpc __zero_reg__,%B1"
-  [(set_attr "length" "2")])
+        (compare:CC (any_extend:HISI (match_operand:QIPSI 0 "register_operand" "r"))
+                    (match_operand:HISI 1 "register_operand" "r")))]
+  "reload_completed
+   && GET_MODE_SIZE (<HISI:MODE>mode) > GET_MODE_SIZE (<QIPSI:MODE>mode)"
+  {
+    return avr_out_cmp_ext (operands, <CODE>, nullptr);
+  }
+  [(set_attr "adjust_len" "cmp_<extend_su>ext")])
 
-(define_insn "*cmphi.zero-extend.1"
+;; Swapped version of the above.
+;; May be generated by "*cbranch<HISI:mode>.<code><QIPSI:mode>.0/1".
+(define_insn "*cmp<HISI:mode>.<code><QIPSI:mode>.1"
   [(set (reg:CC REG_CC)
-        (compare:CC (match_operand:HI 0 "register_operand" "r")
-                 (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))))]
-  "reload_completed"
-  "cp %A0,%1\;cpc %B0,__zero_reg__"
-  [(set_attr "length" "2")])
+        (compare:CC (match_operand:HISI 0 "register_operand" "r")
+                    (any_extend:HISI (match_operand:QIPSI 1 "register_operand" "r"))))]
+  "reload_completed
+   && GET_MODE_SIZE (<HISI:MODE>mode) > GET_MODE_SIZE (<QIPSI:MODE>mode)"
+  {
+    return avr_out_cmp_ext (operands, <CODE>, nullptr);
+  }
+  [(set_attr "adjust_len" "cmp_<extend_su>ext")])
+
 
 ;; "cmphi3"
 ;; "cmphq3" "cmpuhq3"
@@ -6575,8 +6598,8 @@ (define_insn "*cmphi.zero-extend.1"
 (define_insn "cmp<mode>3"
   [(set (reg:CC REG_CC)
         (compare:CC (match_operand:ALL2 0 "register_operand"  "!w  ,r  ,r,d ,r  ,d,r")
-                 (match_operand:ALL2 1 "nonmemory_operand"  "Y00,Y00,r,s ,s  ,M,n Ynn")))
-   (clobber (match_scratch:QI 2                            "=X  ,X  ,X,&d,&d ,X,&d"))]
+                    (match_operand:ALL2 1 "nonmemory_operand"  "Y00,Y00,r,s ,s  ,M,n Ynn")))
+   (clobber (match_scratch:QI 2                               "=X  ,X  ,X,&d,&d ,X,&d"))]
   "reload_completed"
   {
     switch (which_alternative)
@@ -6603,14 +6626,14 @@ (define_insn "cmp<mode>3"
 
     return avr_out_compare (insn, operands, NULL);
   }
-  [(set_attr "length" "1,2,2,3,4,2,4")
+  [(set_attr "length" "2,2,2,3,4,2,4")
    (set_attr "adjust_len" "tsthi,tsthi,*,*,*,compare,compare")])
 
 (define_insn "*cmppsi"
   [(set (reg:CC REG_CC)
         (compare:CC (match_operand:PSI 0 "register_operand"  "r,r,d ,r  ,d,r")
-                 (match_operand:PSI 1 "nonmemory_operand" "L,r,s ,s  ,M,n")))
-   (clobber (match_scratch:QI 2                          "=X,X,&d,&d ,X,&d"))]
+                    (match_operand:PSI 1 "nonmemory_operand" "L,r,s ,s  ,M,n")))
+   (clobber (match_scratch:QI 2                             "=X,X,&d,&d ,X,&d"))]
   "reload_completed"
   {
     switch (which_alternative)
@@ -6641,8 +6664,8 @@ (define_insn "*cmppsi"
 (define_insn "*cmp<mode>"
   [(set (reg:CC REG_CC)
         (compare:CC (match_operand:ALL4 0 "register_operand"  "r  ,r ,d,r ,r")
-                 (match_operand:ALL4 1 "nonmemory_operand" "Y00,r ,M,M ,n Ynn")))
-   (clobber (match_scratch:QI 2                           "=X  ,X ,X,&d,&d"))]
+                    (match_operand:ALL4 1 "nonmemory_operand" "Y00,r ,M,M ,n Ynn")))
+   (clobber (match_scratch:QI 2                              "=X  ,X ,X,&d,&d"))]
   "reload_completed"
   {
     if (0 == which_alternative)
@@ -6656,6 +6679,13 @@ (define_insn "*cmp<mode>"
    (set_attr "adjust_len" "tstsi,*,compare,compare,compare")])
 
 
+;; A helper for avr_pass_ifelse::avr_rest_of_handle_ifelse().
+(define_expand "gen_compare<mode>"
+  [(parallel [(set (reg:CC REG_CC)
+                   (compare:CC (match_operand:HISI 0 "register_operand")
+                               (match_operand:HISI 1 "const_int_operand")))
+              (clobber (match_operand:QI 2 "scratch_operand"))])])
+
 ;; ----------------------------------------------------------------------
 ;; JUMP INSTRUCTIONS
 ;; ----------------------------------------------------------------------
@@ -6664,53 +6694,67 @@ (define_insn "*cmp<mode>"
 (define_expand "cbranch<mode>4"
   [(set (pc)
         (if_then_else (match_operator 0 "ordered_comparison_operator"
-                        [(match_operand:ALL1 1 "register_operand" "")
-                         (match_operand:ALL1 2 "nonmemory_operand" "")])
-         (label_ref (match_operand 3 "" ""))
-         (pc)))])
+                        [(match_operand:ALL1 1 "register_operand")
+                         (match_operand:ALL1 2 "nonmemory_operand")])
+                      (label_ref (match_operand 3))
+                      (pc)))]
+  ""
+  {
+    int icode = (int) GET_CODE (operands[0]);
+
+    targetm.canonicalize_comparison (&icode, &operands[1], &operands[2], false);
+    PUT_CODE (operands[0], (enum rtx_code) icode);
+  })
 
 (define_expand "cbranch<mode>4"
   [(parallel
      [(set (pc)
-           (if_then_else
-             (match_operator 0 "ordered_comparison_operator"
-               [(match_operand:ORDERED234 1 "register_operand" "")
-                (match_operand:ORDERED234 2 "nonmemory_operand" "")])
-             (label_ref (match_operand 3 "" ""))
-             (pc)))
-      (clobber (match_scratch:QI 4 ""))])])
-
-;; "*cbranchqi4"
-;; "*cbranchqq4"  "*cbranchuqq4"
-(define_insn_and_split "*cbranch<mode>4"
+           (if_then_else (match_operator 0 "ordered_comparison_operator"
+                           [(match_operand:ALL234 1 "register_operand")
+                            (match_operand:ALL234 2 "nonmemory_operand")])
+                         (label_ref (match_operand 3))
+                         (pc)))
+      (clobber (match_scratch:QI 4))])]
+  ""
+  {
+    int icode = (int) GET_CODE (operands[0]);
+
+    targetm.canonicalize_comparison (&icode, &operands[1], &operands[2], false);
+    PUT_CODE (operands[0], (enum rtx_code) icode);
+  })
+
+
+;; "cbranchqi4_insn"
+;; "cbranchqq4_insn"  "cbranchuqq4_insn"
+(define_insn_and_split "cbranch<mode>4_insn"
   [(set (pc)
         (if_then_else (match_operator 0 "ordered_comparison_operator"
-                        [(match_operand:ALL1 1 "register_operand" "r  ,r,d")
+                        [(match_operand:ALL1 1 "register_operand"  "r  ,r,d")
                          (match_operand:ALL1 2 "nonmemory_operand" "Y00,r,i")])
-         (label_ref (match_operand 3 "" ""))
-         (pc)))]
+                      (label_ref (match_operand 3))
+                      (pc)))]
    ""
    "#"
    "reload_completed"
    [(set (reg:CC REG_CC)
-                    (compare:CC (match_dup 1) (match_dup 2)))
+         (compare:CC (match_dup 1) (match_dup 2)))
     (set (pc)
          (if_then_else (match_op_dup 0
                          [(reg:CC REG_CC) (const_int 0)])
                        (label_ref (match_dup 3))
-                       (pc)))]
-   "")
+                       (pc)))])
 
-;; "*cbranchsi4"  "*cbranchsq4"  "*cbranchusq4"  "*cbranchsa4"  "*cbranchusa4"
-(define_insn_and_split "*cbranch<mode>4"
+;; "cbranchsi4_insn"
+;; "cbranchsq4_insn"  "cbranchusq4_insn"  "cbranchsa4_insn"  "cbranchusa4_insn"
+(define_insn_and_split "cbranch<mode>4_insn"
   [(set (pc)
-           (if_then_else
-             (match_operator 0 "ordered_comparison_operator"
-               [(match_operand:ALL4 1 "register_operand" "r  ,r ,d,r ,r")
-                (match_operand:ALL4 2 "nonmemory_operand" "Y00,r ,M,M ,n Ynn")])
-             (label_ref (match_operand 3 "" ""))
-             (pc)))
-   (clobber (match_scratch:QI 4 "=X  ,X ,X,&d,&d"))]
+        (if_then_else
+         (match_operator 0 "ordered_comparison_operator"
+           [(match_operand:ALL4 1 "register_operand"  "r  ,r,d,r ,r")
+            (match_operand:ALL4 2 "nonmemory_operand" "Y00,r,M,M ,n Ynn")])
+         (label_ref (match_operand 3))
+         (pc)))
+   (clobber (match_scratch:QI 4                      "=X  ,X,X,&d,&d"))]
    ""
    "#"
    "reload_completed"
@@ -6721,19 +6765,18 @@ (define_insn_and_split "*cbranch<mode>4"
          (if_then_else (match_op_dup 0
                          [(reg:CC REG_CC) (const_int 0)])
                        (label_ref (match_dup 3))
-                       (pc)))]
-   "")
+                       (pc)))])
 
-;; "*cbranchpsi4"
-(define_insn_and_split "*cbranchpsi4"
+;; "cbranchpsi4_insn"
+(define_insn_and_split "cbranchpsi4_insn"
   [(set (pc)
-           (if_then_else
-             (match_operator 0 "ordered_comparison_operator"
-               [(match_operand:PSI 1 "register_operand" "r,r,d ,r  ,d,r")
-                (match_operand:PSI 2 "nonmemory_operand" "L,r,s ,s  ,M,n")])
-             (label_ref (match_operand 3 "" ""))
-             (pc)))
-   (clobber (match_scratch:QI 4 "=X,X,&d,&d ,X,&d"))]
+        (if_then_else
+         (match_operator 0 "ordered_comparison_operator"
+           [(match_operand:PSI 1 "register_operand"  "r,r,d ,r ,d,r")
+            (match_operand:PSI 2 "nonmemory_operand" "L,r,s ,s ,M,n")])
+         (label_ref (match_operand 3))
+         (pc)))
+   (clobber (match_scratch:QI 4                     "=X,X,&d,&d,X,&d"))]
    ""
    "#"
    "reload_completed"
@@ -6744,19 +6787,19 @@ (define_insn_and_split "*cbranchpsi4"
          (if_then_else (match_op_dup 0
                          [(reg:CC REG_CC) (const_int 0)])
                        (label_ref (match_dup 3))
-                       (pc)))]
-   "")
+                       (pc)))])
 
-;; "*cbranchhi4"  "*cbranchhq4"  "*cbranchuhq4"  "*cbranchha4"  "*cbranchuha4"
-(define_insn_and_split "*cbranch<mode>4"
+;; "cbranchhi4_insn"
+;; "cbranchhq4_insn"  "cbranchuhq4_insn"  "cbranchha4_insn"  "cbranchuha4_insn"
+(define_insn_and_split "cbranch<mode>4_insn"
   [(set (pc)
-           (if_then_else
-             (match_operator 0 "ordered_comparison_operator"
-               [(match_operand:ALL2 1 "register_operand" "!w  ,r  ,r,d ,r  ,d,r")
-                (match_operand:ALL2 2 "nonmemory_operand" "Y00,Y00,r,s ,s  ,M,n Ynn")])
-             (label_ref (match_operand 3 "" ""))
-             (pc)))
-   (clobber (match_scratch:QI 4 "=X  ,X  ,X,&d,&d ,X,&d"))]
+        (if_then_else
+         (match_operator 0 "ordered_comparison_operator"
+           [(match_operand:ALL2 1 "register_operand" "!w  ,r  ,r,d ,r ,d,r")
+            (match_operand:ALL2 2 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn")])
+         (label_ref (match_operand 3))
+         (pc)))
+   (clobber (match_scratch:QI 4                      "=X  ,X  ,X,&d,&d,X,&d"))]
    ""
    "#"
    "reload_completed"
@@ -6767,8 +6810,71 @@ (define_insn_and_split "*cbranch<mode>4"
          (if_then_else (match_op_dup 0
                          [(reg:CC REG_CC) (const_int 0)])
                        (label_ref (match_dup 3))
-                       (pc)))]
-   "")
+                       (pc)))])
+
+;; Combiner pattern to compare sign- or zero-extended register against
+;; a wider register, like comparing uint8_t against uint16_t.
+(define_insn_and_split "*cbranch<HISI:mode>.<code><QIPSI:mode>.0"
+  [(set (pc)
+        (if_then_else (match_operator 0 "ordered_comparison_operator"
+                        [(any_extend:HISI (match_operand:QIPSI 1 "register_operand" "r"))
+                         (match_operand:HISI 2 "register_operand" "r")])
+                      (label_ref (match_operand 3))
+                      (pc)))]
+  "optimize
+   && GET_MODE_SIZE (<HISI:MODE>mode) > GET_MODE_SIZE (<QIPSI:MODE>mode)"
+  "#"
+  "&& reload_completed"
+  [; "*cmp<HISI:mode>.<code><QIPSI:mode>.0"
+   (set (reg:CC REG_CC)
+        (compare:CC (match_dup 1)
+                    (match_dup 2)))
+   ; "branch"
+   (set (pc)
+        (if_then_else (match_op_dup 0 [(reg:CC REG_CC)
+                                       (const_int 0)])
+                      (label_ref (match_dup 3))
+                      (pc)))]
+  {
+    operands[1] = gen_rtx_<CODE> (<HISI:MODE>mode, operands[1]);
+    if (difficult_comparison_operator (operands[0], VOIDmode))
+      {
+        PUT_CODE (operands[0], swap_condition (GET_CODE (operands[0])));
+        std::swap (operands[1], operands[2]);
+      }
+  })
+
+;; Same combiner pattern, but with swapped operands.
+(define_insn_and_split "*cbranch<HISI:mode>.<code><QIPSI:mode>.0"
+  [(set (pc)
+        (if_then_else (match_operator 0 "ordered_comparison_operator"
+                        [(match_operand:HISI 1 "register_operand" "r")
+                         (any_extend:HISI (match_operand:QIPSI 2 "register_operand" "r"))])
+                      (label_ref (match_operand 3))
+                      (pc)))]
+  "optimize
+   && GET_MODE_SIZE (<HISI:MODE>mode) > GET_MODE_SIZE (<QIPSI:MODE>mode)"
+  "#"
+  "&& reload_completed"
+  [; "*cmp<HISI:mode>.<code><QIPSI:mode>.0"
+   (set (reg:CC REG_CC)
+        (compare:CC (match_dup 1)
+                    (match_dup 2)))
+   ; "branch"
+   (set (pc)
+        (if_then_else (match_op_dup 0 [(reg:CC REG_CC)
+                                       (const_int 0)])
+                      (label_ref (match_dup 3))
+                      (pc)))]
+  {
+    operands[2] = gen_rtx_<CODE> (<HISI:MODE>mode, operands[2]);
+    if (difficult_comparison_operator (operands[0], VOIDmode))
+      {
+        PUT_CODE (operands[0], swap_condition (GET_CODE (operands[0])));
+        std::swap (operands[1], operands[2]);
+      }
+  })
+
 
 ;; Test a single bit in a QI/HI/SImode register.
 ;; Combine will create zero extract patterns for single bit tests.
@@ -6842,14 +6948,11 @@ (define_insn_and_split "*sbrx_and_branch<mode>_split"
   "#"
   "&& reload_completed"
   [(parallel [(set (pc)
-                   (if_then_else
-                   (match_op_dup 0
-                                 [(and:QISI
-                                   (match_dup 1)
-                                   (match_dup 2))
-                                  (const_int 0)])
-                   (label_ref (match_dup 3))
-                   (pc)))
+                   (if_then_else (match_op_dup 0 [(and:QISI (match_dup 1)
+                                                            (match_dup 2))
+                                                  (const_int 0)])
+                                 (label_ref (match_dup 3))
+                                 (pc)))
               (clobber (reg:CC REG_CC))])])
 
 (define_insn "*sbrx_and_branch<mode>"
@@ -6878,163 +6981,77 @@ (define_insn "*sbrx_and_branch<mode>"
                                     (const_int 2)
                                     (const_int 4))))])
 
-;; Convert sign tests to bit 7/15/31 tests that match the above insns.
-(define_peephole2
-  [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "")
-                       (const_int 0)))
-   (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0))
-                                      (label_ref (match_operand 1 "" ""))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
-  [(parallel [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0)
-                                                           (const_int 1)
-                                                           (const_int 7))
-                                          (const_int 0))
-                                      (label_ref (match_dup 1))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])])
 
-(define_peephole2
-  [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "")
-                       (const_int 0)))
-   (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0))
-                                      (label_ref (match_operand 1 "" ""))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
-  [(parallel [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0)
-                                                           (const_int 1)
-                                                           (const_int 7))
-                                          (const_int 0))
-                                      (label_ref (match_dup 1))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])])
-
-(define_peephole2
-  [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "")
-                                  (const_int 0)))
-              (clobber (match_operand:HI 2 ""))])
-   (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0))
-                                      (label_ref (match_operand 1 "" ""))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
-  [(parallel [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
-                                          (const_int 0))
-                                      (label_ref (match_dup 1))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])])
-
-(define_peephole2
-  [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "")
-                                  (const_int 0)))
-              (clobber (match_operand:HI 2 ""))])
-   (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0))
-                                      (label_ref (match_operand 1 "" ""))
-                                      (pc)))
+;; Convert sign tests to bit 7 tests that match the above insns.
+(define_peephole2 ; "*sbrx_branch<mode>"
+  [(set (reg:CC REG_CC)
+        (compare:CC (match_operand:ALLs1 0 "register_operand")
+                    (match_operand:ALLs1 1 "const0_operand")))
+   (set (pc)
+        (if_then_else (gelt (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "peep2_regno_dead_p (2, REG_CC)"
+  [(parallel [(set (pc)
+                   (if_then_else (<gelt_eqne> (zero_extract:HI (match_dup 0)
+                                                               (const_int 1)
+                                                               (match_dup 1))
+                                              (const_int 0))
+                                 (label_ref (match_dup 2))
+                                 (pc)))
               (clobber (reg:CC REG_CC))])]
-  ""
-  [(parallel [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
-                                          (const_int 0))
-                                      (label_ref (match_dup 1))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])])
+  {
+    operands[0] = avr_to_int_mode (operands[0]);
+    operands[1] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
+  })
 
-(define_peephole2
-  [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "")
-                                  (const_int 0)))
-              (clobber (match_operand:SI 2 ""))])
-   (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0))
-                                      (label_ref (match_operand 1 "" ""))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
-  [(parallel [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
-                                          (const_int 0))
-                                      (label_ref (match_dup 1))
-                                      (pc)))
+;; Convert sign tests to bit 15/23/31 tests that match the above insns.
+(define_peephole2 ; "*sbrx_branch<mode>"
+  [(parallel [(set (reg:CC REG_CC)
+                   (compare:CC (match_operand:ALLs234 0 "register_operand")
+                               (match_operand:ALLs234 1 "const0_operand")))
+              (clobber (match_operand:QI 3 "scratch_operand"))])
+   (set (pc)
+        (if_then_else (gelt (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "peep2_regno_dead_p (2, REG_CC)"
+  [(parallel [(set (pc)
+                   (if_then_else (<gelt_eqne> (zero_extract:HI (match_dup 0)
+                                                               (const_int 1)
+                                                               (match_dup 1))
+                                              (const_int 0))
+                                 (label_ref (match_dup 2))
+                                 (pc)))
               (clobber (reg:CC REG_CC))])]
-  "operands[2] = gen_int_mode (-2147483647 - 1, SImode);")
+  {
+    operands[0] = avr_to_int_mode (operands[0]);
+    operands[1] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
+  })
 
-(define_peephole2
-  [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "")
-                                  (const_int 0)))
-              (clobber (match_operand:SI 2 ""))])
-   (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0))
-                                      (label_ref (match_operand 1 "" ""))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
-  [(parallel [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
-                                          (const_int 0))
-                                      (label_ref (match_dup 1))
-                                      (pc)))
-              (clobber (reg:CC REG_CC))])]
-  "operands[2] = gen_int_mode (-2147483647 - 1, SImode);")
 
 ;; ************************************************************************
 ;; Implementation of conditional jumps here.
 ;;  Compare with 0 (test) jumps
 ;; ************************************************************************
 
-(define_insn_and_split "branch"
+(define_insn "branch"
   [(set (pc)
         (if_then_else (match_operator 1 "simple_comparison_operator"
-                                      [(reg:CC REG_CC)
-                                       (const_int 0)])
-                      (label_ref (match_operand 0 "" ""))
+                        [(reg:CC REG_CC)
+                         (const_int 0)])
+                      (label_ref (match_operand 0))
                       (pc)))]
   "reload_completed"
-  "#"
-  "&& reload_completed"
-  [(parallel [(set (pc)
-                   (if_then_else (match_op_dup 1
-                                               [(reg:CC REG_CC)
-                                                (const_int 0)])
-                                 (label_ref (match_dup 0))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])])
-
-(define_insn "*branch"
-  [(set (pc)
-        (if_then_else (match_operator 1 "simple_comparison_operator"
-                                      [(reg:CC REG_CC)
-                                       (const_int 0)])
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))
-   (clobber (reg:CC REG_CC))]
-  "reload_completed"
-  {
-    return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
-  }
-  [(set_attr "type" "branch")])
-
-
-;; Same as above but wrap SET_SRC so that this branch won't be transformed
-;; or optimized in the remainder.
-
-(define_insn "branch_unspec"
-  [(set (pc)
-        (unspec [(if_then_else (match_operator 1 "simple_comparison_operator"
-                                               [(reg:CC REG_CC)
-                                                (const_int 0)])
-                               (label_ref (match_operand 0 "" ""))
-                               (pc))
-                 ] UNSPEC_IDENTITY))
-   (clobber (reg:CC REG_CC))]
-  "reload_completed"
   {
     return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
   }
   [(set_attr "type" "branch")])
 
-;; ****************************************************************
-;; AVR does not have following conditional jumps: LE,LEU,GT,GTU.
-;; Convert them all to proper jumps.
-;; ****************************************************************/
 
-(define_insn_and_split "difficult_branch"
+(define_insn "difficult_branch"
   [(set (pc)
         (if_then_else (match_operator 1 "difficult_comparison_operator"
                         [(reg:CC REG_CC)
@@ -7042,95 +7059,11 @@ (define_insn_and_split "difficult_branch"
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   "reload_completed"
-  "#"
-  "&& reload_completed"
-  [(parallel [(set (pc)
-                   (if_then_else (match_op_dup 1
-                                   [(reg:CC REG_CC)
-                                    (const_int 0)])
-                                 (label_ref (match_dup 0))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])])
-
-(define_insn "*difficult_branch"
-  [(set (pc)
-        (if_then_else (match_operator 1 "difficult_comparison_operator"
-                        [(reg:CC REG_CC)
-                         (const_int 0)])
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))
-   (clobber (reg:CC REG_CC))]
-  "reload_completed"
   {
     return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
   }
   [(set_attr "type" "branch1")])
 
-;; revers branch
-
-(define_insn_and_split "rvbranch"
-  [(set (pc)
-        (if_then_else (match_operator 1 "simple_comparison_operator"
-                                      [(reg:CC REG_CC)
-                                       (const_int 0)])
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  "reload_completed"
-  "#"
-  "&& reload_completed"
-  [(parallel [(set (pc)
-                   (if_then_else (match_op_dup 1
-                                               [(reg:CC REG_CC)
-                                                (const_int 0)])
-                                 (pc)
-                                 (label_ref (match_dup 0))))
-              (clobber (reg:CC REG_CC))])])
-
-(define_insn "*rvbranch"
-  [(set (pc)
-        (if_then_else (match_operator 1 "simple_comparison_operator"
-                                      [(reg:CC REG_CC)
-                                       (const_int 0)])
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))
-   (clobber (reg:CC REG_CC))]
-  "reload_completed"
-  {
-    return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
-  }
-  [(set_attr "type" "branch1")])
-
-(define_insn_and_split "difficult_rvbranch"
-  [(set (pc)
-        (if_then_else (match_operator 1 "difficult_comparison_operator"
-                                      [(reg:CC REG_CC)
-                                       (const_int 0)])
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  "reload_completed"
-  "#"
-  "&& reload_completed"
-  [(parallel [(set (pc)
-                   (if_then_else (match_op_dup 1
-                                               [(reg:CC REG_CC)
-                                                (const_int 0)])
-                                 (pc)
-                                 (label_ref (match_dup 0))))
-              (clobber (reg:CC REG_CC))])])
-
-(define_insn "*difficult_rvbranch"
-  [(set (pc)
-        (if_then_else (match_operator 1 "difficult_comparison_operator"
-                                      [(reg:CC REG_CC)
-                                       (const_int 0)])
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))
-   (clobber (reg:CC REG_CC))]
-  "reload_completed"
-  {
-    return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
-  }
-  [(set_attr "type" "branch")])
 
 ;; **************************************************************************
 ;; Unconditional and other jump instructions.
@@ -7656,15 +7589,14 @@ (define_peephole ; "*dec-and-branchsi!=-1.d.clobber"
               (clobber (reg:CC REG_CC))])
    (parallel [(set (reg:CC REG_CC)
                    (compare:CC (match_dup 0)
-                            (const_int -1)))
-              (clobber (match_operand:QI 1 "d_register_operand" ""))])
-   (parallel [(set (pc)
-                   (if_then_else (eqne (reg:CC REG_CC)
-                                       (const_int 0))
-                                 (label_ref (match_operand 2 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
+                               (const_int -1)))
+              (clobber (match_operand:QI 1 "scratch_or_d_register_operand"))])
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "dead_or_set_regno_p (insn, REG_CC)"
   {
     const char *op;
     int jump_mode;
@@ -7700,15 +7632,14 @@ (define_peephole ; "*dec-and-branchhi!=-1"
               (clobber (reg:CC REG_CC))])
    (parallel [(set (reg:CC REG_CC)
                    (compare:CC (match_dup 0)
-                            (const_int -1)))
+                               (const_int -1)))
               (clobber (match_operand:QI 1 "d_register_operand" ""))])
-   (parallel [(set (pc)
-                   (if_then_else (eqne (reg:CC REG_CC)
-                                       (const_int 0))
-                                 (label_ref (match_operand 2 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "dead_or_set_regno_p (insn, REG_CC)"
   {
     const char *op;
     int jump_mode;
@@ -7742,15 +7673,14 @@ (define_peephole ; "*dec-and-branchhi!=-1.d.clobber"
               (clobber (reg:CC REG_CC))])
    (parallel [(set (reg:CC REG_CC)
                    (compare:CC (match_dup 0)
-                            (const_int -1)))
-              (clobber (match_operand:QI 1 "d_register_operand" ""))])
-   (parallel [(set (pc)
-                   (if_then_else (eqne (reg:CC REG_CC)
-                                       (const_int 0))
-                                 (label_ref (match_operand 2 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
+                               (const_int -1)))
+              (clobber (match_operand:QI 1 "scratch_or_d_register_operand"))])
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "dead_or_set_regno_p (insn, REG_CC)"
   {
     const char *op;
     int jump_mode;
@@ -7784,15 +7714,14 @@ (define_peephole ; "*dec-and-branchhi!=-1.l.clobber"
               (clobber (reg:CC REG_CC))])
    (parallel [(set (reg:CC REG_CC)
                    (compare:CC (match_dup 0)
-                            (const_int -1)))
+                               (const_int -1)))
               (clobber (match_operand:QI 1 "d_register_operand" ""))])
-   (parallel [(set (pc)
-                   (if_then_else (eqne (reg:CC REG_CC)
-                                       (const_int 0))
-                                 (label_ref (match_operand 2 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "dead_or_set_regno_p (insn, REG_CC)"
   {
     const char *op;
     int jump_mode;
@@ -7822,14 +7751,13 @@ (define_peephole ; "*dec-and-branchqi!=-1"
               (clobber (reg:CC REG_CC))])
    (set (reg:CC REG_CC)
         (compare:CC (match_dup 0)
-                 (const_int -1)))
-   (parallel [(set (pc)
-                   (if_then_else (eqne (reg:CC REG_CC)
-                                       (const_int 0))
-                                 (label_ref (match_operand 1 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  ""
+                    (const_int -1)))
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 1))
+                      (pc)))]
+  "dead_or_set_regno_p (insn, REG_CC)"
   {
     const char *op;
     int jump_mode;
@@ -7855,14 +7783,14 @@ (define_peephole ; "*dec-and-branchqi!=-1"
 (define_peephole ; "*cpse.eq"
   [(set (reg:CC REG_CC)
         (compare:CC (match_operand:ALL1 1 "register_operand" "r,r")
-                 (match_operand:ALL1 2 "reg_or_0_operand" "r,Y00")))
-   (parallel [(set (pc)
-                   (if_then_else (eq (reg:CC REG_CC)
-                                     (const_int 0))
-                                 (label_ref (match_operand 0 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  "jump_over_one_insn_p (insn, operands[0])"
+                    (match_operand:ALL1 2 "reg_or_0_operand" "r,Y00")))
+   (set (pc)
+        (if_then_else (eq (reg:CC REG_CC)
+                          (const_int 0))
+                      (label_ref (match_operand 0))
+                      (pc)))]
+  "jump_over_one_insn_p (insn, operands[0])
+   && dead_or_set_regno_p (insn, REG_CC)"
   "@
 	cpse %1,%2
 	cpse %1,__zero_reg__")
@@ -7890,16 +7818,16 @@ (define_peephole ; "*cpse.eq"
 
 (define_peephole ; "*cpse.ne"
   [(set (reg:CC REG_CC)
-        (compare:CC (match_operand:ALL1 1 "register_operand" "")
-                 (match_operand:ALL1 2 "reg_or_0_operand" "")))
-   (parallel [(set (pc)
-                   (if_then_else (ne (reg:CC REG_CC)
-                                     (const_int 0))
-                                 (label_ref (match_operand 0 "" ""))
-                                 (pc)))
-              (clobber (reg:CC REG_CC))])]
-  "!AVR_HAVE_JMP_CALL
-   || !TARGET_SKIP_BUG"
+        (compare:CC (match_operand:ALL1 1 "register_operand")
+                    (match_operand:ALL1 2 "reg_or_0_operand")))
+   (set (pc)
+        (if_then_else (ne (reg:CC REG_CC)
+                          (const_int 0))
+                      (label_ref (match_operand 0))
+                      (pc)))]
+  "(!AVR_HAVE_JMP_CALL
+    || !TARGET_SKIP_BUG)
+   && dead_or_set_regno_p (insn, REG_CC)"
   {
     if (operands[2] == CONST0_RTX (<MODE>mode))
       operands[2] = zero_reg_rtx;
@@ -8094,7 +8022,7 @@ (define_insn_and_split "delay_cycles_1"
                                 (const_int 1)]
                                UNSPECV_DELAY_CYCLES)
               (set (match_dup 1)
-               (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+                   (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
               (clobber (match_dup 2))
               (clobber (reg:CC REG_CC))])])
 
@@ -8126,7 +8054,7 @@ (define_insn_and_split "delay_cycles_2"
                                 (const_int 2)]
                                UNSPECV_DELAY_CYCLES)
               (set (match_dup 1)
-               (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+                   (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
               (clobber (match_dup 2))
               (clobber (reg:CC REG_CC))])]
   ""
@@ -8163,7 +8091,7 @@ (define_insn_and_split "delay_cycles_3"
                                 (const_int 3)]
                                UNSPECV_DELAY_CYCLES)
               (set (match_dup 1)
-               (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+                   (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
               (clobber (match_dup 2))
               (clobber (match_dup 3))
               (clobber (match_dup 4))
@@ -8206,7 +8134,7 @@ (define_insn_and_split "delay_cycles_4"
                                 (const_int 4)]
                                UNSPECV_DELAY_CYCLES)
               (set (match_dup 1)
-               (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+                   (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
               (clobber (match_dup 2))
               (clobber (match_dup 3))
               (clobber (match_dup 4))
@@ -9095,16 +9023,20 @@ (define_insn "*movbitqi.1-6.b"
   "bst %3,0\;bld %0,%4"
   [(set_attr "length" "2")])
 
-;; Move bit $3.0 into bit $0.0.
-;; For bit 0, combiner generates slightly different pattern.
-(define_insn "*movbitqi.0"
-  [(set (match_operand:QI 0 "register_operand"                     "=r")
-        (ior:QI (and:QI (match_operand:QI 1 "register_operand"      "0")
-                        (match_operand:QI 2 "single_zero_operand"   "n"))
-                (and:QI (match_operand:QI 3 "register_operand"      "r")
-                        (const_int 1))))]
-  "0 == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
-  "bst %3,0\;bld %0,0"
+;; Move bit $3.x into bit $0.x.
+(define_insn "*movbit<mode>.0-6"
+  [(set (match_operand:QISI 0 "register_operand"                       "=r")
+        (ior:QISI (and:QISI (match_operand:QISI 1 "register_operand"    "0")
+                            (match_operand:QISI 2 "single_zero_operand" "n"))
+                  (and:QISI (match_operand:QISI 3 "register_operand"    "r")
+                            (match_operand:QISI 4 "single_one_operand"  "n"))))]
+  "GET_MODE_MASK(<MODE>mode)
+   == (GET_MODE_MASK(<MODE>mode) & (INTVAL(operands[2]) ^ INTVAL(operands[4])))"
+  {
+    auto bitmask = GET_MODE_MASK (<MODE>mode) & UINTVAL (operands[4]);
+    operands[4] = GEN_INT (exact_log2 (bitmask));
+    return "bst %T3%T4" CR_TAB "bld %T0%T4";
+  }
   [(set_attr "length" "2")])
 
 ;; Move bit $2.0 into bit $0.7.
@@ -9489,6 +9421,258 @@ (define_peephole2
               (clobber (reg:CC REG_CC))])])
 
 
+;; Try optimize decrement-and-branch.  When we have an addition followed
+;; by a comparison of the result against zero, we can output the addition
+;; in such a way that SREG.N and SREG.Z are set according to the result.
+
+;; { -1, +1 } for QImode, otherwise the empty set.
+(define_mode_attr p1m1 [(QI "N P")
+                        (HI "Yxx") (PSI "Yxx") (SI "Yxx")])
+
+;; FIXME: reload1.cc::do_output_reload() does not support output reloads
+;; for JUMP_INSNs, hence letting combine doing decrement-and-branch like
+;; the following might run into ICE.  Doing reloads by hand is too painful...
+;
+; (define_insn_and_split "*add.for.eqne.<mode>.cbranch"
+;   [(set (pc)
+;         (if_then_else (eqne (match_operand:QISI 1 "register_operand"  "0")
+;                             (match_operand:QISI 2 "const_int_operand" "n"))
+;                       (label_ref (match_operand 4))
+;                       (pc)))
+;    (set (match_operand:QISI 0 "register_operand" "=r")
+;         (plus:QISI (match_dup 1)
+;                    (match_operand:QISI 3 "const_int_operand" "n")))]
+;   ;; No clobber for now as combine might not have one handy.
+;   ;; We pop a scatch in split1.
+;   "!reload_completed
+;    && const0_rtx == simplify_binary_operation (PLUS, <MODE>mode,
+;                                                operands[2], operands[3])"
+;   { gcc_unreachable(); }
+;   "&& 1"
+;   [(parallel [(set (pc)
+;                    (if_then_else (eqne (match_dup 1)
+;                                        (match_dup 2))
+;                                  (label_ref (match_dup 4))
+;                                  (pc)))
+;               (set (match_dup 0)
+;                    (plus:QISI (match_dup 1)
+;                               (match_dup 3)))
+;               (clobber (scratch:QI))])])
+;
+;; ...Hence, stick with RTL peepholes for now.  Unfortunately, there is no
+;; canonical form, and if reload shuffles registers around, we might miss
+;; opportunities to match a decrement-and-branch.
+;; doloop_end doesn't reload either, so doloop_end also won't work.
+
+(define_expand "gen_add_for_<code>_<mode>"
+  ; "*add.for.eqne.<mode>"
+  [(parallel [(set (reg:CC REG_CC)
+                   (compare:CC (plus:QISI (match_operand:QISI 0 "register_operand")
+                                          (match_operand:QISI 1 "const_int_operand"))
+                               (const_int 0)))
+              (set (match_dup 0)
+                   (plus:QISI (match_dup 0)
+                              (match_dup 1)))
+              (clobber (match_operand:QI 3))])
+   ; "branch"
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_dup 2))
+                      (pc)))])
+
+
+;; 1/3: A version without clobber: d-reg or 8-bit adds +/-1.
+(define_peephole2
+  [(parallel [(set (match_operand:QISI 0 "register_operand")
+                   (plus:QISI (match_dup 0)
+                              (match_operand:QISI 1 "const_int_operand")))
+              (clobber (reg:CC REG_CC))])
+   (set (reg:CC REG_CC)
+        (compare:CC (match_dup 0)
+                    (const_int 0)))
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "peep2_regno_dead_p (3, REG_CC)
+   && (d_register_operand (operands[0], <MODE>mode)
+       || (<MODE>mode == QImode
+           && (INTVAL (operands[1]) == 1
+               || INTVAL (operands[1]) == -1)))"
+  [(scratch)]
+  {
+    emit (gen_gen_add_for_<code>_<mode> (operands[0], operands[1], operands[2],
+          gen_rtx_SCRATCH (QImode)));
+    DONE;
+  })
+
+;; 2/3: A version with clobber from the insn.
+(define_peephole2
+  [(parallel [(set (match_operand:QISI 0 "register_operand")
+                   (plus:QISI (match_dup 0)
+                              (match_operand:QISI 1 "const_int_operand")))
+              (clobber (match_operand:QI 3 "scratch_or_d_register_operand"))
+              (clobber (reg:CC REG_CC))])
+   (parallel [(set (reg:CC REG_CC)
+                   (compare:CC (match_dup 0)
+                               (const_int 0)))
+              (clobber (match_operand:QI 4 "scratch_or_d_register_operand"))])
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "peep2_regno_dead_p (3, REG_CC)"
+  [(scratch)]
+  {
+    rtx scratch = REG_P (operands[3]) ? operands[3] : operands[4];
+
+    // We need either a d-register or a scratch register to clobber.
+    if (! REG_P (scratch)
+        && ! d_register_operand (operands[0], <MODE>mode)
+        && ! (QImode == <MODE>mode
+              && (INTVAL (operands[1]) == 1
+                  || INTVAL (operands[1]) == -1)))
+      {
+        FAIL;
+      }
+    emit (gen_gen_add_for_<code>_<mode> (operands[0], operands[1], operands[2],
+          scratch));
+    DONE;
+  })
+
+;; 3/3 A version with a clobber from peephole2.
+(define_peephole2
+  [(match_scratch:QI 3 "d")
+   (parallel [(set (match_operand:QISI 0 "register_operand")
+                   (plus:QISI (match_dup 0)
+                              (match_operand:QISI 1 "const_int_operand")))
+              (clobber (reg:CC REG_CC))])
+   (set (reg:CC REG_CC)
+        (compare:CC (match_dup 0)
+                    (const_int 0)))
+   (set (pc)
+        (if_then_else (eqne (reg:CC REG_CC)
+                            (const_int 0))
+                      (label_ref (match_operand 2))
+                      (pc)))]
+  "peep2_regno_dead_p (3, REG_CC)"
+  [(scratch)]
+  {
+    emit (gen_gen_add_for_<code>_<mode> (operands[0], operands[1], operands[2],
+          operands[3]));
+    DONE;
+  })
+
+;; Result of the above three peepholes is an addition that also
+;; performs an EQ or NE comparison (of the result) against zero.
+;; FIXME: Using (match_dup 0) instead of operands[3/4] makes rnregs
+;; barf in regrename.cc::merge_overlapping_regs().  For now, use the
+;; fix from PR50788: Constrain as "0".
+(define_insn "*add.for.eqne.<mode>"
+  [(set (reg:CC REG_CC)
+        (compare:CC
+         (plus:QISI (match_operand:QISI 3 "register_operand"  "0,0     ,0")
+                    (match_operand:QISI 1 "const_int_operand" "n,<p1m1>,n"))
+         (const_int 0)))
+   (set (match_operand:QISI 0 "register_operand"             "=d,*r    ,r")
+        (plus:QISI (match_operand:QISI 4 "register_operand"   "0,0     ,0")
+                   (match_dup 1)))
+   (clobber (match_scratch:QI 2                              "=X,X     ,&d"))]
+  "reload_completed"
+  {
+    return avr_out_plus_set_ZN (operands, nullptr);
+  }
+  [(set_attr "adjust_len" "add_set_ZN")])
+
+
+;; Swapping both comparison and branch condition.  This can turn difficult
+;; branches to easy ones.  And in some cases, a comparison against one can
+;; be turned into a comparison against zero.
+
+(define_peephole2 ; "*swapped_tst<mode>"
+  [(parallel [(set (reg:CC REG_CC)
+                   (compare:CC (match_operand:ALLs234 1 "register_operand")
+                               (match_operand:ALLs234 2 "const_operand")))
+              (clobber (match_operand:QI 3 "scratch_operand"))])
+   (set (pc)
+        (if_then_else (match_operator 0 "ordered_comparison_operator"
+                        [(reg:CC REG_CC)
+                         (const_int 0)])
+                      (label_ref (match_operand 4))
+                      (pc)))]
+  "peep2_regno_dead_p (2, REG_CC)"
+  [(set (reg:CC REG_CC)
+        (compare:CC (match_dup 2)
+                    (match_dup 1)))
+   ; "branch"
+   (set (pc)
+        (if_then_else (match_op_dup 0 [(reg:CC REG_CC)
+                                       (const_int 0)])
+                      (label_ref (match_dup 4))
+                      (pc)))]
+  {
+    rtx xval = avr_to_int_mode (operands[2]);
+    enum rtx_code code = GET_CODE (operands[0]);
+
+    if (code == GT && xval == const0_rtx)
+      code = LT;
+    else if (code == GE && xval == const1_rtx)
+      code = LT;
+    else if (code == LE && xval == const0_rtx)
+      code = GE;
+    else if (code == LT && xval == const1_rtx)
+      code = GE;
+    else
+      FAIL;
+
+    operands[2] = CONST0_RTX (<MODE>mode);
+    PUT_CODE (operands[0], code);
+  })
+
+;; Same, but for 8-bit modes which have no scratch reg.
+(define_peephole2 ; "*swapped_tst<mode>"
+  [(set (reg:CC REG_CC)
+        (compare:CC (match_operand:ALLs1 1 "register_operand")
+                    (match_operand:ALLs1 2 "const_operand")))
+   (set (pc)
+        (if_then_else (match_operator 0 "ordered_comparison_operator"
+                        [(reg:CC REG_CC)
+                         (const_int 0)])
+                      (label_ref (match_operand 4))
+                      (pc)))]
+  "peep2_regno_dead_p (2, REG_CC)"
+  [(set (reg:CC REG_CC)
+        (compare:CC (match_dup 2)
+                    (match_dup 1)))
+   ; "branch"
+   (set (pc)
+        (if_then_else (match_op_dup 0 [(reg:CC REG_CC)
+                                       (const_int 0)])
+                      (label_ref (match_dup 4))
+                      (pc)))]
+  {
+    rtx xval = avr_to_int_mode (operands[2]);
+    enum rtx_code code = GET_CODE (operands[0]);
+
+    if (code == GT && xval == const0_rtx)
+      code = LT;
+    else if (code == GE && xval == const1_rtx)
+      code = LT;
+    else if (code == LE && xval == const0_rtx)
+      code = GE;
+    else if (code == LT && xval == const1_rtx)
+      code = GE;
+    else
+      FAIL;
+
+    operands[2] = CONST0_RTX (<MODE>mode);
+    PUT_CODE (operands[0], code);
+  })
+
+
 (define_expand "extzv"
   [(set (match_operand:QI 0 "register_operand" "")
         (zero_extract:QI (match_operand:QI 1 "register_operand"  "")
--- a/src/gcc/config/avr/constraints.md
+++ b/src/gcc/config/avr/constraints.md
@@ -245,6 +245,11 @@ (define_constraint "Ym2"
 	    (match_test "INTVAL (avr_to_int_mode (op)) == -2"))
        (match_test "satisfies_constraint_Cm2 (op)")))
 
+;; Constraint that's the empty set.  Useful with mode and code iterators.
+(define_constraint "Yxx"
+  "A constraints that is always false"
+  (match_test "false"))
+
 (define_constraint "Yx2"
   "Fixed-point or integer constant not in the range @minus{}2 @dots{} 2"
   (and (ior (match_code "const_int")
--- a/src/gcc/config/avr/predicates.md
+++ b/src/gcc/config/avr/predicates.md
@@ -27,6 +27,11 @@ (define_predicate "d_register_operand"
   (and (match_code "reg")
        (match_test "REGNO (op) >= 16 && REGNO (op) <= 31")))
 
+(define_predicate "scratch_or_d_register_operand"
+  (ior (match_operand 0 "d_register_operand")
+       (and (match_code ("scratch"))
+            (match_operand 0 "scratch_operand"))))
+
 (define_predicate "even_register_operand"
   (and (match_code "reg")
        (and (match_test "REGNO (op) <= 31")
--- a/src/gcc/config/i386/cygwin.h
+++ b/src/gcc/config/i386/cygwin.h
@@ -57,7 +57,7 @@ along with GCC; see the file COPYING3.  If not see
 
 #undef ENDFILE_SPEC
 #define ENDFILE_SPEC \
-  "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s}\
+  "%{mdaz-ftz:crtfastmath.o%s;Ofast|ffast-math|funsafe-math-optimizations:%{!mno-daz-ftz:crtfastmath.o%s}} \
    %{!shared:%:if-exists(default-manifest.o%s)}\
    %{fvtable-verify=none:%s; \
     fvtable-verify=preinit:vtv_end.o%s; \
--- a/src/gcc/config/i386/darwin.h
+++ b/src/gcc/config/i386/darwin.h
@@ -109,8 +109,8 @@ along with GCC; see the file COPYING3.  If not see
 "%{!force_cpusubtype_ALL:-force_cpusubtype_ALL} "
 
 #undef ENDFILE_SPEC
-#define ENDFILE_SPEC \
-  "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
+#define ENDFILE_SPEC
+\  "%{mdaz-ftz:crtfastmath.o%s;Ofast|ffast-math|funsafe-math-optimizations:%{!mno-daz-ftz:crtfastmath.o%s}} \
    %{mpc32:crtprec32.o%s} \
    %{mpc64:crtprec64.o%s} \
    %{mpc80:crtprec80.o%s}" TM_DESTRUCTOR
--- a/src/gcc/config/i386/gnu-user-common.h
+++ b/src/gcc/config/i386/gnu-user-common.h
@@ -47,7 +47,7 @@ along with GCC; see the file COPYING3.  If not see
 
 /* Similar to standard GNU userspace, but adding -ffast-math support.  */
 #define GNU_USER_TARGET_MATHFILE_SPEC \
-  "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
+  "%{mdaz-ftz:crtfastmath.o%s;Ofast|ffast-math|funsafe-math-optimizations:%{!mno-daz-ftz:crtfastmath.o%s}} \
    %{mpc32:crtprec32.o%s} \
    %{mpc64:crtprec64.o%s} \
    %{mpc80:crtprec80.o%s}"
--- a/src/gcc/config/i386/i386.cc
+++ b/src/gcc/config/i386/i386.cc
@@ -18396,8 +18396,10 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi)
 	      tree itype = GET_MODE_INNER (TYPE_MODE (type)) == E_SFmode
 		? intSI_type_node : intDI_type_node;
 	      type = get_same_sized_vectype (itype, type);
-	      arg2 = gimple_build (&stmts, VIEW_CONVERT_EXPR, type, arg2);
 	    }
+	  else
+	    type = signed_type_for (type);
+	  arg2 = gimple_build (&stmts, VIEW_CONVERT_EXPR, type, arg2);
 	  tree zero_vec = build_zero_cst (type);
 	  tree cmp_type = truth_type_for (type);
 	  tree cmp = gimple_build (&stmts, LT_EXPR, cmp_type, arg2, zero_vec);
--- a/src/gcc/config/i386/i386.opt
+++ b/src/gcc/config/i386/i386.opt
@@ -420,6 +420,10 @@ mpc80
 Target RejectNegative
 Set 80387 floating-point precision to 80-bit.
 
+mdaz-ftz
+Target
+Set the FTZ and DAZ Flags.
+
 mpreferred-stack-boundary=
 Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg)
 Attempt to keep stack aligned to this power of 2.
--- a/src/gcc/config/i386/mingw32.h
+++ b/src/gcc/config/i386/mingw32.h
@@ -197,7 +197,7 @@ along with GCC; see the file COPYING3.  If not see
 
 #undef ENDFILE_SPEC
 #define ENDFILE_SPEC \
-  "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
+  "%{mdaz-ftz:crtfastmath.o%s;Ofast|ffast-math|funsafe-math-optimizations:%{!mno-daz-ftz:crtfastmath.o%s}} \
    %{!shared:%:if-exists(default-manifest.o%s)}\
    %{fvtable-verify=none:%s; \
     fvtable-verify=preinit:vtv_end.o%s; \
--- a/src/gcc/config/riscv/riscv.cc
+++ b/src/gcc/config/riscv/riscv.cc
@@ -5600,9 +5600,8 @@ riscv_asan_shadow_offset (void)
   /* We only have libsanitizer support for RV64 at present.
 
      This number must match kRiscv*_ShadowOffset* in the file
-     libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64,
-     even though 1<<36 makes more sense.  */
-  return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0;
+     libsanitizer/asan/asan_mapping.h.  */
+  return TARGET_64BIT ? HOST_WIDE_INT_UC (0xd55550000) : 0;
 }
 
 /* Initialize the GCC target structure.  */
--- a/src/gcc/config/rs6000/altivec.md
+++ b/src/gcc/config/rs6000/altivec.md
@@ -385,14 +385,22 @@ (define_split
 
 (define_insn_and_split "sldoi_to_mov<mode>"
   [(set (match_operand:VM 0 "altivec_register_operand")
-	(unspec:VM [(match_operand:VM 1 "easy_vector_constant")
+	(unspec:VM [(match_operand:VM 1 "const_vector_each_byte_same")
 	            (match_dup 1)
 		    (match_operand:QI 2 "u5bit_cint_operand")]
 		    UNSPEC_VSLDOI))]
-  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()"
+  "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()"
   "#"
   "&& 1"
-  [(set (match_dup 0) (match_dup 1))])
+  [(set (match_dup 0) (match_dup 1))]
+  "{
+     if (!easy_vector_constant (operands[1], <MODE>mode))
+       {
+	 rtx dest = gen_reg_rtx (<MODE>mode);
+	 emit_move_insn (dest, operands[1]);
+	 operands[1] = dest;
+       }
+  }")
 
 (define_insn "get_vrsave_internal"
   [(set (match_operand:SI 0 "register_operand" "=r")
--- a/src/gcc/config/rs6000/predicates.md
+++ b/src/gcc/config/rs6000/predicates.md
@@ -798,6 +798,43 @@ (define_predicate "easy_vector_constant_vsldoi"
 	    (and (match_test "easy_altivec_constant (op, mode)")
 		 (match_test "vspltis_shifted (op) != 0")))))
 
+;; Return true if this is a vector constant and each byte in
+;; it is the same.
+(define_predicate "const_vector_each_byte_same"
+  (match_code "const_vector")
+{
+  rtx elt;
+  if (!const_vec_duplicate_p (op, &elt))
+    return false;
+
+  machine_mode emode = GET_MODE_INNER (mode);
+  unsigned HOST_WIDE_INT eval;
+  if (CONST_INT_P (elt))
+    eval = INTVAL (elt);
+  else if (CONST_DOUBLE_AS_FLOAT_P (elt))
+    {
+      gcc_assert (emode == SFmode || emode == DFmode);
+      long l[2];
+      real_to_target (l, CONST_DOUBLE_REAL_VALUE (elt), emode);
+      /* real_to_target puts 32-bit pieces in each long.  */
+      eval = zext_hwi (l[0], 32);
+      eval |= zext_hwi (l[1], 32) << 32;
+    }
+  else
+    return false;
+
+  unsigned int esize = GET_MODE_SIZE (emode);
+  unsigned char byte0 = eval & 0xff;
+  for (unsigned int i = 1; i < esize; i++)
+    {
+      eval >>= BITS_PER_UNIT;
+      if (byte0 != (eval & 0xff))
+	return false;
+    }
+
+  return true;
+})
+
 ;; Return 1 if operand is a vector int register or is either a vector constant
 ;; of all 0 bits of a vector constant of all 1 bits.
 (define_predicate "vector_int_reg_or_same_bit"
--- a/src/gcc/config/rs6000/rs6000-builtins.def
+++ b/src/gcc/config/rs6000/rs6000-builtins.def
@@ -2796,6 +2796,19 @@
   const vsi __builtin_vsx_xxbrw_v4si (vsi);
     XXBRW_V4SI p9_xxbrw_v4si {}
 
+  const signed int __builtin_vsx_scalar_cmp_exp_qp_eq (_Float128, _Float128);
+    VSCEQPEQ xscmpexpqp_eq_kf {}
+
+  const signed int __builtin_vsx_scalar_cmp_exp_qp_gt (_Float128, _Float128);
+    VSCEQPGT xscmpexpqp_gt_kf {}
+
+  const signed int __builtin_vsx_scalar_cmp_exp_qp_lt (_Float128, _Float128);
+    VSCEQPLT xscmpexpqp_lt_kf {}
+
+  const signed int \
+      __builtin_vsx_scalar_cmp_exp_qp_unordered (_Float128, _Float128);
+    VSCEQPUO xscmpexpqp_unordered_kf {}
+
 
 ; Miscellaneous P9 functions
 [power9]
@@ -2878,19 +2891,6 @@
   fpmath _Float128 __builtin_mulf128_round_to_odd (_Float128, _Float128);
     MULF128_ODD mulkf3_odd {}
 
-  const signed int __builtin_vsx_scalar_cmp_exp_qp_eq (_Float128, _Float128);
-    VSCEQPEQ xscmpexpqp_eq_kf {}
-
-  const signed int __builtin_vsx_scalar_cmp_exp_qp_gt (_Float128, _Float128);
-    VSCEQPGT xscmpexpqp_gt_kf {}
-
-  const signed int __builtin_vsx_scalar_cmp_exp_qp_lt (_Float128, _Float128);
-    VSCEQPLT xscmpexpqp_lt_kf {}
-
-  const signed int \
-      __builtin_vsx_scalar_cmp_exp_qp_unordered (_Float128, _Float128);
-    VSCEQPUO xscmpexpqp_unordered_kf {}
-
   fpmath _Float128 __builtin_sqrtf128_round_to_odd (_Float128);
     SQRTF128_ODD sqrtkf2_odd {}
 
--- a/src/gcc/config/rs6000/rs6000.cc
+++ b/src/gcc/config/rs6000/rs6000.cc
@@ -8128,7 +8128,8 @@ darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
       type = TREE_TYPE (type);
   } while (AGGREGATE_TYPE_P (type));
 
-  if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
+  if (type != error_mark_node && ! AGGREGATE_TYPE_P (type)
+      && ! TYPE_PACKED (type) && maximum_field_alignment == 0)
     align = MAX (align, TYPE_ALIGN (type));
 
   return align;
@@ -28603,7 +28604,6 @@ vec_const_128bit_to_bytes (rtx op,
 
   info->all_words_same
     = (info->words[0] == info->words[1]
-       && info->words[0] == info->words[1]
        && info->words[0] == info->words[2]
        && info->words[0] == info->words[3]);
 
--- a/src/gcc/config/rs6000/vsx.md
+++ b/src/gcc/config/rs6000/vsx.md
@@ -2018,22 +2018,20 @@ (define_insn "*vsx_tsqrt<mode>2_internal"
   "x<VSv>tsqrt<sd>p %0,%x1"
   [(set_attr "type" "<VStype_simple>")])
 
-;; Fused vector multiply/add instructions. Support the classical Altivec
-;; versions of fma, which allows the target to be a separate register from the
-;; 3 inputs.  Under VSX, the target must be either the addend or the first
-;; multiply.
-
+;; Fused vector multiply/add instructions. Do not generate the Altivec versions
+;; of fma (vmaddfp and vnmsubfp).  These instructions allows the target to be a
+;; separate register from the 3 inputs, but they have different rounding
+;; behaviors than the VSX instructions.
 (define_insn "*vsx_fmav4sf4"
-  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
 	(fma:V4SF
-	  (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
-	  (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
-	  (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))]
+	  (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa")
+	  (match_operand:V4SF 2 "vsx_register_operand" "wa,0")
+	  (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))]
   "VECTOR_UNIT_VSX_P (V4SFmode)"
   "@
    xvmaddasp %x0,%x1,%x2
-   xvmaddmsp %x0,%x1,%x3
-   vmaddfp %0,%1,%2,%3"
+   xvmaddmsp %x0,%x1,%x3"
   [(set_attr "type" "vecfloat")])
 
 (define_insn "*vsx_fmav2df4"
@@ -2075,18 +2073,17 @@ (define_insn "*vsx_nfma<mode>4"
   [(set_attr "type" "<VStype_mul>")])
 
 (define_insn "*vsx_nfmsv4sf4"
-  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
 	(neg:V4SF
 	 (fma:V4SF
-	   (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
-	   (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
+	   (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa")
+	   (match_operand:V4SF 2 "vsx_register_operand" "wa,0")
 	   (neg:V4SF
-	     (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))))]
+	     (match_operand:V4SF 3 "vsx_register_operand" "0,wa")))))]
   "VECTOR_UNIT_VSX_P (V4SFmode)"
   "@
    xvnmsubasp %x0,%x1,%x2
-   xvnmsubmsp %x0,%x1,%x3
-   vnmsubfp %0,%1,%2,%3"
+   xvnmsubmsp %x0,%x1,%x3"
   [(set_attr "type" "vecfloat")])
 
 (define_insn "*vsx_nfmsv2df4"
--- a/src/gcc/cp/ChangeLog
+++ b/src/gcc/cp/ChangeLog
@@ -1,3 +1,44 @@
+2023-05-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/109868
+	* init.cc (build_zero_init_1): Don't initialize zero-width bitfields.
+	For unions only initialize the first FIELD_DECL.
+
+2023-05-15  Jason Merrill  <jason@redhat.com>
+
+	PR c++/109241
+	* pt.cc (find_parameter_packs_r): Handle null TREE_BINFO.
+
+2023-05-09  Patrick Palka  <ppalka@redhat.com>
+
+	Backported from master:
+	2023-04-01  Patrick Palka  <ppalka@redhat.com>
+
+	PR c++/109160
+	* cp-tree.h (do_auto_deduction): Add defaulted tmpl parameter.
+	* pt.cc (convert_template_argument): Pass 'in_decl' as 'tmpl' to
+	do_auto_deduction.
+	(tsubst_decl) <case VAR_/TYPE_DECL>: Pass 'tmpl' instead of 't' as
+	'in_decl' to coerce_template_parms.
+	(unify) <case TEMPLATE_PARM_INDEX>: Pass TPARMS_PRIMARY_TEMPLATE
+	as 'tmpl' to do_auto_deduction.
+	(do_auto_deduction): Document default arguments.  Rename local
+	variable 'tmpl' to 'ctmpl'.  Use 'tmpl' to obtain a full set of
+	template arguments for satisfaction in the adc_unify case.
+
+2023-05-09  Jason Merrill  <jason@redhat.com>
+
+	PR c++/106740
+	PR c++/105852
+	* decl.cc (duplicate_decls): Change non-templated friend
+	check to an assert.
+	* pt.cc	(tsubst_function_decl): Don't set DECL_TEMPLATE_INFO
+	on non-templated friends.
+	(tsubst_friend_function): Adjust.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
--- a/src/gcc/cp/cp-tree.h
+++ b/src/gcc/cp/cp-tree.h
@@ -7295,7 +7295,8 @@ extern tree do_auto_deduction                   (tree, tree, tree,
                                                  auto_deduction_context
 						 = adc_unspecified,
 						 tree = NULL_TREE,
-						 int = LOOKUP_NORMAL);
+						 int = LOOKUP_NORMAL,
+						 tree = NULL_TREE);
 extern tree type_uses_auto			(tree);
 extern tree type_uses_auto_or_concept		(tree);
 extern void append_type_to_template_for_access_check (tree, tree, tree,
--- a/src/gcc/cp/decl.cc
+++ b/src/gcc/cp/decl.cc
@@ -2666,10 +2666,11 @@ duplicate_decls (tree newdecl, tree olddecl, bool hiding, bool was_hidden)
 		  = TINFO_USED_TEMPLATE_ID (new_template_info);
 	    }
 
-	  if (non_templated_friend_p (olddecl))
-	    /* Don't copy tinfo from a non-templated friend (PR105761).  */;
-	  else
-	    DECL_TEMPLATE_INFO (newdecl) = DECL_TEMPLATE_INFO (olddecl);
+	  /* We don't want to copy template info from a non-templated friend
+	     (PR105761), but these shouldn't have DECL_TEMPLATE_INFO now.  */
+	  gcc_checking_assert (!DECL_TEMPLATE_INFO (olddecl)
+			       || !non_templated_friend_p (olddecl));
+	  DECL_TEMPLATE_INFO (newdecl) = DECL_TEMPLATE_INFO (olddecl);
 	}
 
       if (DECL_DECLARES_FUNCTION_P (newdecl))
--- a/src/gcc/cp/init.cc
+++ b/src/gcc/cp/init.cc
@@ -189,15 +189,21 @@ build_zero_init_1 (tree type, tree nelts, bool static_storage_p,
     init = build_zero_cst (type);
   else if (RECORD_OR_UNION_CODE_P (TREE_CODE (type)))
     {
-      tree field;
+      tree field, next;
       vec<constructor_elt, va_gc> *v = NULL;
 
       /* Iterate over the fields, building initializations.  */
-      for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
+      for (field = TYPE_FIELDS (type); field; field = next)
 	{
+	  next = DECL_CHAIN (field);
+
 	  if (TREE_CODE (field) != FIELD_DECL)
 	    continue;
 
+	  /* For unions, only the first field is initialized.  */
+	  if (TREE_CODE (type) == UNION_TYPE)
+	    next = NULL_TREE;
+
 	  if (TREE_TYPE (field) == error_mark_node)
 	    continue;
 
@@ -212,6 +218,11 @@ build_zero_init_1 (tree type, tree nelts, bool static_storage_p,
 		continue;
 	    }
 
+	  /* Don't add zero width bitfields.  */
+	  if (DECL_C_BIT_FIELD (field)
+	      && integer_zerop (DECL_SIZE (field)))
+	    continue;
+
 	  /* Note that for class types there will be FIELD_DECLs
 	     corresponding to base classes as well.  Thus, iterating
 	     over TYPE_FIELDs will result in correct initialization of
@@ -230,10 +241,6 @@ build_zero_init_1 (tree type, tree nelts, bool static_storage_p,
 	      if (value)
 		CONSTRUCTOR_APPEND_ELT(v, field, value);
 	    }
-
-	  /* For unions, only the first field is initialized.  */
-	  if (TREE_CODE (type) == UNION_TYPE)
-	    break;
 	}
 
       /* Build a constructor to contain the initializations.  */
--- a/src/gcc/cp/pt.cc
+++ b/src/gcc/cp/pt.cc
@@ -4106,10 +4106,14 @@ find_parameter_packs_r (tree *tp, int *walk_subtrees, void* data)
     case TAG_DEFN:
       t = TREE_TYPE (t);
       if (CLASS_TYPE_P (t))
-	/* Local class, need to look through the whole definition.  */
-	for (tree bb : BINFO_BASE_BINFOS (TYPE_BINFO (t)))
-	  cp_walk_tree (&BINFO_TYPE (bb), &find_parameter_packs_r,
-			ppd, ppd->visited);
+	{
+	  /* Local class, need to look through the whole definition.
+	     TYPE_BINFO might be unset for a partial instantiation.  */
+	  if (TYPE_BINFO (t))
+	    for (tree bb : BINFO_BASE_BINFOS (TYPE_BINFO (t)))
+	      cp_walk_tree (&BINFO_TYPE (bb), &find_parameter_packs_r,
+			    ppd, ppd->visited);
+	}
       else
 	/* Enum, look at the values.  */
 	for (tree l = TYPE_VALUES (t); l; l = TREE_CHAIN (l))
@@ -8636,7 +8640,7 @@ convert_template_argument (tree parm,
       else if (tree a = type_uses_auto (t))
 	{
 	  t = do_auto_deduction (t, arg, a, complain, adc_unify, args,
-				 LOOKUP_IMPLICIT);
+				 LOOKUP_IMPLICIT, /*tmpl=*/in_decl);
 	  if (t == error_mark_node)
 	    return error_mark_node;
 	}
@@ -11339,9 +11343,10 @@ tsubst_friend_function (tree decl, tree args)
       tree new_friend_template_info = DECL_TEMPLATE_INFO (new_friend);
       tree new_friend_result_template_info = NULL_TREE;
       bool new_friend_is_defn =
-	(DECL_INITIAL (DECL_TEMPLATE_RESULT
-		       (template_for_substitution (new_friend)))
-	 != NULL_TREE);
+	(new_friend_template_info
+	 && (DECL_INITIAL (DECL_TEMPLATE_RESULT
+			   (template_for_substitution (new_friend)))
+	     != NULL_TREE));
       tree not_tmpl = new_friend;
 
       if (TREE_CODE (new_friend) == TEMPLATE_DECL)
@@ -14175,6 +14180,10 @@ tsubst_function_decl (tree t, tree args, tsubst_flags_t complain,
 	  && !LAMBDA_FUNCTION_P (t))
 	return t;
 
+      /* A non-templated friend doesn't get DECL_TEMPLATE_INFO.  */
+      if (non_templated_friend_p (t))
+	goto friend_case;
+
       /* Calculate the most general template of which R is a
 	 specialization.  */
       gen_tmpl = most_general_template (DECL_TI_TEMPLATE (t));
@@ -14220,6 +14229,7 @@ tsubst_function_decl (tree t, tree args, tsubst_flags_t complain,
 	 tsubst_friend_function, and we want only to create a
 	 new decl (R) with appropriate types so that we can call
 	 determine_specialization.  */
+    friend_case:
       gen_tmpl = NULL_TREE;
       argvec = NULL_TREE;
     }
@@ -14415,7 +14425,7 @@ tsubst_function_decl (tree t, tree args, tsubst_flags_t complain,
       /* If this is an instantiation of a member template, clone it.
 	 If it isn't, that'll be handled by
 	 clone_constructors_and_destructors.  */
-      if (PRIMARY_TEMPLATE_P (gen_tmpl))
+      if (gen_tmpl && PRIMARY_TEMPLATE_P (gen_tmpl))
 	clone_cdtor (r, /*update_methods=*/false);
     }
   else if ((complain & tf_error) != 0
@@ -15022,7 +15032,7 @@ tsubst_decl (tree t, tree args, tsubst_flags_t complain)
 		if (argvec != error_mark_node)
 		  argvec = (coerce_innermost_template_parms
 			    (DECL_TEMPLATE_PARMS (gen_tmpl),
-			     argvec, t, complain,
+			     argvec, tmpl, complain,
 			     /*all*/true, /*defarg*/true));
 		if (argvec == error_mark_node)
 		  RETURN (error_mark_node);
@@ -24449,7 +24459,9 @@ unify (tree tparms, tree targs, tree parm, tree arg, int strict,
 	  if (tree a = type_uses_auto (tparm))
 	    {
 	      tparm = do_auto_deduction (tparm, arg, a,
-					 complain, adc_unify, targs);
+					 complain, adc_unify, targs,
+					 LOOKUP_NORMAL,
+					 TPARMS_PRIMARY_TEMPLATE (tparms));
 	      if (tparm == error_mark_node)
 		return 1;
 	    }
@@ -30334,13 +30346,20 @@ do_class_deduction (tree ptype, tree tmpl, tree init,
    adc_requirement contexts to communicate the necessary template arguments
    to satisfaction.  OUTER_TARGS is ignored in other contexts.
 
-   For partial-concept-ids, extra args may be appended to the list of deduced
-   template arguments prior to determining constraint satisfaction.  */
+   Additionally for adc_unify contexts TMPL is the template for which TYPE
+   is a template parameter type.
+
+   For partial-concept-ids, extra args from OUTER_TARGS, TMPL and the current
+   scope may be appended to the list of deduced template arguments prior to
+   determining constraint satisfaction as appropriate.  */
 
 tree
 do_auto_deduction (tree type, tree init, tree auto_node,
-                   tsubst_flags_t complain, auto_deduction_context context,
-		   tree outer_targs, int flags)
+		   tsubst_flags_t complain /* = tf_warning_or_error */,
+		   auto_deduction_context context /* = adc_unspecified */,
+		   tree outer_targs /* = NULL_TREE */,
+		   int flags /* = LOOKUP_NORMAL */,
+		   tree tmpl /* = NULL_TREE */)
 {
   if (init == error_mark_node)
     return error_mark_node;
@@ -30359,9 +30378,9 @@ do_auto_deduction (tree type, tree init, tree auto_node,
      auto_node.  */
   complain &= ~tf_partial;
 
-  if (tree tmpl = CLASS_PLACEHOLDER_TEMPLATE (auto_node))
+  if (tree ctmpl = CLASS_PLACEHOLDER_TEMPLATE (auto_node))
     /* C++17 class template argument deduction.  */
-    return do_class_deduction (type, tmpl, init, flags, complain);
+    return do_class_deduction (type, ctmpl, init, flags, complain);
 
   if (init == NULL_TREE || TREE_TYPE (init) == NULL_TREE)
     /* Nothing we can do with this, even in deduction context.  */
@@ -30521,7 +30540,10 @@ do_auto_deduction (tree type, tree init, tree auto_node,
 		}
 	    }
 
-      tree full_targs = add_to_template_args (outer_targs, targs);
+      tree full_targs = outer_targs;
+      if (context == adc_unify && tmpl)
+	full_targs = add_outermost_template_args (tmpl, full_targs);
+      full_targs = add_to_template_args (full_targs, targs);
 
       /* HACK: Compensate for callers not always communicating all levels of
 	 outer template arguments by filling in the outermost missing levels
--- a/src/gcc/d/ChangeLog
+++ b/src/gcc/d/ChangeLog
@@ -1,3 +1,8 @@
+2023-06-06  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	* dmd/MERGE: Merge upstream dmd 316b89f1e3.
+	* dmd/VERSION: Bump version to v2.100.2.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
--- a/src/gcc/d/dmd/MERGE
+++ b/src/gcc/d/dmd/MERGE
@@ -1,4 +1,4 @@
-76e3b41375e3e1cb4dbca692b587d8e916c0b49f
+316b89f1e3dffcad488c26f56f58c8adfcb84b26
 
 The first line of this file holds the git revision number of the last
 merge done from the dlang/dmd repository.
--- a/src/gcc/d/dmd/VERSION
+++ b/src/gcc/d/dmd/VERSION
@@ -1 +1 @@
-v2.100.1
+v2.100.2
--- a/src/gcc/fortran/ChangeLog
+++ b/src/gcc/fortran/ChangeLog
@@ -1,3 +1,33 @@
+2023-06-09  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-06-09  Jakub Jelinek  <jakub@redhat.com>
+
+	PR fortran/96024
+	* primary.cc (gfc_convert_to_structure_constructor): Only do
+	constant string ctor length verification and truncation/padding
+	if constant length has INTEGER type.
+
+2023-06-04  Steve Kargl  <kargl@gcc.gnu.org>
+
+	Backported from master:
+	2023-06-02  Steve Kargl  <kargl@gcc.gnu.org>
+
+	PR fortran/100607
+	* resolve.cc (resolve_select_rank): Remove duplicate error.
+	(resolve_fl_var_and_proc): Prevent NULL pointer dereference and
+	suppress error message for temporary.
+
+2023-05-20  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2023-05-15  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/109846
+	* expr.cc (gfc_check_vardef_context): Check appropriate pointer
+	attribute for CLASS vs. non-CLASS function result in variable
+	definition context.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
--- a/src/gcc/fortran/expr.cc
+++ b/src/gcc/fortran/expr.cc
@@ -6254,7 +6254,7 @@ gfc_check_vardef_context (gfc_expr* e, bool pointer, bool alloc_obj,
       && !(sym->attr.flavor == FL_PROCEDURE && sym == sym->result)
       && !(sym->attr.flavor == FL_PROCEDURE && sym->attr.proc_pointer)
       && !(sym->attr.flavor == FL_PROCEDURE
-	   && sym->attr.function && sym->attr.pointer))
+	   && sym->attr.function && attr.pointer))
     {
       if (context)
 	gfc_error ("%qs in variable definition context (%s) at %L is not"
--- a/src/gcc/fortran/primary.cc
+++ b/src/gcc/fortran/primary.cc
@@ -3196,10 +3196,11 @@ gfc_convert_to_structure_constructor (gfc_expr *e, gfc_symbol *sym, gfc_expr **c
 	goto cleanup;
 
       /* For a constant string constructor, make sure the length is
-	 correct; truncate of fill with blanks if needed.  */
+	 correct; truncate or fill with blanks if needed.  */
       if (this_comp->ts.type == BT_CHARACTER && !this_comp->attr.allocatable
 	  && this_comp->ts.u.cl && this_comp->ts.u.cl->length
 	  && this_comp->ts.u.cl->length->expr_type == EXPR_CONSTANT
+	  && this_comp->ts.u.cl->length->ts.type == BT_INTEGER
 	  && actual->expr->ts.type == BT_CHARACTER
 	  && actual->expr->expr_type == EXPR_CONSTANT)
 	{
--- a/src/gcc/fortran/resolve.cc
+++ b/src/gcc/fortran/resolve.cc
@@ -9923,11 +9923,6 @@ resolve_select_rank (gfc_code *code, gfc_namespace *old_ns)
 			       || gfc_expr_attr (code->expr1).pointer))
 	gfc_error ("RANK (*) at %L cannot be used with the pointer or "
 		   "allocatable selector at %L", &c->where, &code->expr1->where);
-
-      if (case_value == -1 && (gfc_expr_attr (code->expr1).allocatable
-			       || gfc_expr_attr (code->expr1).pointer))
-	gfc_error ("RANK (*) at %L cannot be used with the pointer or "
-		   "allocatable selector at %L", &c->where, &code->expr1->where);
     }
 
   /* Add EXEC_SELECT to switch on rank.  */
@@ -12913,7 +12908,10 @@ resolve_fl_var_and_proc (gfc_symbol *sym, int mp_flag)
 
       if (allocatable)
 	{
-	  if (dimension && as->type != AS_ASSUMED_RANK)
+	  if (dimension
+	      && as
+	      && as->type != AS_ASSUMED_RANK
+	      && !sym->attr.select_rank_temporary)
 	    {
 	      gfc_error ("Allocatable array %qs at %L must have a deferred "
 			 "shape or assumed rank", sym->name, &sym->declared_at);
--- a/src/gcc/match.pd
+++ b/src/gcc/match.pd
@@ -1723,7 +1723,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
 /* (x | CST1) & CST2 -> (x & CST2) | (CST1 & CST2) */
 (simplify
   (bit_and (bit_ior @0 CONSTANT_CLASS_P@1) CONSTANT_CLASS_P@2)
-  (bit_ior (bit_and @0 @2) (bit_and @1 @2)))
+  (bit_ior (bit_and @0 @2) (bit_and! @1 @2)))
 
 /* Combine successive equal operations with constants.  */
 (for bitop (bit_and bit_ior bit_xor)
@@ -1732,7 +1732,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
   (if (!CONSTANT_CLASS_P (@0))
    /* This is the canonical form regardless of whether (bitop @1 @2) can be
       folded to a constant.  */
-   (bitop @0 (bitop @1 @2))
+   (bitop @0 (bitop! @1 @2))
    /* In this case we have three constants and (bitop @0 @1) doesn't fold
       to a constant.  This can happen if @0 or @1 is a POLY_INT_CST and if
       the values involved are such that the operation can't be decided at
@@ -2635,13 +2635,13 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
 	 forever if something doesn't simplify into a constant.  */
       (if (!CONSTANT_CLASS_P (@0))
        (if (outer_op == PLUS_EXPR)
-	(plus (view_convert @0) (inner_op @2 (view_convert @1)))
-	(minus (view_convert @0) (neg_inner_op @2 (view_convert @1)))))
+	(plus (view_convert @0) (inner_op! @2 (view_convert @1)))
+	(minus (view_convert @0) (neg_inner_op! @2 (view_convert @1)))))
       (if (!ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0))
 	   || TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0)))
        (if (outer_op == PLUS_EXPR)
-	(view_convert (plus @0 (inner_op (view_convert @2) @1)))
-	(view_convert (minus @0 (neg_inner_op (view_convert @2) @1))))
+	(view_convert (plus @0 (inner_op! (view_convert @2) @1)))
+	(view_convert (minus @0 (neg_inner_op! (view_convert @2) @1))))
        /* If the constant operation overflows we cannot do the transform
 	  directly as we would introduce undefined overflow, for example
 	  with (a - 1) + INT_MIN.  */
@@ -2672,10 +2672,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
      /* If all 3 captures are CONSTANT_CLASS_P, punt, as we might recurse
 	forever if something doesn't simplify into a constant.  */
      (if (!CONSTANT_CLASS_P (@0))
-      (minus (outer_op (view_convert @1) @2) (view_convert @0)))
+      (minus (outer_op! (view_convert @1) @2) (view_convert @0)))
      (if (!ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0))
 	  || TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0)))
-      (view_convert (minus (outer_op @1 (view_convert @2)) @0))
+      (view_convert (minus (outer_op! @1 (view_convert @2)) @0))
       (if (types_match (type, @0))
        (with { tree cst = const_binop (outer_op, type, @1, @2); }
 	(if (cst && !TREE_OVERFLOW (cst))
@@ -2691,10 +2691,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
     /* If all 3 captures are CONSTANT_CLASS_P, punt, as we might recurse
       forever if something doesn't simplify into a constant.  */
     (if (!CONSTANT_CLASS_P (@0))
-     (plus (view_convert @0) (minus @1 (view_convert @2))))
+     (plus (view_convert @0) (minus! @1 (view_convert @2))))
     (if (!ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0))
 	 || TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0)))
-     (view_convert (plus @0 (minus (view_convert @1) @2)))
+     (view_convert (plus @0 (minus! (view_convert @1) @2)))
      (if (types_match (type, @0))
       (with { tree cst = const_binop (MINUS_EXPR, type, @1, @2); }
        (if (cst && !TREE_OVERFLOW (cst))
--- a/src/gcc/testsuite/ChangeLog
+++ b/src/gcc/testsuite/ChangeLog
@@ -1,3 +1,4216 @@
+2023-06-10  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/109650
+	Backport from 2023-05-10 master r14-1688.
+	* gcc.target/avr/torture/pr109650-1.c: New test.
+	* gcc.target/avr/torture/pr109650-2.c: New test.
+
+2023-06-09  Iain Sandoe  <iain@sandoe.co.uk>
+
+	Backported from master:
+	2023-06-02  Iain Sandoe  <iain@sandoe.co.uk>
+
+	PR target/110044
+	* gcc.target/powerpc/darwin-abi-13-0.c: New test.
+	* gcc.target/powerpc/darwin-abi-13-1.c: New test.
+	* gcc.target/powerpc/darwin-abi-13-2.c: New test.
+	* gcc.target/powerpc/darwin-structs-0.h: New test.
+
+2023-06-09  liuhongt  <hongtao.liu@intel.com>
+
+	* gcc.target/i386/pr110108-2.c: New test.
+
+2023-06-08  Alex Coplan  <alex.coplan@arm.com>
+
+	Backported from master:
+	2023-05-25  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/109800
+	* gcc.target/arm/pure-code/pr109800.c: New test.
+
+2023-06-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Backported from master:
+	2023-05-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/109939
+	* gcc.target/arm/pr109939.c: New test.
+
+2023-06-04  Steve Kargl  <kargl@gcc.gnu.org>
+
+	Backported from master:
+	2023-06-02  Steve Kargl  <kargl@gcc.gnu.org>
+
+	PR fortran/100607
+	* gfortran.dg/select_rank_6.f90: New test.
+
+2023-05-30  Christophe Lyon  <christophe.lyon@linaro.org>
+
+	Backported from master:
+	2023-05-30  Christophe Lyon  <christophe.lyon@linaro.org>
+
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c:
+	Support both definitions of int32_t.
+
+2023-05-25  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/82931
+	* gcc.target/avr/pr82931.c: New test.
+
+2023-05-22   Michael Meissner  <meissner@linux.ibm.com>
+
+	PR target/70243
+	* gcc.target/powerpc/pr70243.c: New test.  Back port from master
+	04/10/2023 change.
+
+2023-05-22  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-21  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/109505
+	* gcc.target/aarch64/sve/pr109505.c: New test.
+
+2023-05-20  Harald Anlauf  <anlauf@gmx.de>
+
+	Backported from master:
+	2023-05-15  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/109846
+	* gfortran.dg/ptr-func-5.f90: New test.
+
+2023-05-20  Triffid Hunter  <triffid.hunter@gmail.com>
+
+	PR target/105753
+	Backport from 2023-05-20 https://gcc.gnu.org/r14-1016
+	* gcc.target/avr/torture/pr105753.c: New test.
+
+2023-05-19  Patrick Palka  <ppalka@redhat.com>
+
+	Backported from master:
+	2023-05-15  Patrick Palka  <ppalka@redhat.com>
+
+	* g++.dg/cpp23/feat-cxx2b.C: Test __cpp_auto_cast.
+
+2023-05-18  Alexandre Oliva  <oliva@adacore.com>
+
+	* gcc.target/arm/acle/cde-mve-full-assembly.c: Drop blank
+	after tab after vmsr, and lower the case of P0.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/srshr.c: Update shift value.
+	* gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value.
+	* gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value.
+	* gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value.
+	* gcc.target/arm/mve/intrinsics/urshr.c: Update shift value.
+	* gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value.
+	* gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx.
+	* gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx.
+	* gcc.target/arm/mve/mve_const_shifts.c: New test.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/109697
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: XFAIL check.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: XFAIL check.
+	* gcc.target/arm/mve/pr108177-1.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-10.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-11.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-12.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-13.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-13-run.c: use mve_fp
+	* gcc.target/arm/mve/pr108177-14.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-14-run.c: use mve_fp
+	* gcc.target/arm/mve/pr108177-2.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-3.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-4.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-5.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-6.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-7.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-8.c: Relax registers.
+	* gcc.target/arm/mve/pr108177-9.c: Relax registers.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vaddq_m.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vaddq_n.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c: Removed.
+	* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c: Removed.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c: Removed.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: Add testcases.
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Add testcases.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c: New.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/asrl.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/lsll.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/sqrshr.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/sqshl.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/sqshll.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/srshr.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/srshrl.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/uqrshl.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/uqrshll_sat48.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/uqshl.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/uqshll.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/urshr.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/urshrl.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadciq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadciq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadcq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vadcq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vandq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbicq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp16q.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp16q_m.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp32q_m.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp64q_m.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vctp8q_m.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/veorq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmsq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmsq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovnbq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmovntq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vornq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vorrq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpnot.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vpselq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovntq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshlq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshlq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_r_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_r_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_r_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_r_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_r_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_r_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsliq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsriq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vld1q_f16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld4q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst2q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vst4q_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-04-06  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: Remove unused variables.
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Remove unused variables.
+
+2023-05-18  Murray Steele  <murray.steele@arm.com>
+
+	Backported from master:
+	2023-01-18  Murray Steele  <murray.steele@arm.com>
+
+	* gcc.target/arm/mve/general/preserve_user_namespace_1.c: New test.
+
+2023-05-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	Backported from master:
+	2023-01-24  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	* gcc.target/arm/mve/pr108177-1-run.c: New test.
+	* gcc.target/arm/mve/pr108177-1.c: New test.
+	* gcc.target/arm/mve/pr108177-10-run.c: New test.
+	* gcc.target/arm/mve/pr108177-10.c: New test.
+	* gcc.target/arm/mve/pr108177-11-run.c: New test.
+	* gcc.target/arm/mve/pr108177-11.c: New test.
+	* gcc.target/arm/mve/pr108177-12-run.c: New test.
+	* gcc.target/arm/mve/pr108177-12.c: New test.
+	* gcc.target/arm/mve/pr108177-13-run.c: New test.
+	* gcc.target/arm/mve/pr108177-13.c: New test.
+	* gcc.target/arm/mve/pr108177-14-run.c: New test.
+	* gcc.target/arm/mve/pr108177-14.c: New test.
+	* gcc.target/arm/mve/pr108177-2-run.c: New test.
+	* gcc.target/arm/mve/pr108177-2.c: New test.
+	* gcc.target/arm/mve/pr108177-3-run.c: New test.
+	* gcc.target/arm/mve/pr108177-3.c: New test.
+	* gcc.target/arm/mve/pr108177-4-run.c: New test.
+	* gcc.target/arm/mve/pr108177-4.c: New test.
+	* gcc.target/arm/mve/pr108177-5-run.c: New test.
+	* gcc.target/arm/mve/pr108177-5.c: New test.
+	* gcc.target/arm/mve/pr108177-6-run.c: New test.
+	* gcc.target/arm/mve/pr108177-6.c: New test.
+	* gcc.target/arm/mve/pr108177-7-run.c: New test.
+	* gcc.target/arm/mve/pr108177-7.c: New test.
+	* gcc.target/arm/mve/pr108177-8-run.c: New test.
+	* gcc.target/arm/mve/pr108177-8.c: New test.
+	* gcc.target/arm/mve/pr108177-9-run.c: New test.
+	* gcc.target/arm/mve/pr108177-9.c: New test.
+	* gcc.target/arm/mve/pr108177-main.x: New test include.
+	* gcc.target/arm/mve/pr108177.x: New test include.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-04-04  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Tighten test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Tighten test.
+
+2023-05-18  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	Backported from master:
+	2023-01-16  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+	PR target/96795
+	PR target/107515
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c: New test.
+	* gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: New test.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c: Add missing extern
+	"C".
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vld2q_f16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vld2q_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld2q_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld2q_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld2q_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld2q_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld2q_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vld2q_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqnegq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqnegq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqnegq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqabsq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqabsq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqabsq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vcmulq_f16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vcmulq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vcmlaq_f16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vnegq_f16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vnegq_x_s8.c: Likewise.
+	* gcc.target/arm/simd/mve-vneg.c: Update test.
+	* gcc.target/arm/simd/mve-vshr.c: Likewise
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vclzq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks.  Use
+	extern "C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vclzq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclzq_x_u8.c: Likewise.
+	* gcc.target/arm/simd/mve-vclz.c: Update test.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2023-01-25  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vclsq_m_s16.c: Use
+	check-function-bodies instead of scan-assembler checks. Use extern
+	"C" for C++ testing.
+	* gcc.target/arm/mve/intrinsics/vclsq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vclsq_x_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-12-08  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: Extern functions
+	as "C".
+	* gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise.
+
+2023-05-18  Christophe Lyon  <christophe.lyon@arm.com>
+
+	Backported from master:
+	2022-09-30  Christophe Lyon  <christophe.lyon@arm.com>
+
+	* gcc.target/arm/mve/mve_load_memory_modes.c: Update expected
+	registers.
+	* gcc.target/arm/mve/mve_store_memory_modes.c: Likewise.
+
+2023-05-18  Christophe Lyon  <christophe.lyon@arm.com>
+
+	Backported from master:
+	2022-10-03  Christophe Lyon  <christophe.lyon@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c: New test.
+
+2023-05-18  Christophe Lyon  <christophe.lyon@arm.com>
+
+	Backported from master:
+	2022-12-01  Christophe Lyon  <christophe.lyon@arm.com>
+
+	* gcc.target/arm/simd/mve-compare-1.c: Update.
+	* gcc.target/arm/simd/mve-compare-scalar-1.c: Update.
+	* gcc.target/arm/simd/mve-vabs.c: Update.
+	* gcc.target/arm/simd/mve-vadd-1.c: Update.
+	* gcc.target/arm/simd/mve-vadd-scalar-1.c: Update.
+	* gcc.target/arm/simd/mve-vcmp.c: Update.
+	* gcc.target/arm/simd/pr101325.c: Update.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Improve tests.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_s16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_s32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_s8.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_u16.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_u32.c:
+	* gcc.target/arm/mve/intrinsics/vqsubq_u8.c:
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c:
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c:
+	* gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c:
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Improve tests.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqaddq_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Improve tests.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Improve tests.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c: Improve tests.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vsubq_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmulq_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvaq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vabsq_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vabdq_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Improve tests.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c : Improve test.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c : Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_n_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c : Likewise.
+	* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c : Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c:
+	Update test.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c:
+	Likewise.
+	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c:
+	Likewise.
+
+2023-05-18  Andrea Corallo  <andrea.corallo@arm.com>
+
+	Backported from master:
+	2022-11-28  Andrea Corallo  <andrea.corallo@arm.com>
+
+	* gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Improve test.
+	* gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise.
+
+2023-05-17  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-17  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/109868
+	* g++.dg/init/pr109868.C: New test.
+
+2023-05-15  Jason Merrill  <jason@redhat.com>
+
+	PR c++/109241
+	* g++.dg/cpp1y/lambda-generic-local-class2.C: New test.
+
+2023-05-15  Richard Biener  <rguenther@suse.de>
+
+	PR testsuite/108776
+	* c-c++-common/rotate-11.c: Add --param logical-op-non-short-circuit=1.
+
+2023-05-15  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2023-05-15  Richard Biener  <rguenther@suse.de>
+
+	* gcc.dg/vect/pr108950.c: Re-order dg-require-effective-target
+	and dg-do.
+
+2023-05-10  Richard Biener  <rguenther@suse.de>
+
+	Backported from master:
+	2023-05-10  Richard Biener  <rguenther@suse.de>
+
+	* g++.dg/torture/pr106922.C: Force _GLIBCXX_USE_CXX11_ABI to 1.
+
+2023-05-09  Patrick Palka  <ppalka@redhat.com>
+
+	Backported from master:
+	2023-04-01  Patrick Palka  <ppalka@redhat.com>
+
+	PR c++/109160
+	* g++.dg/cpp2a/concepts-placeholder12.C: New test.
+
+2023-05-09  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-09  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/109778
+	* gcc.dg/lto/pr109778_0.c: New test.
+	* gcc.dg/lto/pr109778_1.c: New file.
+
+2023-05-09  Jakub Jelinek  <jakub@redhat.com>
+
+	Backported from master:
+	2023-05-09  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/109778
+	* gcc.c-torture/execute/pr109778.c: New test.
+
+2023-05-09  Martin Uecker  <uecker@tugraz.at>
+
+	Backported from master:
+	2023-02-18  Martin Uecker  <uecker@tugraz.at>
+
+	PR c/105660
+	PR c/105660
+	* gcc.dg/pr105660-1.c: New test.
+	* gcc.dg/pr105660-2.c: New test.
+
+2023-05-09  Kewen Lin  <linkw@linux.ibm.com>
+
+	Backported from master:
+	2023-04-26  Kewen Lin  <linkw@linux.ibm.com>
+
+	PR target/109069
+	* gcc.target/powerpc/pr109069-1.c: New test.
+	* gcc.target/powerpc/pr109069-2-run.c: New test.
+	* gcc.target/powerpc/pr109069-2.c: New test.
+	* gcc.target/powerpc/pr109069-2.h: New test.
+
+2023-05-09  Jason Merrill  <jason@redhat.com>
+
+	PR c++/106740
+	PR c++/105852
+	* g++.dg/template/friend78.C: New test.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
--- a/src/gcc/testsuite/c-c++-common/rotate-11.c
+++ b/src/gcc/testsuite/c-c++-common/rotate-11.c
@@ -1,6 +1,6 @@
 /* PR tree-optimization/108440 */
 /* { dg-do compile { target { { ilp32 || lp64 } || llp64 } } } */
-/* { dg-options "-O2 -fdump-tree-optimized" } */
+/* { dg-options "-O2 -fdump-tree-optimized --param logical-op-non-short-circuit=1" } */
 /* { dg-final { scan-tree-dump-times " r<< " 5 "optimized" } } */
 /* { dg-final { scan-tree-dump-times " \\\& 7;" 4 "optimized" } } */
 
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/g++.dg/cpp1y/lambda-generic-local-class2.C
@@ -0,0 +1,13 @@
+// PR c++/109241
+// { dg-do compile { target c++14 } }
+// { dg-options "" } no pedantic
+
+void g() {
+  [](auto) {
+    [](auto) {
+      ({
+        struct A {};
+      });
+    };
+  }(1);
+}
--- a/src/gcc/testsuite/g++.dg/cpp23/feat-cxx2b.C
+++ b/src/gcc/testsuite/g++.dg/cpp23/feat-cxx2b.C
@@ -557,3 +557,9 @@
 #elif __cpp_multidimensional_subscript != 202110
 #  error "__cpp_multidimensional_subscript != 202110"
 #endif
+
+#ifndef __cpp_auto_cast
+#  error "__cpp_auto_cast"
+#elif __cpp_auto_cast != 202110
+#  error "__cpp_auto_cast != 202110"
+#endif
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/g++.dg/cpp2a/concepts-placeholder12.C
@@ -0,0 +1,29 @@
+// PR c++/109160
+// { dg-do compile { target c++20 } }
+
+template<class T, bool B>
+concept C = B;
+
+template<int> struct X { };
+
+template<bool B>
+struct A {
+  template<C<B> auto V> static void f();
+  template<C<B> auto V> static void g(X<V>);
+  template<C<B> auto V> static inline int value;
+  template<C<B> auto V> struct D { };
+};
+
+int main() {
+  A<true>::f<0>();
+  A<false>::f<0>(); // { dg-error "no match|constraints" }
+
+  A<true>::g(X<0>{});
+  A<false>::g(X<0>{}); // { dg-error "no match|constraints" }
+
+  bool v1 = A<true>::value<0>;
+  bool v2 = A<false>::value<0>;  // { dg-error "constraints" }
+
+  A<true>::D<0> d1;
+  A<false>::D<0> d2; // { dg-error "constraints" }
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/g++.dg/init/pr109868.C
@@ -0,0 +1,13 @@
+// PR c++/109868
+// { dg-do compile }
+// { dg-options "-O2" }
+
+struct A { virtual void foo (); };
+struct B { long b; int : 0; };
+struct C : A { B c; };
+
+void
+bar (C *p)
+{
+  *p = C ();
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/g++.dg/template/friend78.C
@@ -0,0 +1,18 @@
+// PR c++/106740
+// { dg-additional-options -Wno-non-template-friend }
+
+template <typename> struct EnumClass { friend int toString(EnumClass); };
+struct AmhsConvInfoCoFw {
+  enum AftnTypeXMsgTypeEnum {};
+  typedef EnumClass<AftnTypeXMsgTypeEnum> AftnTypeXMsgType;
+  const int getAftnTypeXMsgTypeAsStr() const;
+  struct MtcuAxgwInfo {
+    AftnTypeXMsgType mAftnTypeXMsgType;
+  };
+};
+const int AmhsConvInfoCoFw::getAftnTypeXMsgTypeAsStr() const {
+  MtcuAxgwInfo __trans_tmp_1;
+  toString(__trans_tmp_1.mAftnTypeXMsgType);
+  return 0;
+}
+int toString(AmhsConvInfoCoFw::AftnTypeXMsgType);
--- a/src/gcc/testsuite/g++.dg/torture/pr106922.C
+++ b/src/gcc/testsuite/g++.dg/torture/pr106922.C
@@ -4,8 +4,16 @@
 // -O1 doesn't iterate VN and thus has bogus uninit diagnostics
 // { dg-skip-if "" { *-*-* } { "-O1" } { "" } }
 
+// The testcase still emits bogus diagnostics with the pre-C++11 ABI
+#undef _GLIBCXX_USE_CXX11_ABI
+#define _GLIBCXX_USE_CXX11_ABI 1
+
 #include <vector>
 
+// When the library is not dual-ABI and defaults to old just compile
+// an empty TU
+#if _GLIBCXX_USE_CXX11_ABI
+
 #include <optional>
 template <class T>
 using Optional = std::optional<T>;
@@ -46,3 +54,4 @@ void test()
         externals.external2 = internal2;
     }
 }
+#endif
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr109778.c
@@ -0,0 +1,26 @@
+/* PR tree-optimization/109778 */
+
+int a, b, c, d, *e = &c;
+
+static inline unsigned
+foo (unsigned char x)
+{
+  x = 1 | x << 1;
+  x = x >> 4 | x << 4;
+  return x;
+}
+
+static inline void
+bar (unsigned x)
+{
+  *e = 8 > foo (x + 86) - 86;
+}
+
+int
+main ()
+{
+  d = a && b;
+  bar (d + 4);
+  if (c != 1)
+    __builtin_abort ();
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.dg/lto/pr109778_0.c
@@ -0,0 +1,22 @@
+/* PR tree-optimization/109778 */
+/* { dg-lto-do run } */
+/* { dg-lto-options { "-O2 -flto" } } */
+/* { dg-require-effective-target int32 } */
+
+int bar (int);
+
+__attribute__((noipa)) int
+foo (int x)
+{
+  x = bar (x);
+  x = (x << 16) | (int) ((unsigned) x >> 16);
+  return x & 0x10000000;
+}
+
+int
+main ()
+{
+  if (foo (0) || foo (-1))
+    __builtin_abort ();
+  return 0;
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.dg/lto/pr109778_1.c
@@ -0,0 +1,7 @@
+int
+bar (int x)
+{
+  x &= 0x22222222;
+  x |= (int) 0xf1234567U;
+  return x;
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.dg/pr105660-1.c
@@ -0,0 +1,13 @@
+/* PR105660
+ * { dg-do compile }
+ * { dg-options "-std=c17" }
+ */
+
+void gatherConservativeVars(int, int, int, int, int, int, int Hnvar, int,
+                            int Hnyt, int Hnxyt, int, int Hstep, double[Hnyt],
+                            double[Hnvar][Hstep][Hnxyt]);
+void gatherConservativeVars(int, int, int, int, int, int, int Hnvar, int, int Hnyt,
+                            int Hnxyt, int, int Hstep, double[Hnyt],
+                            double[Hnvar][Hstep][Hnxyt]);
+
+
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.dg/pr105660-2.c
@@ -0,0 +1,12 @@
+/* PR105660
+ * { dg-do compile }
+ * { dg-options "-Wall -std=c17" }
+ */
+
+
+struct bat_gen_conf_s;
+void batch_generator_create2(struct bat_gen_conf_s* config, int D, int N, const long bat_dims[D][N], const long tot_dims[D][N], const long tot_strs[D][N], const _Complex float* data[D]);
+void batch_generator_create2(struct bat_gen_conf_s* config, int D, int N, const long bat_dims[D][N], const long tot_dims[D][N], const long tot_strs[D][N], const _Complex float* data[D]);
+
+
+
--- a/src/gcc/testsuite/gcc.dg/vect/pr108950.c
+++ b/src/gcc/testsuite/gcc.dg/vect/pr108950.c
@@ -1,5 +1,5 @@
-/* { dg-require-effective-target vect_simd_clones } */
 /* { dg-do compile } */
+/* { dg-require-effective-target vect_simd_clones } */
 
 int m;
 short int n;
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/aarch64/sve/pr109505.c
@@ -0,0 +1,12 @@
+/* PR tree-optimization/109505 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.2-a+sve" } */
+
+#pragma GCC aarch64 "arm_sve.h"
+
+unsigned long
+foo (unsigned long x)
+{
+  unsigned long y = svcntb ();
+  return (x | 15) & y;
+}
--- a/src/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c
+++ b/src/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c
@@ -567,80 +567,80 @@
    contain back references).  */
 /*
 ** test_cde_vcx1q_mfloat16x8_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_mfloat32x4_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_muint8x16_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_muint16x8_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_muint32x4_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_muint64x2_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_mint8x16_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_mint16x8_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_mint32x4_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1q_mint64x2_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1t	p0, q0, #32
 ** 	bx	lr
@@ -649,80 +649,80 @@
 
 /*
 ** test_cde_vcx1qa_mfloat16x8_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_mfloat32x4_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_muint8x16_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_muint16x8_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_muint32x4_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_muint64x2_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_mint8x16_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_mint16x8_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_mint32x4_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
 */
 /*
 ** test_cde_vcx1qa_mint64x2_tintint:
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
-** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	 P0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
+** 	(?:vldr\.64	d0, \.L[0-9]*\n\tvldr\.64	d1, \.L[0-9]*\+8|vmsr	p0, r2	@ movhi)
 ** 	vpst
 ** 	vcx1at	p0, q0, #32
 ** 	bx	lr
@@ -731,8 +731,8 @@
 
 /*
 ** test_cde_vcx2q_mfloat16x8_tuint16x8_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -740,8 +740,8 @@
 */
 /*
 ** test_cde_vcx2q_mfloat16x8_tfloat32x4_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -749,8 +749,8 @@
 */
 /*
 ** test_cde_vcx2q_mfloat32x4_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -758,8 +758,8 @@
 */
 /*
 ** test_cde_vcx2q_mint64x2_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -767,8 +767,8 @@
 */
 /*
 ** test_cde_vcx2q_mint8x16_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -776,8 +776,8 @@
 */
 /*
 ** test_cde_vcx2q_muint16x8_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -785,8 +785,8 @@
 */
 /*
 ** test_cde_vcx2q_muint8x16_tint64x2_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -794,8 +794,8 @@
 */
 /*
 ** test_cde_vcx2q_muint8x16_tint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -803,8 +803,8 @@
 */
 /*
 ** test_cde_vcx2q_muint8x16_tuint16x8_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -812,8 +812,8 @@
 */
 /*
 ** test_cde_vcx2q_muint8x16_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2t	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -823,8 +823,8 @@
 
 /*
 ** test_cde_vcx2qa_mfloat16x8_tuint16x8_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -832,8 +832,8 @@
 */
 /*
 ** test_cde_vcx2qa_mfloat16x8_tfloat32x4_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -841,8 +841,8 @@
 */
 /*
 ** test_cde_vcx2qa_mfloat32x4_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -850,8 +850,8 @@
 */
 /*
 ** test_cde_vcx2qa_mint64x2_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -859,8 +859,8 @@
 */
 /*
 ** test_cde_vcx2qa_mint8x16_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -868,8 +868,8 @@
 */
 /*
 ** test_cde_vcx2qa_muint16x8_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -877,8 +877,8 @@
 */
 /*
 ** test_cde_vcx2qa_muint8x16_tint64x2_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -886,8 +886,8 @@
 */
 /*
 ** test_cde_vcx2qa_muint8x16_tint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -895,8 +895,8 @@
 */
 /*
 ** test_cde_vcx2qa_muint8x16_tuint16x8_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -904,8 +904,8 @@
 */
 /*
 ** test_cde_vcx2qa_muint8x16_tuint8x16_tint:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r1	@ movhi)
 ** 	vpst
 ** 	vcx2at	p0, (q[0-7]), q0, #32
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -915,8 +915,8 @@
 
 /*
 ** test_cde_vcx3q_muint8x16_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -924,8 +924,8 @@
 */
 /*
 ** test_cde_vcx3q_mfloat16x8_tfloat16x8_tfloat16x8_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -933,8 +933,8 @@
 */
 /*
 ** test_cde_vcx3q_mfloat32x4_tuint64x2_tfloat16x8_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -942,8 +942,8 @@
 */
 /*
 ** test_cde_vcx3q_muint16x8_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -951,8 +951,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tuint16x8_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -960,8 +960,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tuint8x16_tuint16x8_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -969,8 +969,8 @@
 */
 /*
 ** test_cde_vcx3q_mint8x16_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -978,8 +978,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -987,8 +987,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tuint8x16_tint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -996,8 +996,8 @@
 */
 /*
 ** test_cde_vcx3q_mint64x2_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1005,8 +1005,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tint64x2_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1014,8 +1014,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tuint8x16_tint64x2_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1023,8 +1023,8 @@
 */
 /*
 ** test_cde_vcx3q_muint8x16_tint64x2_tint64x2_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3t	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1034,8 +1034,8 @@
 
 /*
 ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1043,8 +1043,8 @@
 */
 /*
 ** test_cde_vcx3qa_mfloat16x8_tfloat16x8_tfloat16x8_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1052,8 +1052,8 @@
 */
 /*
 ** test_cde_vcx3qa_mfloat32x4_tuint64x2_tfloat16x8_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1061,8 +1061,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint16x8_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1070,8 +1070,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tuint16x8_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1079,8 +1079,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint16x8_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1088,8 +1088,8 @@
 */
 /*
 ** test_cde_vcx3qa_mint8x16_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1097,8 +1097,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1106,8 +1106,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tuint8x16_tint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1115,8 +1115,8 @@
 */
 /*
 ** test_cde_vcx3qa_mint64x2_tuint8x16_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1124,8 +1124,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tint64x2_tuint8x16_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1133,8 +1133,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tuint8x16_tint64x2_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
@@ -1142,8 +1142,8 @@
 */
 /*
 ** test_cde_vcx3qa_muint8x16_tint64x2_tint64x2_t:
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
-** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	 P0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
+** 	(?:vldr\.64	d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64	d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr	p0, r0	@ movhi)
 ** 	vpst
 ** 	vcx3at	p0, (q[0-7]), q0, q1, #15
 ** 	vmov	q0, \1([[:space:]]+@ [^\n]*)?
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/general/preserve_user_namespace_1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#define __ARM_MVE_PRESERVE_USER_NAMESPACE
+#include <arm_mve.h>
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	asrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64_t
-asrl_reg (int64_t longval3, int32_t x)
+foo (int64_t value, int32_t shift)
 {
-  return asrl (longval3, x);
+  return asrl (value, shift);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "asrl\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	lsll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint64_t
-lsll_reg (uint64_t longval3, int32_t x)
+foo (uint64_t value, int32_t shift)
 {
-  return lsll (longval3, x);
+  return lsll (value, shift);
+}
+
+/*
+**foo1:
+**	...
+**	lsll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint64_t
+foo1 (int32_t shift)
+{
+  return lsll (1, shift);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "lsll\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include <arm_mve.h>
-int8x16_t foo (int8x16_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-int16x8_t foo1 (int16x8_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-int32x4_t foo2 (int32x4_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-uint8x16_t foo3 (uint8x16_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-uint16x8_t foo4 (uint16x8_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-uint32x4_t foo5 (uint32x4_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-float16x8_t foo6 (float16x8_t a)
-{
-  return vaddq (a, (float16_t)23.6);
-}
-float32x4_t foo7 (float32x4_t a)
-{
-  return vaddq (a, (float32_t)23.46);
-}
-float16x8_t foo8 (float16x8_t a)
-{
-  return vaddq (a, 23.6);
-}
-float32x4_t foo9 (float32x4_t a)
-{
-  return vaddq (a, 23.46);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-fp.c
@@ -0,0 +1,61 @@
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-incompatible-pointer-types" { target c } } */
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive" { target c++ } } */
+#include "arm_mve.h"
+
+float f1;
+double f2;
+float16_t f3;
+float32_t f4;
+__fp16 f5;
+#ifndef __cplusplus
+_Float16 f6;
+#endif
+
+float16x8_t floatvec;
+
+/* Test a few different supported ways of passing a scalar int value.
+The intrinsic vmulq was chosen arbitrarily, but it is representative of
+all intrinsics that take a non-const scalar value.  */
+void
+test_scalars (void)
+{
+    /* Test a few different supported ways of passing a float value.  */
+    floatvec = vmulq(floatvec, 0.5);
+    floatvec = vmulq(floatvec, 0.5f);
+    floatvec = vmulq(floatvec, (__fp16) 0.5);
+    floatvec = vmulq(floatvec, f1);
+    floatvec = vmulq(floatvec, f2);
+    floatvec = vmulq(floatvec, f3);
+    floatvec = vmulq(floatvec, f4);
+    floatvec = vmulq(floatvec, f5);
+#ifndef __cplusplus
+    floatvec = vmulq(floatvec, f6);
+    floatvec = vmulq(floatvec, 0.15f16);
+    floatvec = vmulq(floatvec, (_Float16) 0.15);
+#endif
+}
+
+/* Next, test a number of valid pointer overloads.  */
+void
+foo11 (__fp16 * addr, float16x8_t value)
+{
+  vst1q (addr, value);
+}
+
+#ifndef __cplusplus
+void
+foo12 (_Float16 * addr, float16x8_t value)
+{
+  vst1q (addr, value);
+}
+#endif
+
+void
+foo13 (float * addr, float32x4_t value)
+{
+  vst1q (addr, value);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c
@@ -0,0 +1,100 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -Wno-incompatible-pointer-types" { target c } } */
+/* { dg-additional-options "-O2 -Wno-pedantic -Wno-long-long -fpermissive" { target c++ } } */
+#include "arm_mve.h"
+
+int i1;
+short i2;
+long i3;
+long long i4;
+int8_t i5;
+int16_t i6;
+int32_t i7;
+int64_t i8;
+
+int16x8_t intvec;
+
+/* Test a few different supported ways of passing a scalar int value.
+The intrinsic vmulq was chosen arbitrarily, but it is representative of
+all intrinsics that take a non-const scalar value.  */
+void
+test_scalars (void)
+{
+    intvec = vmulq(intvec, 2);
+    intvec = vmulq(intvec, (int32_t) 2);
+    intvec = vmulq(intvec, (short) 2);
+    intvec = vmulq(intvec, i1);
+    intvec = vmulq(intvec, i2);
+    intvec = vmulq(intvec, i3);
+    intvec = vmulq(intvec, i4);
+    intvec = vmulq(intvec, i5);
+    intvec = vmulq(intvec, i6);
+    intvec = vmulq(intvec, i7);
+    intvec = vmulq(intvec, i8);
+}
+
+/* Next, test a number of valid pointer overloads.  */
+void
+foo1 (signed char * addr, int8x16_t value)
+{
+  vst1q (addr, value);
+}
+
+void
+foo2 (short * addr, int16x8_t value)
+{
+  vst1q (addr, value);
+}
+
+/* Glibc defines int32_t as 'int' while newlib defines it as 'long int'.
+
+   Although these correspond to the same size, g++ complains when using the
+   'wrong' version:
+  invalid conversion from 'long int*' to 'int32_t*' {aka 'int*'} [-fpermissive]
+
+  The trick below is to make this test pass whether using glibc-based or
+  newlib-based toolchains.  */
+
+#if defined(__GLIBC__)
+#define word_type int
+#else
+#define word_type long int
+#endif
+void
+foo3 (word_type * addr, int32x4_t value)
+{
+  vst1q (addr, value);
+}
+
+void
+foo5 (long long * addr, uint64x2_t value)
+{
+  vldrdq_gather_offset (addr, value);
+}
+
+void
+foo6 (unsigned char * addr, uint8x16_t value)
+{
+  vst1q (addr, value);
+}
+
+void
+foo7 (unsigned short * addr, uint16x8_t value)
+{
+  vst1q (addr, value);
+}
+
+void
+foo8 (unsigned word_type * addr, uint32x4_t value)
+{
+  vst1q (addr, value);
+}
+
+void
+foo10 (unsigned long long * addr, uint64x2_t value)
+{
+  vldrdq_gather_offset (addr, value);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_m.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include <arm_mve.h>
-mve_pred16_t p;
-
-int32x4_t fn1 (int32x4_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_s32(), vecIdx, 1, p);
-}
-
-int16x8_t fn2 (int16x8_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_s16(), vecIdx, 1, p);
-}
-
-int8x16_t fn3 (int8x16_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_s8(), vecIdx, 1, p);
-}
-
-uint32x4_t fn4 (uint32x4_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_u32(), vecIdx, 1, p);
-}
-
-uint16x8_t fn5 (uint16x8_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_u16(), vecIdx, 1, p);
-}
-
-uint8x16_t fn6 (uint8x16_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_u8(), vecIdx, 1, p);
-}
-
-float32x4_t fn7 (float32x4_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_f32(), vecIdx, (float32_t) 1.23, p);
-}
-
-float16x8_t fn8 (float16x8_t vecIdx)
-{
-  return vaddq_m(vuninitializedq_f16(), vecIdx, (float16_t) 1.40, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include <arm_mve.h>
-int8x16_t foo (int8x16_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-int16x8_t foo1 (int16x8_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-int32x4_t foo2 (int32x4_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-uint8x16_t foo3 (uint8x16_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-uint16x8_t foo4 (uint16x8_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-uint32x4_t foo5 (uint32x4_t a, int16_t b)
-{
-  return vaddq (a, (b<<3));
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p)
-{
-  return vddupq_m (inactive, a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p)
-{
-  return vddupq_m (inactive, a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_m_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p)
-{
-  return vddupq_m (inactive, a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (int32_t a)
-{
-  return vddupq_u16 (a, 4);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (int32_t a)
-{
-  return vddupq_u32 (a, 1);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (int32_t a)
-{
-  return vddupq_u8 (a, 1);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint16x8_t
-foo1 (int32_t a, mve_pred16_t p)
-{
-  return vddupq_x_u16 (a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (int32_t a, mve_pred16_t p)
-{
-  return vddupq_x_u32 (a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vddupq_x_n_u8.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint8x16_t
-foo1 (int32_t a, mve_pred16_t p)
-{
-  return vddupq_x_u8 (a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
-  return vdwdupq_x_u16 (a, b, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
-  return vdwdupq_x_u32 (a, b, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
-  return vdwdupq_x_u8 (a, b, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (uint16x8_t inactive, int32_t a, mve_pred16_t p)
-{
-  return vidupq_m (inactive, a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (uint32x4_t inactive, int32_t a, mve_pred16_t p)
-{
-  return vidupq_m (inactive, a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_m_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (uint8x16_t inactive, int32_t a, mve_pred16_t p)
-{
-  return vidupq_m (inactive, a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (int32_t a)
-{
-  return vidupq_u16 (a, 4);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (int32_t a)
-{
-  return vidupq_u32 (a, 1);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (int32_t a)
-{
-  return vidupq_u8 (a, 1);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint16x8_t
-foo1 (int32_t a, mve_pred16_t p)
-{
-  return vidupq_x_u16 (a, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (int32_t a, mve_pred16_t p)
-{
-  return vidupq_x_u32 (a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vidupq_x_n_u8.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint8x16_t
-foo1 (int32_t a, mve_pred16_t p)
-{
-  return vidupq_x_u8 (a, 1, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
-  return viwdupq_x_u16 (a, b, 2, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
-  return viwdupq_x_u32 (a, b, 4, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_viwdupq_x_n_u8.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint8x16_t
-foo1 (int32_t a, uint32_t b, mve_pred16_t p)
-{
-  return viwdupq_x_u8 (a, b, 8, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_s64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int64x2_t
-foo1 (int64_t * base, uint64x2_t offset)
-{
-  return vldrdq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_u64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint64x2_t
-foo1 (uint64_t * base, uint64x2_t offset)
-{
-  return vldrdq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_s64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int64x2_t
-foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p)
-{
-  return vldrdq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_offset_z_u64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint64x2_t
-foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p)
-{
-  return vldrdq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_s64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int64x2_t
-foo1 (int64_t * base, uint64x2_t offset)
-{
-  return vldrdq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_u64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint64x2_t
-foo1 (uint64_t * base, uint64x2_t offset)
-{
-  return vldrdq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_s64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int64x2_t
-foo1 (int64_t * base, uint64x2_t offset, mve_pred16_t p)
-{
-  return vldrdq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrdq_gather_shifted_offset_z_u64.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint64x2_t
-foo1 (uint64_t * base, uint64x2_t offset, mve_pred16_t p)
-{
-  return vldrdq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_f16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16_t * base, uint16x8_t offset)
-{
-  return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int16x8_t
-foo1 (int16_t * base, uint16x8_t offset)
-{
-  return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_s32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int32x4_t
-foo1 (int16_t * base, uint32x4_t offset)
-{
-  return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint16x8_t
-foo1 (uint16_t * base, uint16x8_t offset)
-{
-  return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint16_t * base, uint32x4_t offset)
-{
-  return vldrhq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_f16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int16x8_t
-foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_s32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int32x4_t
-foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_offset_z_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_f16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16_t * base, uint16x8_t offset)
-{
-  return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int16x8_t
-foo1 (int16_t * base, uint16x8_t offset)
-{
-  return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int16_t * base, uint32x4_t offset)
-{
-  return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint16x8_t
-foo1 (uint16_t * base, uint16x8_t offset)
-{
-  return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint16_t * base, uint32x4_t offset)
-{
-  return vldrhq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_f16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler "vldrht.f16"  }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s16.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int16x8_t
-foo1 (int16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_s32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-int32x4_t
-foo1 (int16_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u16.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint16x8_t
-foo1 (uint16_t * base, uint16x8_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrhq_gather_shifted_offset_z_u32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-uint32x4_t
-foo1 (uint16_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrhq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_f32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32_t * base, uint32x4_t offset)
-{
-  return vldrwq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int32_t * base, uint32x4_t offset)
-{
-  return vldrwq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32_t * base, uint32x4_t offset)
-{
-  return vldrwq_gather_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_f32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrwq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrwq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_offset_z_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrwq_gather_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_f32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32_t * base, uint32x4_t offset)
-{
-  return vldrwq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int32_t * base, uint32x4_t offset)
-{
-  return vldrwq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32_t * base, uint32x4_t offset)
-{
-  return vldrwq_gather_shifted_offset (base, offset);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_f32.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrwq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_s32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int32x4_t
-foo1 (int32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrwq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldrwq_gather_shifted_offset_z_u32.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-uint32x4_t
-foo1 (uint32_t * base, uint32x4_t offset, mve_pred16_t p)
-{
-  return vldrwq_gather_shifted_offset_z (base, offset, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-int
-foowu32( uint32_t * pDataSrc, uint32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc);
-    uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[4]);
-    vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs1, vecIn1);
-    vstrwq_scatter_shifted_offset_u32 (pDataDest, vecOffs2, vecIn2);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foowf32( float32_t * pDataSrc, float32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    float32x4_t vecIn1 = vldrwq_f32 ((float32_t const *) pDataSrc);
-    float32x4_t vecIn2 = vldrwq_f32 ((float32_t const *) &pDataSrc[4]);
-    vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs1, vecIn1);
-    vstrwq_scatter_shifted_offset_f32 (pDataDest, vecOffs2, vecIn2);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foohu16( uint16_t * pDataSrc, uint16_t * pDataDest)
-{
-    const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
-    const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
-    uint16x8_t vecIn1 = vldrhq_u16 ((uint16_t const *) pDataSrc);
-    uint16x8_t vecIn2 = vldrhq_u16 ((uint16_t const *) &pDataSrc[8]);
-    vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs1, vecIn1);
-    vstrhq_scatter_shifted_offset_u16 (pDataDest, vecOffs2, vecIn2);
-    pDataDest[16] = pDataSrc[16];
-    return 0;
-}
-
-int
-foohu32( uint32_t * pDataSrc, uint32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    uint32x4_t vecIn1 = vldrhq_u32 ((uint16_t const *) pDataSrc);
-    uint32x4_t vecIn2 = vldrhq_u32 ((uint16_t const *) &pDataSrc[4]);
-    vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs1, vecIn1);
-    vstrhq_scatter_shifted_offset_u32 ((uint16_t *)pDataDest, vecOffs2, vecIn2);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foohf16( float16_t * pDataSrc, float16_t * pDataDest)
-{
-    const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
-    const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
-    float16x8_t vecIn1 = vldrhq_f16 ((float16_t const *) pDataSrc);
-    float16x8_t vecIn2 = vldrhq_f16 ((float16_t const *) &pDataSrc[8]);
-    vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs1, vecIn1);
-    vstrhq_scatter_shifted_offset_f16 (pDataDest, vecOffs2, vecIn2);
-    pDataDest[16] = pDataSrc[16];
-    return 0;
-}
-
-int
-foodu64( uint64_t * pDataSrc, uint64_t * pDataDest)
-{
-    const uint64x2_t vecOffs1 = { 0, 1};
-    const uint64x2_t vecOffs2 = { 2, 3};
-    uint32x4_t vecIn1 = vldrwq_u32 ((uint32_t const *) pDataSrc);
-    uint32x4_t vecIn2 = vldrwq_u32 ((uint32_t const *) &pDataSrc[2]);
-
-    vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs1, (uint64x2_t) vecIn1);
-    vstrdq_scatter_shifted_offset_u64 (pDataDest, vecOffs2, (uint64x2_t) vecIn2);
-
-    pDataDest[2] = pDataSrc[2];
-    return 0;
-}
-
-int
-foows32( int32_t * pDataSrc, int32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc);
-    int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[4]);
-    vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs1, vecIn1);
-    vstrwq_scatter_shifted_offset_s32 (pDataDest, vecOffs2, vecIn2);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foohs16( int16_t * pDataSrc, int16_t * pDataDest)
-{
-    const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
-    const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
-    int16x8_t vecIn1 = vldrhq_s16 ((int16_t const *) pDataSrc);
-    int16x8_t vecIn2 = vldrhq_s16 ((int16_t const *) &pDataSrc[8]);
-    vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs1, vecIn1);
-    vstrhq_scatter_shifted_offset_s16 (pDataDest, vecOffs2, vecIn2);
-    pDataDest[16] = pDataSrc[16];
-    return 0;
-}
-
-int
-foohs32( int32_t * pDataSrc, int32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    int32x4_t vecIn1 = vldrhq_s32 ((int16_t const *) pDataSrc);
-    int32x4_t vecIn2 = vldrhq_s32 ((int16_t const *) &pDataSrc[4]);
-    vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs1, vecIn1);
-    vstrhq_scatter_shifted_offset_s32 ((int16_t *)pDataDest, vecOffs2, vecIn2);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foods64( int64_t * pDataSrc, int64_t * pDataDest)
-{
-    const uint64x2_t vecOffs1 = { 0, 1};
-    const uint64x2_t vecOffs2 = { 2, 3};
-    int32x4_t vecIn1 = vldrwq_s32 ((int32_t const *) pDataSrc);
-    int32x4_t vecIn2 = vldrwq_s32 ((int32_t const *) &pDataSrc[2]);
-
-    vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs1, (int64x2_t) vecIn1);
-    vstrdq_scatter_shifted_offset_s64 (pDataDest, vecOffs2, (int64x2_t) vecIn2);
-
-    pDataDest[2] = pDataSrc[2];
-    return 0;
-}
-
-/* { dg-final { scan-assembler-times "vstr\[a-z\]" 20 } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-
-mve_pred16_t __p;
-int
-foowu32( uint32_t * pDataSrc, uint32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p);
-    uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[4], __p);
-    vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs1, vecIn1, __p);
-    vstrwq_scatter_shifted_offset_p_u32 (pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foowf32( float32_t * pDataSrc, float32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    float32x4_t vecIn1 = vldrwq_z_f32 ((float32_t const *) pDataSrc, __p);
-    float32x4_t vecIn2 = vldrwq_z_f32 ((float32_t const *) &pDataSrc[4], __p);
-    vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs1, vecIn1, __p);
-    vstrwq_scatter_shifted_offset_p_f32 (pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foohu16( uint16_t * pDataSrc, uint16_t * pDataDest)
-{
-    const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
-    const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
-    uint16x8_t vecIn1 = vldrhq_z_u16 ((uint16_t const *) pDataSrc, __p);
-    uint16x8_t vecIn2 = vldrhq_z_u16 ((uint16_t const *) &pDataSrc[8], __p);
-    vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs1, vecIn1, __p);
-    vstrhq_scatter_shifted_offset_p_u16 (pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[16] = pDataSrc[16];
-    return 0;
-}
-
-int
-foohu32( uint32_t * pDataSrc, uint32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    uint32x4_t vecIn1 = vldrhq_z_u32 ((uint16_t const *) pDataSrc, __p);
-    uint32x4_t vecIn2 = vldrhq_z_u32 ((uint16_t const *) &pDataSrc[4], __p);
-    vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs1, vecIn1, __p);
-    vstrhq_scatter_shifted_offset_p_u32 ((uint16_t *)pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foohf16( float16_t * pDataSrc, float16_t * pDataDest)
-{
-    const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
-    const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
-    float16x8_t vecIn1 = vldrhq_z_f16 ((float16_t const *) pDataSrc, __p);
-    float16x8_t vecIn2 = vldrhq_z_f16 ((float16_t const *) &pDataSrc[8], __p);
-    vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs1, vecIn1, __p);
-    vstrhq_scatter_shifted_offset_p_f16 (pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[16] = pDataSrc[16];
-    return 0;
-}
-
-int
-foodu64( uint64_t * pDataSrc, uint64_t * pDataDest)
-{
-    const uint64x2_t vecOffs1 = { 0, 1};
-    const uint64x2_t vecOffs2 = { 2, 3};
-    uint32x4_t vecIn1 = vldrwq_z_u32 ((uint32_t const *) pDataSrc, __p);
-    uint32x4_t vecIn2 = vldrwq_z_u32 ((uint32_t const *) &pDataSrc[2], __p);
-
-    vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs1, (uint64x2_t) vecIn1, __p);
-    vstrdq_scatter_shifted_offset_p_u64 (pDataDest, vecOffs2, (uint64x2_t) vecIn2, __p);
-
-    pDataDest[2] = pDataSrc[2];
-    return 0;
-}
-
-int
-foows32( int32_t * pDataSrc, int32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p);
-    int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[4], __p);
-    vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs1, vecIn1, __p);
-    vstrwq_scatter_shifted_offset_p_s32 (pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foohs16( int16_t * pDataSrc, int16_t * pDataDest)
-{
-    const uint16x8_t vecOffs1 = { 0, 3, 6, 1, 4, 7, 2, 5};
-    const uint16x8_t vecOffs2 = { 9, 11, 13, 10, 12, 15, 8, 14};
-    int16x8_t vecIn1 = vldrhq_z_s16 ((int16_t const *) pDataSrc, __p);
-    int16x8_t vecIn2 = vldrhq_z_s16 ((int16_t const *) &pDataSrc[8], __p);
-    vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs1, vecIn1, __p);
-    vstrhq_scatter_shifted_offset_p_s16 (pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[16] = pDataSrc[16];
-    return 0;
-}
-
-int
-foohs32( int32_t * pDataSrc, int32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    int32x4_t vecIn1 = vldrhq_z_s32 ((int16_t const *) pDataSrc, __p);
-    int32x4_t vecIn2 = vldrhq_z_s32 ((int16_t const *) &pDataSrc[4], __p);
-    vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs1, vecIn1, __p);
-    vstrhq_scatter_shifted_offset_p_s32 ((int16_t *)pDataDest, vecOffs2, vecIn2, __p);
-    pDataDest[8] = pDataSrc[8];
-    return 0;
-}
-
-int
-foods64( int64_t * pDataSrc, int64_t * pDataDest)
-{
-    const uint64x2_t vecOffs1 = { 0, 1};
-    const uint64x2_t vecOffs2 = { 2, 3};
-    int32x4_t vecIn1 = vldrwq_z_s32 ((int32_t const *) pDataSrc, __p);
-    int32x4_t vecIn2 = vldrwq_z_s32 ((int32_t const *) &pDataSrc[2], __p);
-
-    vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs1, (int64x2_t) vecIn1, __p);
-    vstrdq_scatter_shifted_offset_p_s64 (pDataDest, vecOffs2, (int64x2_t) vecIn2, __p);
-
-    pDataDest[2] = pDataSrc[2];
-    return 0;
-}
-
-/* { dg-final { scan-assembler-times "vstr\[a-z\]t" 20 } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	sqrshr	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32_t
-sqrshr_reg (int32_t longval3, int32_t x)
+foo (int32_t value, int32_t shift)
 {
-  return sqrshr (longval3, x);
+  return sqrshr (value, shift);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "sqrshr\\tr\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	sqrshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64_t
-sqrshrl_reg (int64_t longval3, int32_t x)
+foo (int64_t value, int32_t shift)
 {
-  return sqrshrl_sat48 (longval3, x);
+  return sqrshrl_sat48 (value, shift);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "sqrshrl\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	sqshl	(?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-sqshl_imm (int32_t longval3)
+foo (int32_t value)
 {
-  return sqshl (longval3, 25);
+  return sqshl (value, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "sqshl\\tr\[0-9\]+, #25" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	sqshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-sqshll_imm(int64_t value)
+foo (int64_t value)
 {
-  return sqshll (value, 21);
+  return sqshll (value, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "sqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	srshr	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int32_t
-srshr_imm (int32_t longval3)
+foo (int32_t value)
 {
-  return srshr (longval3, 25);
+  return srshr (value, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "srshr\\tr\[0-9\]+, #25" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	srshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 int64_t
-srshrl_imm(int64_t value)
+foo (int64_t value)
 {
-  return srshrl (value, 21);
+  return srshrl (value, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "srshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	uqrshl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32_t
-uqrshl_reg (uint32_t longval3, int32_t x)
+foo (uint32_t value, int32_t shift)
 {
-  return uqrshl (longval3, x);
+  return uqrshl (value, shift);
+}
+
+/*
+**foo1:
+**	...
+**	uqrshl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32_t
+foo1 (int32_t shift)
+{
+  return uqrshl (1, shift);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "uqrshl\\tr\[0-9\]+, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	uqrshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint64_t
-uqrshll_reg (uint64_t longval3, int32_t x)
+foo (uint64_t value, int32_t shift)
 {
-  return uqrshll_sat48 (longval3, x);
+  return uqrshll_sat48 (value, shift);
+}
+
+/*
+**foo1:
+**	...
+**	uqrshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #48, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint64_t
+foo1 (int32_t shift)
+{
+  return uqrshll_sat48 (1, shift);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "uqrshll\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	uqshl	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint32_t
-uqshl_imm (uint32_t longval3)
+foo (uint32_t value)
 {
-  return uqshl (longval3, 21);
+  return uqshl (value, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "uqshl\\tr\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	uqshll	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint64_t
-uqshll_imm(uint64_t value)
+foo (uint64_t value)
 {
-  return uqshll (value, 21);
+  return uqshll (value, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "uqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint64_t
-urshr_imm (uint32_t longval3)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	urshr	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
+uint32_t
+foo (uint32_t value)
+{
+  return urshr (value, 1);
+}
+
+/*
+**foo1:
+**	...
+**	urshr	(?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
+uint32_t
+foo1 ()
 {
-  return urshr (longval3, 21);
+  return urshr (1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "urshr\\tr\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	urshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
 uint64_t
-urshrl_imm(uint64_t value)
+foo (uint64_t value)
 {
-  return urshrl (value, 21);
+  return urshrl (value, 1);
+}
+
+/*
+**foo1:
+**	...
+**	urshrl	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?:	@.*|)
+**	...
+*/
+uint64_t
+foo1 ()
+{
+  return urshrl (1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "urshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vabavq_p_s16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vabavq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.s16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+  return vabavq_p (1, b, c, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vabavq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vabavq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.s32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vabavq_p (1, b, c, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
 {
   return vabavq_p_s8 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
 {
   return vabavq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.s8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int8x16_t b, int8x16_t c, mve_pred16_t p)
+{
+  return vabavq_p (1, b, c, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
 {
   return vabavq_p_u16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
 {
   return vabavq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+{
+  return vabavq_p (1, b, c, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
 {
   return vabavq_p_u32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
 {
   return vabavq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+{
+  return vabavq_p (1, b, c, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p)
 {
   return vabavq_p_u8 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p)
 {
   return vabavq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vabavt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabavt.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint8x16_t b, uint8x16_t c, mve_pred16_t p)
+{
+  return vabavq_p (1, b, c, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int16x8_t b, int16x8_t c)
 {
   return vabavq_s16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int16x8_t b, int16x8_t c)
 {
   return vabavq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.s16"  }  } */
+/*
+**foo2:
+**	...
+**	vabav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int16x8_t b, int16x8_t c)
+{
+  return vabavq (1, b, c);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int32x4_t b, int32x4_t c)
 {
   return vabavq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int32x4_t b, int32x4_t c)
 {
   return vabavq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.s32"  }  } */
+/*
+**foo2:
+**	...
+**	vabav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int32x4_t b, int32x4_t c)
+{
+  return vabavq (1, b, c);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int8x16_t b, int8x16_t c)
 {
   return vabavq_s8 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int8x16_t b, int8x16_t c)
 {
   return vabavq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.s8"  }  } */
+/*
+**foo2:
+**	...
+**	vabav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int8x16_t b, int8x16_t c)
+{
+  return vabavq (1, b, c);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabav.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint16x8_t b, uint16x8_t c)
 {
   return vabavq_u16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabav.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint16x8_t b, uint16x8_t c)
 {
   return vabavq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vabav.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint16x8_t b, uint16x8_t c)
+{
+  return vabavq (1, b, c);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabav.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b, uint32x4_t c)
 {
   return vabavq_u32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabav.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b, uint32x4_t c)
 {
   return vabavq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vabav.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint32x4_t b, uint32x4_t c)
+{
+  return vabavq (1, b, c);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabav.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint8x16_t b, uint8x16_t c)
 {
   return vabavq_u8 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabav.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint8x16_t b, uint8x16_t c)
 {
   return vabavq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vabav.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vabav.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint8x16_t b, uint8x16_t c)
+{
+  return vabavq (1, b, c);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabd.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vabdq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabd.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vabdq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vabdq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vabdq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vabdq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vabdq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vabdq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vabdq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vabdq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vabdq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vabdq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vabdq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vabdq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vabdq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vabdq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vabdq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vabdq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vabdq (a, b);
 }
 
-/* { dg-final { scan-assembler "vabd.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vabdq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vabdq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vabdq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vabdq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vabdq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vabdq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vabdq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vabdq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabdt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabdt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vabdq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabs.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vabsq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vabs.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vabs.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vabsq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabs.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vabsq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vabs.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vabs.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vabsq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vabsq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vabsq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vabsq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vabsq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vabsq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabs.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vabsq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vabs.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabs.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vabsq (a);
 }
 
-/* { dg-final { scan-assembler "vabs.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabs.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vabsq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vabs.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabs.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vabsq (a);
 }
 
-/* { dg-final { scan-assembler "vabs.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vabs.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vabsq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vabs.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vabs.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vabsq (a);
 }
 
-/* { dg-final { scan-assembler "vabs.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vabsq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vabsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vabsq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vabsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vabsq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vabsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vabsq_x_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vabsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vabsq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vabst.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vabst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vabsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vadciq_m_s32 (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vadciq_m (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vadciq_m_u32 (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vadciq_m (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadcit.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
 {
   return vadciq_s32 (a, b, carry_out);
 }
 
-/* { dg-final { scan-assembler "vadci.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry_out)
 {
   return vadciq (a, b, carry_out);
 }
 
-/* { dg-final { scan-assembler "vadci.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 {
   return vadciq_u32 (a, b, carry_out);
 }
 
-/* { dg-final { scan-assembler "vadci.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 {
   return vadciq (a, b, carry_out);
 }
 
-/* { dg-final { scan-assembler "vadci.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
@@ -1,23 +1,77 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
 {
   return vadcq_m_s32 (inactive, a, b, carry, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
 {
   return vadcq_m (inactive, a, b, carry, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
@@ -1,23 +1,77 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
 {
   return vadcq_m_u32 (inactive, a, b, carry, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vadct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
 {
   return vadcq_m (inactive, a, b, carry, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vadct.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
@@ -1,21 +1,69 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vadc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry)
+foo (int32x4_t a, int32x4_t b, unsigned *carry)
 {
   return vadcq_s32 (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vadc.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vadc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry)
 {
   return vadcq (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vadc.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
@@ -1,21 +1,69 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vadc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
 {
   return vadcq_u32 (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vadc.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vadc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry)
 {
   return vadcq (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vadc.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddlvaq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddlvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvat.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint64_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddlvaq_p_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvat.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint64_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddlvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvat.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint32x4_t b, mve_pred16_t p)
+{
+  return vaddlvaq_p (1, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddlva.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b)
 {
   return vaddlvaq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddlva.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddlva.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b)
 {
   return vaddlvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddlva.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddlva.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint64_t a, uint32x4_t b)
 {
   return vaddlvaq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddlva.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddlva.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint64_t a, uint32x4_t b)
 {
   return vaddlvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddlva.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vaddlva.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint32x4_t b)
+{
+  return vaddlvaq (1, b);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vaddlvq_p_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vaddlvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvt.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vaddlvq_p_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddlvt.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vaddlvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddlvt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddlv.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a)
 {
   return vaddlvq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vaddlv.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddlv.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a)
 {
-  return vaddlvq_s32 (a);
+  return vaddlvq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vaddlv.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddlv.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint32x4_t a)
 {
-    return vaddlvq_u32 (a);
+  return vaddlvq_u32 (a);
 }
 
-/* { dg-final { scan-assembler "vaddlv.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddlv.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint32x4_t a)
 {
-    return vaddlvq (a);
+  return vaddlvq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vaddlv.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vaddq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vaddq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vaddq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vaddq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vaddq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vaddq_m_n_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vaddq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vaddq_m_n_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vaddq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vaddq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vaddq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vaddq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vaddq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vaddq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vaddq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vaddq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vaddq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vaddq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vaddq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b)
 {
   return vaddq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vadd.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t a)
+{
+  return vaddq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b)
 {
   return vaddq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vadd.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t a)
+{
+  return vaddq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vaddq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vaddq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vaddq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vaddq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vaddq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vaddq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vaddq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vaddq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vaddq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vaddq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vaddq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vaddq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vaddq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vaddq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vaddq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vadd.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vadd.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vaddq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vaddq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vaddq_x (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vaddq_x_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vaddq_x (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vaddq_x (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vaddq_x_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vaddq_x (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vaddq_x_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vaddq_x_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vaddq_x_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vaddq_x_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vaddq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vaddq_x_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vaddq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vaddq_x_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vaddq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vaddq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vaddq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vaddq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vaddq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int16x8_t b, mve_pred16_t p)
 {
   return vaddvaq_p_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int16x8_t b, mve_pred16_t p)
 {
   return vaddvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddvaq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, mve_pred16_t p)
 {
   return vaddvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int8x16_t b, mve_pred16_t p)
 {
   return vaddvaq_p_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int8x16_t b, mve_pred16_t p)
 {
   return vaddvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vaddvaq_p_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vaddvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint16x8_t b, mve_pred16_t p)
+{
+  return vaddvaq_p (1, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddvaq_p_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vaddvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint32x4_t b, mve_pred16_t p)
+{
+  return vaddvaq_p (1, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vaddvaq_p_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vaddvaq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vaddvat.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvat.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint8x16_t b, mve_pred16_t p)
+{
+  return vaddvaq_p (1, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddva.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int16x8_t b)
 {
   return vaddvaq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddva.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int16x8_t b)
 {
   return vaddvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddva.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b)
 {
   return vaddvaq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddva.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b)
 {
   return vaddvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddva.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int8x16_t b)
 {
   return vaddvaq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddva.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int8x16_t b)
 {
   return vaddvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddva.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint16x8_t b)
 {
   return vaddvaq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddva.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint16x8_t b)
 {
   return vaddvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vaddva.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint16x8_t b)
+{
+  return vaddvaq (1, b);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddva.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b)
 {
   return vaddvaq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddva.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b)
 {
   return vaddvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vaddva.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint32x4_t b)
+{
+  return vaddvaq (1, b);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddva.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint8x16_t b)
 {
   return vaddvaq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddva.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint8x16_t b)
 {
   return vaddvaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vaddva.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vaddva.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint8x16_t b)
+{
+  return vaddvaq (1, b);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vaddvq_p_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vaddvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vaddvq_p_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vaddvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vaddvq_p_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vaddvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vaddvq_p_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vaddvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vaddvq_p_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vaddvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vaddvq_p_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vaddvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vaddvq_p (a, p);
 }
 
-/* { dg-final { scan-assembler "vaddvt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddv.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int16x8_t a)
 {
   return vaddvq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddv.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int16x8_t a)
 {
-  return vaddvq_s16 (a);
+  return vaddvq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vaddv.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddv.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32x4_t a)
 {
   return vaddvq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddv.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32x4_t a)
 {
-  return vaddvq_s32 (a);
+  return vaddvq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vaddv.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddv.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int8x16_t a)
 {
   return vaddvq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddv.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int8x16_t a)
 {
   return vaddvq (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint16x8_t a)
 {
-    return vaddvq_u16 (a);
+  return vaddvq_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint16x8_t a)
 {
-    return vaddvq (a);
+  return vaddvq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vaddv.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32x4_t a)
 {
-    return vaddvq_u32 (a);
+  return vaddvq_u32 (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32x4_t a)
 {
-    return vaddvq (a);
+  return vaddvq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vaddv.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vaddv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint8x16_t a)
 {
-    return vaddvq_u8 (a);
+  return vaddvq_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vaddv.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vaddv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint8x16_t a)
 {
-    return vaddvq (a);
+  return vaddvq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vaddv.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vandq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vandq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vandq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vandq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vandq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vandq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vandq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vandq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vandq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vandq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vandq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vandq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vandq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vandq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vandq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vandq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vandq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
 
+/*
+**foo1:
+**	...
+**	vand	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vandq (a, b);
 }
 
-/* { dg-final { scan-assembler "vand"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vandq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vandq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vandq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vandq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vandq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vandq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vandq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vandq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vandt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vandt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vandq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vbicq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vbicq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vbicq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vbicq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-  return vbicq_m_n_s16 (a, 16, p);
+  return vbicq_m_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
-  return vbicq_m_n (a, 16, p);
+  return vbicq_m_n (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vbicq_m_n_s32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vbicq_m_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vbicq_m_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vbicq_m_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vbicq_m_n_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vbicq_m_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vbicq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vbicq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vbicq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vbicq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vbicq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vbicq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vbicq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vbicq_n_s16 (a, 1);
 }
 
+
+/*
+**foo1:
+**	...
+**	vbic.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vbicq (a, 1);
 }
 
-/* { dg-final { scan-assembler-times "vbic.i16" 2 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vbicq_n_s32 (a, 1);
 }
 
+
+/*
+**foo1:
+**	...
+**	vbic.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vbicq (a, 1);
 }
 
-/* { dg-final { scan-assembler-times "vbic.i32" 2 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
   return vbicq_n_u16 (a, 1);
 }
 
+
+/*
+**foo1:
+**	...
+**	vbic.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
   return vbicq (a, 1);
 }
 
-/* { dg-final { scan-assembler-times "vbic.i16" 2 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
   return vbicq_n_u32 (a, 1);
 }
 
+
+/*
+**foo1:
+**	...
+**	vbic.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
   return vbicq (a, 1);
 }
 
-/* { dg-final { scan-assembler-times "vbic.i32" 2 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vbicq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vbicq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vbicq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vbicq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vbicq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vbicq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbic	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vbicq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbic"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vbicq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vbicq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vbicq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vbicq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vbicq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vbicq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vbicq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vbicq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbict"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbict	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vbicq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, int32_t b)
 {
   return vbrsrq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, int32_t b)
 {
   return vbrsrq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b)
 {
   return vbrsrq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vbrsrq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b)
 {
   return vbrsrq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b)
 {
   return vbrsrq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b)
 {
   return vbrsrq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vbrsr.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b)
 {
   return vbrsrq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vbrsr.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b)
 {
   return vbrsrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vbrsr.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vbrsrt.8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vbrsrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vbrsrt.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcaddq_rot270_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcaddq_rot270_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcaddq_rot270_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcaddq_rot270_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcaddq_rot270_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vcaddq_rot270_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vcaddq_rot270_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vcaddq_rot270_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcaddq_rot90_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcaddq_rot90_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcaddq_rot90_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcaddq_rot90_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcaddq_rot90_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vcaddq_rot90_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vcaddq_rot90_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vcaddq_rot90_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcadd.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcadd.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcaddt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcaddt.i8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vclsq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclst.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vclsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vclsq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclst.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vclsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vclsq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclst.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vclsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcls.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vclsq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vcls.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcls.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vclsq (a);
 }
 
-/* { dg-final { scan-assembler "vcls.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcls.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vclsq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vcls.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcls.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vclsq (a);
 }
 
-/* { dg-final { scan-assembler "vcls.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcls.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vclsq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vcls.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcls.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vclsq (a);
 }
 
-/* { dg-final { scan-assembler "vcls.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vclsq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclst.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vclsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vclsq_x_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclst.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vclsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vclsq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclst.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vclsq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vclzq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vclzq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vclzq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vclzq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vclzq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vclzq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vclzq_m_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vclzq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vclzq_m_u32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vclzq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vclzq_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vclzq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vclz.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vclzq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vclz.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vclzq (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vclz.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vclzq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vclz.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vclzq (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vclz.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vclzq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vclz.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vclzq (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vclz.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-    return vclzq_u16 (a);
+  return vclzq_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vclz.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-    return vclzq (a);
+  return vclzq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vclz.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vclz.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
-    return vclzq_u32 (a);
+  return vclzq_u32 (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vclz.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
-    return vclzq (a);
+  return vclzq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vclz.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vclz.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-    return vclzq_u8 (a);
+  return vclzq_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vclz.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vclz.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-    return vclzq (a);
+  return vclzq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vclz.i8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vclzq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vclzq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vclzq_x_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vclzq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vclzq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vclzq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vclzq_x_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vclzq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vclzq_x_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vclzq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vclzq_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vclzt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vclzt.i8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vclzq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_f16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_f32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_m_f16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_m_f32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_rot180_f16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_rot180 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_rot180_f32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_rot180 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_rot180_m_f16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_rot180_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_rot180_m_f32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_rot180_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_rot270_f16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_rot270 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_rot270_f32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_rot270 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_rot270_m_f16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_rot270_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_rot270_m_f32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_rot270_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_rot90_f16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
 {
   return vcmlaq_rot90 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_rot90_f32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmla.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
 {
   return vcmlaq_rot90 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vcmla.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_rot90_m_f16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
 {
   return vcmlaq_rot90_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_rot90_m_f32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmlat.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
 {
   return vcmlaq_rot90_m (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmlat.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmpcsq_m_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmpcsq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vcmpcsq_m (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmpcsq_m_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmpcsq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vcmpcsq_m (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmpcsq_m_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmpcsq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vcmpcsq_m (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmpcsq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmpcsq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmpcsq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmpcsq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmpcsq_m_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmpcsq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.u16	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vcmpcsq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u16	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vcmpcsq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.u16	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a)
+{
+  return vcmpcsq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.u32	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vcmpcsq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u32	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vcmpcsq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.u32	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a)
+{
+  return vcmpcsq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.u8	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vcmpcsq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u8	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vcmpcsq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.u8	cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a)
+{
+  return vcmpcsq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.u16	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vcmpcsq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u16	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vcmpcsq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.u32	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vcmpcsq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u32	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vcmpcsq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.u8	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vcmpcsq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u8	cs, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vcmpcsq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmpeqq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmpeqq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vcmpeqq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vcmpeqq_m (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vcmpeqq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vcmpeqq_m (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vcmpeqq_m (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vcmpeqq_m (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vcmpeqq_m (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmpeqq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vcmpeqq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b)
 {
   return vcmpeqq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.f16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a)
+{
+  return vcmpeqq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vcmpeqq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b)
 {
   return vcmpeqq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.f32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a)
+{
+  return vcmpeqq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b)
 {
   return vcmpeqq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b)
 {
   return vcmpeqq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b)
 {
   return vcmpeqq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vcmpeqq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.i16	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a)
+{
+  return vcmpeqq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vcmpeqq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.i32	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a)
+{
+  return vcmpeqq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vcmpeqq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.i8	eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a)
+{
+  return vcmpeqq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcmpeqq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcmpeqq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcmpeqq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vcmpeqq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vcmpeqq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vcmpeqq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	eq, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vcmpeqq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmpgeq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmpgeq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vcmpgeq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vcmpgeq_m (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vcmpgeq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vcmpgeq_m (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpgeq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpgeq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vcmpgeq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b)
 {
   return vcmpgeq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.f16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a)
+{
+  return vcmpgeq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vcmpgeq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b)
 {
   return vcmpgeq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.f32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a)
+{
+  return vcmpgeq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b)
 {
   return vcmpgeq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b)
 {
   return vcmpgeq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s8	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b)
 {
   return vcmpgeq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcmpgeq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcmpgeq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s8	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcmpgeq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	ge, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcmpgeq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmpgtq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmpgtq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vcmpgtq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vcmpgtq_m (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vcmpgtq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vcmpgtq_m (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpgtq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpgtq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vcmpgtq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b)
 {
   return vcmpgtq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.f16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a)
+{
+  return vcmpgtq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vcmpgtq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b)
 {
   return vcmpgtq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.f32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a)
+{
+  return vcmpgtq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b)
 {
   return vcmpgtq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b)
 {
   return vcmpgtq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s8	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b)
 {
   return vcmpgtq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcmpgtq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcmpgtq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s8	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcmpgtq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	gt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcmpgtq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmphiq_m_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmphiq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vcmphiq_m (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmphiq_m_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmphiq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vcmphiq_m (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmphiq_m_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmphiq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vcmphiq_m (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmphiq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u16	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmphiq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmphiq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u32	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmphiq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmphiq_m_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.u8	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmphiq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.u16	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vcmphiq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u16	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vcmphiq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.u16	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a)
+{
+  return vcmphiq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.u32	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vcmphiq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u32	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vcmphiq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.u32	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a)
+{
+  return vcmphiq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.u8	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vcmphiq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u8	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vcmphiq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.u8	hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a)
+{
+  return vcmphiq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.u16	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vcmphiq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u16	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vcmphiq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.u32	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vcmphiq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u32	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vcmphiq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.u8	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vcmphiq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.u8	hi, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vcmphiq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmpleq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmpleq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpleq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpleq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vcmpleq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpleq_m_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vcmpleq_m (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vcmpleq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpleq_m_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vcmpleq_m (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpleq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpleq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpleq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpleq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpleq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpleq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpleq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vcmpleq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b)
 {
   return vcmpleq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.f16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a)
+{
+  return vcmpleq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vcmpleq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b)
 {
   return vcmpleq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.f32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a)
+{
+  return vcmpleq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b)
 {
   return vcmpleq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b)
 {
   return vcmpleq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s8	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b)
 {
   return vcmpleq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	le, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcmpleq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcmpleq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s8	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcmpleq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	le, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcmpleq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmpltq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmpltq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpltq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpltq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vcmpltq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpltq_m_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vcmpltq_m (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vcmpltq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpltq_m_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vcmpltq_m (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpltq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpltq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpltq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpltq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpltq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpltq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.s8	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpltq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vcmpltq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b)
 {
   return vcmpltq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.f16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a)
+{
+  return vcmpltq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vcmpltq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b)
 {
   return vcmpltq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.f32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a)
+{
+  return vcmpltq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b)
 {
   return vcmpltq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b)
 {
   return vcmpltq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s8	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b)
 {
   return vcmpltq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcmpltq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s16	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcmpltq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s32	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.s8	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcmpltq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.s8	lt, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcmpltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmpneq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmpneq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpneq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpneq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vcmpneq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vcmpneq_m (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vcmpneq_m (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.f32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vcmpneq_m (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vcmpneq_m (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vcmpneq_m (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c
@@ -1,22 +1,71 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmpneq_m_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vcmpneq_m (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpneq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpneq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpneq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmpneq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmpneq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmpneq_m_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmpt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmpt.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vcmpneq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vcmpneq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float16x8_t a, float16_t b)
 {
   return vcmpneq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f16"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.f16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float16x8_t a)
+{
+  return vcmpneq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-mve_pred16_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vcmpneq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.f32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (float32x4_t a, float32_t b)
 {
   return vcmpneq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.f32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.f32"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.f32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (float32x4_t a)
+{
+  return vcmpneq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16_t b)
 {
   return vcmpneq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32_t b)
 {
   return vcmpneq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8_t b)
 {
   return vcmpneq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vcmpneq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.i16	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint16x8_t a)
+{
+  return vcmpneq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vcmpneq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.i32	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint32x4_t a)
+{
+  return vcmpneq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c
@@ -1,21 +1,59 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vcmpneq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+/*
+**foo2: { xfail *-*-* }
+**	...
+**	vcmp.i8	ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
+mve_pred16_t
+foo2 (uint8x16_t a)
+{
+  return vcmpneq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vcmpneq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vcmpneq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vcmpneq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vcmpneq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i16	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vcmpneq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i32	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmp.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vcmpneq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmp.i8	ne, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vcmpneq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmp.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmulq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmulq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot180_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot180 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot180_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot180 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #180(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot270_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot270_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot90_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot90_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcmul.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f16	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcmult.f32	q[0-9]+, q[0-9]+, q[0-9]+, #0(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c
@@ -1,13 +1,42 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
+**	...
+*/
 float16x8_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+float16x8_t
+foo1 ()
+{
+  return vcreateq_f16 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c
@@ -1,13 +1,42 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
+**	...
+*/
 float32x4_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+float32x4_t
+foo1 ()
+{
+  return vcreateq_f32 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c
@@ -1,13 +1,42 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
+**	...
+*/
 int16x8_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+int16x8_t
+foo1 ()
+{
+  return vcreateq_s16 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c
@@ -1,13 +1,42 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
+**	...
+*/
 int32x4_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+int32x4_t
+foo1 ()
+{
+  return vcreateq_s32 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c
@@ -1,13 +1,42 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
+**	...
+*/
 int64x2_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_s64 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+int64x2_t
+foo1 ()
+{
+  return vcreateq_s64 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c
@@ -1,13 +1,42 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
+**	...
+*/
 int8x16_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+int8x16_t
+foo1 ()
+{
+  return vcreateq_s8 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c
@@ -1,13 +1,42 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
+**	...
+*/
 uint16x8_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+uint16x8_t
+foo1 ()
+{
+  return vcreateq_u16 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c
@@ -1,13 +1,42 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
+**	...
+*/
 uint32x4_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+uint32x4_t
+foo1 ()
+{
+  return vcreateq_u32 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c
@@ -1,13 +1,42 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
+**	...
+*/
 uint64x2_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_u64 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+uint64x2_t
+foo1 ()
+{
+  return vcreateq_u64 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c
@@ -1,13 +1,42 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r0, r2
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r1, r3
+**	...
+*/
 uint8x16_t
 foo (uint64_t a, uint64_t b)
 {
   return vcreateq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmov"  }  } */
+/*
+**foo1:
+**	...
+**	vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+]
+**	vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+]
+**	...
+*/
+uint8x16_t
+foo1 ()
+{
+  return vcreateq_u8 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
@@ -1,21 +1,44 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vctp.16	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a)
 {
   return vctp16q (a);
 }
 
-/* { dg-final { scan-assembler "vctp.16"  }  } */
-
+/*
+**foo1:
+**	...
+**	vctp.16	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
 {
-  return vctp16q (a);
+  return vctp16q (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vctp.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c
@@ -1,22 +1,52 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.16	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vctp16q_m (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.16"  }  } */
-
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.16	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
 {
-  return vctp16q_m (a, p);
+  return vctp16q_m (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
@@ -1,21 +1,44 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vctp.32	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a)
 {
   return vctp32q (a);
 }
 
-/* { dg-final { scan-assembler "vctp.32"  }  } */
-
+/*
+**foo1:
+**	...
+**	vctp.32	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
 {
-  return vctp32q (a);
+  return vctp32q (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vctp.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c
@@ -1,22 +1,52 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.32	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vctp32q_m (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.32"  }  } */
-
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.32	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
 {
-  return vctp32q_m (a, p);
+  return vctp32q_m (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
@@ -1,21 +1,44 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vctp.64	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a)
 {
   return vctp64q (a);
 }
 
-/* { dg-final { scan-assembler "vctp.64"  }  } */
-
+/*
+**foo1:
+**	...
+**	vctp.64	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
 {
-  return vctp64q (a);
+  return vctp64q (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vctp.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c
@@ -1,22 +1,52 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.64	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vctp64q_m (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.64"  }  } */
-
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.64	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
 {
-  return vctp64q_m (a, p);
+  return vctp64q_m (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
@@ -1,21 +1,44 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vctp.8	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a)
 {
   return vctp8q (a);
 }
 
-/* { dg-final { scan-assembler "vctp.8"  }  } */
-
+/*
+**foo1:
+**	...
+**	vctp.8	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a)
+foo1 ()
 {
-  return vctp8q (a);
+  return vctp8q (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vctp.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c
@@ -1,22 +1,52 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.8	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vctp8q_m (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vctpt.8"  }  } */
-
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vctpt.8	(?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
-foo1 (uint32_t a, mve_pred16_t p)
+foo1 (mve_pred16_t p)
 {
-  return vctp8q_m (a, p);
+  return vctp8q_m (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtaq_m_s16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtaq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtaq_m_s32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtaq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtaq_m_u16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtaq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtaq_m_u32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtaq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvta.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a)
 {
   return vcvtaq_s16_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvta.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvta.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a)
 {
   return vcvtaq_s32_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvta.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvta.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a)
 {
-    return vcvtaq_u16_f16 (a);
+  return vcvtaq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvta.u16.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvta.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a)
 {
-    return vcvtaq_u32_f32 (a);
+  return vcvtaq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvta.u32.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtaq_x_s16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtaq_x_s32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtaq_x_u16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtat.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtaq_x_u32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtat.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtb.f16.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float32x4_t b)
 {
   return vcvtbq_f16_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcvtb.f16.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtb.f32.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float16x8_t a)
 {
   return vcvtbq_f32_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtb.f32.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c
@@ -1,22 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtbt.f16.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcvtbq_m_f16_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtbt.f16.f32"  }  } */
-
-float16x8_t
-foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p)
-{
-  return vcvtbq_m (a, b, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c
@@ -1,22 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtbt.f32.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtbq_m_f32_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtbt.f32.f16"  }  } */
-
-float32x4_t
-foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
-{
-  return vcvtbq_m (inactive, a, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtbt.f32.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtbq_x_f32_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtbt.f32.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtmq_m_s16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtmq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtmq_m_s32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtmq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtmq_m_u16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtmq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtmq_m_u32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtmq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtm.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a)
 {
   return vcvtmq_s16_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtm.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtm.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a)
 {
   return vcvtmq_s32_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtm.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtm.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a)
 {
-    return vcvtmq_u16_f16 (a);
+  return vcvtmq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvtm.u16.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtm.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a)
 {
-    return vcvtmq_u32_f32 (a);
+  return vcvtmq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvtm.u32.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtmq_x_s16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtmq_x_s32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtmq_x_u16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtmt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtmq_x_u32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtmt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtnq_m_s16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtnq_m_s32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtnq_m_u16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtnq_m_u32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtn.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a)
 {
   return vcvtnq_s16_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtn.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtn.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a)
 {
   return vcvtnq_s32_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtn.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtn.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a)
 {
-    return vcvtnq_u16_f16 (a);
+  return vcvtnq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvtn.u16.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtn.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a)
 {
   return vcvtnq_u32_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtn.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtnq_x_s16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtnq_x_s32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtnq_x_u16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtnt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtnq_x_u32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtnt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtpq_m_s16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtpq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtpq_m_s32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtpq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtpq_m_u16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtpq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtpq_m_u32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtpq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtp.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a)
 {
   return vcvtpq_s16_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtp.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtp.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a)
 {
   return vcvtpq_s32_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtp.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtp.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a)
 {
-    return vcvtpq_u16_f16 (a);
+  return vcvtpq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvtp.u16.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtp.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a)
 {
-    return vcvtpq_u32_f32 (a);
+  return vcvtpq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvtp.u32.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtpq_x_s16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtpq_x_s32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtpq_x_u16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtpt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtpq_x_u32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtpt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f16.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (int16x8_t a)
 {
   return vcvtq_f16_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvt.f16.s16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vcvt.f16.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (int16x8_t a)
+{
+  return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f16.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (uint16x8_t a)
 {
   return vcvtq_f16_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvt.f16.u16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vcvt.f16.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (uint16x8_t a)
+{
+  return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f32.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (int32x4_t a)
 {
   return vcvtq_f32_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvt.f32.s32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vcvt.f32.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (int32x4_t a)
+{
+  return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f32.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (uint32x4_t a)
 {
   return vcvtq_f32_u32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvt.f32.u32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vcvt.f32.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (uint32x4_t a)
+{
+  return vcvtq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_f16_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_f16_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_f32_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_f32_u32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_f16_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_f16_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_f32_s32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
-  return vcvtq_m_n_f32_u32 (inactive, a, 16, p);
+  return vcvtq_m_n_f32_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
-  return vcvtq_m_n (inactive, a, 16, p);
+  return vcvtq_m_n (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_s16_f16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_s32_f32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_u16_f16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_n_u32_f32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_s16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_s32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m_u16_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m_u32_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f16.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (int16x8_t a)
 {
   return vcvtq_n_f16_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f16.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcvt.f16.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (int16x8_t a)
 {
   return vcvtq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f16.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f16.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (uint16x8_t a)
 {
   return vcvtq_n_f16_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f16.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcvt.f16.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (uint16x8_t a)
 {
   return vcvtq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f16.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f32.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (int32x4_t a)
 {
   return vcvtq_n_f32_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f32.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcvt.f32.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (int32x4_t a)
 {
   return vcvtq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f32.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.f32.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (uint32x4_t a)
 {
   return vcvtq_n_f32_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f32.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vcvt.f32.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (uint32x4_t a)
 {
   return vcvtq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.f32.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.s16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a)
 {
   return vcvtq_n_s16_f16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.s32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a)
 {
   return vcvtq_n_s32_f32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.u16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a)
 {
   return vcvtq_n_u16_f16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.u32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a)
 {
   return vcvtq_n_u32_f32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vcvt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a)
 {
   return vcvtq_s16_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a)
 {
   return vcvtq_s32_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vcvt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a)
 {
-    return vcvtq_u16_f16 (a);
+  return vcvtq_u16_f16 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvt.u16.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a)
 {
-    return vcvtq_u32_f32 (a);
+  return vcvtq_u32_f32 (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vcvt.u32.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_f16_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_f16_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_f32_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_f32_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_f16_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_f16_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f16.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f16.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_f32_s32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
-  return vcvtq_x_n_f32_u32 (a, 16, p);
+  return vcvtq_x_n_f32_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.f32.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
-  return vcvtq_x_n (a, 16, p);
+  return vcvtq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.f32.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_s16_f16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_s32_f32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u16.f16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_u16_f16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u32.f32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_n_u32_f32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_s16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.s32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_s32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.s32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u16.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvtq_x_u16_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u16.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvtt.u32.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vcvtq_x_u32_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvtt.u32.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtt.f16.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float32x4_t b)
 {
   return vcvttq_f16_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcvtt.f16.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vcvtt.f32.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float16x8_t a)
 {
   return vcvttq_f32_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vcvtt.f32.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c
@@ -1,22 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvttt.f16.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcvttq_m_f16_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvttt.f16.f32"  }  } */
-
-float16x8_t
-foo1 (float16x8_t a, float32x4_t b, mve_pred16_t p)
-{
-  return vcvttq_m (a, b, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c
@@ -1,22 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvttt.f32.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vcvttq_m_f32_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvttt.f32.f16"  }  } */
-
-float32x4_t
-foo1 (float32x4_t inactive, float16x8_t a, mve_pred16_t p)
-{
-  return vcvttq_m (inactive, a, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vcvttt.f32.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vcvttq_x_f32_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcvttt.f32.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vddupq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vddupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vddupq_m (inactive, 1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
 {
-  return vddupq_m_n_u32 (inactive, a, 4, p);
+  return vddupq_m_n_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
 {
-  return vddupq_m (inactive, a, 4, p);
+  return vddupq_m (inactive, a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vddupq_m (inactive, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t a, mve_pred16_t p)
 {
-  return vddupq_m_n_u8 (inactive, a, 4, p);
+  return vddupq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t a, mve_pred16_t p)
 {
-  return vddupq_m (inactive, a, 4, p);
+  return vddupq_m (inactive, a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vddupq_m (inactive, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t *a, mve_pred16_t p)
 {
   return vddupq_m_wb_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t *a, mve_pred16_t p)
 {
   return vddupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vddupq_m (inactive, 1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_m_wb_u32 (inactive, a, 4, p);
+  return vddupq_m_wb_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_m (inactive, a, 4, p);
+  return vddupq_m (inactive, a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vddupq_m (inactive, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_m_wb_u8 (inactive, a, 4, p);
+  return vddupq_m_wb_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_m (inactive, a, 4, p);
+  return vddupq_m (inactive, a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vddupq_m (inactive, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vddup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a)
 {
-  return vddupq_n_u16 (a, 4);
+  return vddupq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vddup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a)
 {
-  return vddupq_u16 (a, 4);
+  return vddupq_u16 (a, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vddup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return vddupq_u16 (1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vddup.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vddup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a)
 {
   return vddupq_n_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vddup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a)
 {
   return vddupq_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vddup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return vddupq_u32 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vddup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a)
 {
   return vddupq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vddup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a)
 {
   return vddupq_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vddup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return vddupq_u8 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vddup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t *a)
 {
-  return vddupq_wb_u16 (a, 4);
+  return vddupq_wb_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vddup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t *a)
 {
-  return vddupq_u16 (a, 4);
+  return vddupq_u16 (a, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vddup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return vddupq_u16 (1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vddup.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vddup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t *a)
 {
   return vddupq_wb_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vddup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t *a)
 {
   return vddupq_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vddup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return vddupq_u32 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vddup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t *a)
 {
   return vddupq_wb_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vddup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t *a)
 {
   return vddupq_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vddup.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vddup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return vddupq_u8 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vddupq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a, mve_pred16_t p)
 {
   return vddupq_x_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return vddupq_x_u16 (1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, mve_pred16_t p)
 {
-  return vddupq_x_n_u32 (a, 4, p);
+  return vddupq_x_n_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a, mve_pred16_t p)
 {
-  return vddupq_x_u32 (a, 4, p);
+  return vddupq_x_u32 (a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return vddupq_x_u32 (1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a, mve_pred16_t p)
 {
-  return vddupq_x_n_u8 (a, 4, p);
+  return vddupq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a, mve_pred16_t p)
 {
-  return vddupq_x_u8 (a, 4, p);
+  return vddupq_x_u8 (a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return vddupq_x_u8 (1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c
@@ -1,25 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint32_t *a;
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (mve_pred16_t p)
+foo (uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_x_wb_u16 (a, 2, p);
+  return vddupq_x_wb_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (mve_pred16_t p)
+foo1 (uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_x_u16 (a, 2, p);
+  return vddupq_x_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return vddupq_x_u16 (1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c
@@ -1,25 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint32_t *a;
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (mve_pred16_t p)
+foo (uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_x_wb_u32 (a, 8, p);
+  return vddupq_x_wb_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (mve_pred16_t p)
+foo1 (uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_x_u32 (a, 8, p);
+  return vddupq_x_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return vddupq_x_u32 (1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c
@@ -1,25 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint32_t *a;
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (mve_pred16_t p)
+foo (uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_x_wb_u8 (a, 8, p);
+  return vddupq_x_wb_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (mve_pred16_t p)
+foo1 (uint32_t *a, mve_pred16_t p)
 {
-  return vddupq_x_u8 (a, 8, p);
+  return vddupq_x_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vddupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vddupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return vddupq_x_u8 (1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c
@@ -1,22 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16_t a, mve_pred16_t p)
 {
   return vdupq_m_n_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t inactive, mve_pred16_t p)
+{
+  return vdupq_m (inactive, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c
@@ -1,22 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32_t a, mve_pred16_t p)
 {
   return vdupq_m_n_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t inactive, mve_pred16_t p)
+{
+  return vdupq_m (inactive, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16_t a, mve_pred16_t p)
 {
   return vdupq_m_n_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32_t a, mve_pred16_t p)
 {
   return vdupq_m_n_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8_t a, mve_pred16_t p)
 {
   return vdupq_m_n_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c
@@ -1,22 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16_t a, mve_pred16_t p)
 {
   return vdupq_m_n_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vdupq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c
@@ -1,22 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vdupq_m_n_u32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vdupq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c
@@ -1,22 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8_t a, mve_pred16_t p)
 {
   return vdupq_m_n_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8_t a, mve_pred16_t p)
 {
   return vdupq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vdupq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdup.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16_t a)
 {
   return vdupq_n_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vdup.16"  }  } */
+/*
+**foo1:
+**	...
+**	vdup.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 ()
+{
+  return vdupq_n_f16 (1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdup.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32_t a)
 {
   return vdupq_n_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vdup.32"  }  } */
+/*
+**foo1:
+**	...
+**	vdup.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 ()
+{
+  return vdupq_n_f32 (1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c
@@ -1,13 +1,28 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdup.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16_t a)
 {
   return vdupq_n_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vdup.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c
@@ -1,13 +1,28 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdup.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32_t a)
 {
   return vdupq_n_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vdup.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdup.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8_t a)
 {
   return vdupq_n_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vdup.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdup.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16_t a)
 {
-    return vdupq_n_u16 (a);
+  return vdupq_n_u16 (a);
+}
+
+/*
+**foo1:
+**	...
+**	vdup.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 ()
+{
+  return vdupq_n_u16 (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vdup.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdup.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a)
 {
-    return vdupq_n_u32 (a);
+  return vdupq_n_u32 (a);
+}
+
+/*
+**foo1:
+**	...
+**	vdup.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 ()
+{
+  return vdupq_n_u32 (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vdup.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c
@@ -1,13 +1,40 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdup.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8_t a)
 {
-    return vdupq_n_u8 (a);
+  return vdupq_n_u8 (a);
+}
+
+/*
+**foo1:
+**	...
+**	vdup.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 ()
+{
+  return vdupq_n_u8 (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vdup.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c
@@ -1,14 +1,48 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16_t a, mve_pred16_t p)
 {
   return vdupq_x_n_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16"  }  } */
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (mve_pred16_t p)
+{
+  return vdupq_x_n_f16 (1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c
@@ -1,14 +1,48 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32_t a, mve_pred16_t p)
 {
   return vdupq_x_n_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32"  }  } */
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (mve_pred16_t p)
+{
+  return vdupq_x_n_f32 (1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16_t a, mve_pred16_t p)
 {
   return vdupq_x_n_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32_t a, mve_pred16_t p)
 {
   return vdupq_x_n_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8_t a, mve_pred16_t p)
 {
   return vdupq_x_n_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c
@@ -1,14 +1,48 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16_t a, mve_pred16_t p)
 {
   return vdupq_x_n_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.16"  }  } */
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (mve_pred16_t p)
+{
+  return vdupq_x_n_u16 (1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c
@@ -1,14 +1,48 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vdupq_x_n_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.32"  }  } */
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (mve_pred16_t p)
+{
+  return vdupq_x_n_u32 (1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c
@@ -1,14 +1,48 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8_t a, mve_pred16_t p)
 {
   return vdupq_x_n_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdupt.8"  }  } */
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdupt.8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (mve_pred16_t p)
+{
+  return vdupq_x_n_u8 (1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 1, p);
+  return vdwdupq_m_n_u16 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
   return vdwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vdwdupq_m (inactive, 1, 1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 4, p);
+  return vdwdupq_m_n_u32 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 4, p);
+  return vdwdupq_m (inactive, a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vdwdupq_m (inactive, 1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 4, p);
+  return vdwdupq_m_n_u8 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 4, p);
+  return vdwdupq_m (inactive, a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vdwdupq_m (inactive, 1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 8, p);
+  return vdwdupq_m_wb_u16 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 8, p);
+  return vdwdupq_m (inactive, a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vdwdupq_m (inactive, 1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 1, p);
+  return vdwdupq_m_wb_u32 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
   return vdwdupq_m (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vdwdupq_m (inactive, 1, 1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 2, p);
+  return vdwdupq_m_wb_u8 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_m (inactive, a, b, 2, p);
+  return vdwdupq_m (inactive, a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vdwdupq_m (inactive, 1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a, uint32_t b)
 {
-  return vdwdupq_n_u16 (a, b, 2);
+  return vdwdupq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vdwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a, uint32_t b)
 {
-  return vdwdupq_u16 (a, b, 2);
+  return vdwdupq_u16 (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vdwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return vdwdupq_u16 (1, 1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vdwdup.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, uint32_t b)
 {
-  return vdwdupq_n_u32 (a, b, 8);
+  return vdwdupq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vdwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a, uint32_t b)
 {
-  return vdwdupq_u32 (a, b, 8);
+  return vdwdupq_u32 (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vdwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return vdwdupq_u32 (1, 1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vdwdup.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a, uint32_t b)
 {
-  return vdwdupq_n_u8 (a, b, 4);
+  return vdwdupq_n_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vdwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a, uint32_t b)
 {
-  return vdwdupq_u8 (a, b, 4);
+  return vdwdupq_u8 (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vdwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return vdwdupq_u8 (1, 1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vdwdup.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t *a, uint32_t b)
 {
-  return vdwdupq_wb_u16 (a, b, 2);
+  return vdwdupq_wb_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vdwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t *a, uint32_t b)
 {
-  return vdwdupq_u16 (a, b, 2);
+  return vdwdupq_u16 (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vdwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return vdwdupq_u16 (1, 1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vdwdup.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t *a, uint32_t b)
 {
-  return vdwdupq_wb_u32 (a, b, 8);
+  return vdwdupq_wb_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vdwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t *a, uint32_t b)
 {
-  return vdwdupq_u32 (a, b, 8);
+  return vdwdupq_u32 (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vdwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return vdwdupq_u32 (1, 1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vdwdup.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vdwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t *a, uint32_t b)
 {
-  return vdwdupq_wb_u8 (a, b, 4);
+  return vdwdupq_wb_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vdwdup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vdwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t *a, uint32_t b)
 {
-  return vdwdupq_u8 (a, b, 4);
+  return vdwdupq_u8 (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vdwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return vdwdupq_u8 (1, 1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vdwdup.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a, uint32_t b, mve_pred16_t p)
 {
   return vdwdupq_x_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a, uint32_t b, mve_pred16_t p)
 {
   return vdwdupq_x_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return vdwdupq_x_u16 (1, 1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_n_u32 (a, b, 4, p);
+  return vdwdupq_x_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_u32 (a, b, 4, p);
+  return vdwdupq_x_u32 (a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return vdwdupq_x_u32 (1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_n_u8 (a, b, 4, p);
+  return vdwdupq_x_n_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_u8 (a, b, 4, p);
+  return vdwdupq_x_u8 (a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return vdwdupq_x_u8 (1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_wb_u16 (a, b, 8, p);
+  return vdwdupq_x_wb_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_u16 (a, b, 8, p);
+  return vdwdupq_x_u16 (a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return vdwdupq_x_u16 (1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
   return vdwdupq_x_wb_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
   return vdwdupq_x_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return vdwdupq_x_u32 (1, 1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_wb_u8 (a, b, 2, p);
+  return vdwdupq_x_wb_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return vdwdupq_x_u8 (a, b, 2, p);
+  return vdwdupq_x_u8 (a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vdwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return vdwdupq_x_u8 (1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vdwdupt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return veorq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return veorq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return veorq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return veorq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return veorq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return veorq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return veorq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return veorq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return veorq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return veorq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return veorq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return veorq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return veorq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return veorq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return veorq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return veorq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return veorq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
 
+/*
+**foo1:
+**	...
+**	veor	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return veorq (a, b);
 }
 
-/* { dg-final { scan-assembler "veor"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return veorq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return veorq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return veorq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return veorq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return veorq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return veorq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return veorq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return veorq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	veort	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return veorq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "veort"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfma.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2)
 {
-  return vfmaq_f16 (a, b, c);
+  return vfmaq_f16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vfma.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfma.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2)
 {
-  return vfmaq (a, b, c);
+  return vfmaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfma.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfma.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2)
 {
-  return vfmaq_f32 (a, b, c);
+  return vfmaq_f32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vfma.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfma.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2)
 {
-  return vfmaq (a, b, c);
+  return vfmaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfma.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
 {
-  return vfmaq_m_f16 (a, b, c, p);
+  return vfmaq_m_f16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
 {
-  return vfmaq_m (a, b, c, p);
+  return vfmaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
 {
-  return vfmaq_m_f32 (a, b, c, p);
+  return vfmaq_m_f32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
 {
-  return vfmaq_m (a, b, c, p);
+  return vfmaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
-{
-  return vfmaq_m (a, b, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+foo (float16x8_t add, float16x8_t m1, float16_t m2, mve_pred16_t p)
 {
-  return vfmaq_m_n_f16 (a, b, c, p);
+  return vfmaq_m_n_f16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+foo1 (float16x8_t add, float16x8_t m1, float16_t m2, mve_pred16_t p)
 {
-  return vfmaq_m (a, b, c, p);
+  return vfmaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t add, float16x8_t m1, mve_pred16_t p)
+{
+  return vfmaq_m (add, m1, 1.1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
-{
-  return vfmaq_m (a, b, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+foo (float32x4_t add, float32x4_t m1, float32_t m2, mve_pred16_t p)
 {
-  return vfmaq_m_n_f32 (a, b, c, p);
+  return vfmaq_m_n_f32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+foo1 (float32x4_t add, float32x4_t m1, float32_t m2, mve_pred16_t p)
 {
-  return vfmaq_m (a, b, c, p);
+  return vfmaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmat.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t add, float32x4_t m1, mve_pred16_t p)
+{
+  return vfmaq_m (add, m1, 1.1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmat.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
-{
-  return vfmaq (a, b, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfma.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c)
+foo (float16x8_t add, float16x8_t m1, float16_t m2)
 {
-  return vfmaq_n_f16 (a, b, c);
+  return vfmaq_n_f16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vfma.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfma.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
+foo1 (float16x8_t add, float16x8_t m1, float16_t m2)
 {
-  return vfmaq (a, b, c);
+  return vfmaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vfma.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t add, float16x8_t m1)
+{
+  return vfmaq (add, m1, 1.1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfma.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
-{
-  return vfmaq (a, b, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfma.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c)
+foo (float32x4_t add, float32x4_t m1, float32_t m2)
 {
-  return vfmaq_n_f32 (a, b, c);
+  return vfmaq_n_f32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vfma.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfma.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
+foo1 (float32x4_t add, float32x4_t m1, float32_t m2)
 {
-  return vfmaq (a, b, c);
+  return vfmaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vfma.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t add, float32x4_t m1)
+{
+  return vfmaq (add, m1, 1.1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfma.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
-{
-  return vfmasq_m (a, b, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmast.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+foo (float16x8_t m1, float16x8_t m2, float16_t add, mve_pred16_t p)
 {
-  return vfmasq_m_n_f16 (a, b, c, p);
+  return vfmasq_m_n_f16 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmast.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmast.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c, mve_pred16_t p)
+foo1 (float16x8_t m1, float16x8_t m2, float16_t add, mve_pred16_t p)
 {
-  return vfmasq_m (a, b, c, p);
+  return vfmasq_m (m1, m2, add, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmast.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t m1, float16x8_t m2, mve_pred16_t p)
+{
+  return vfmasq_m (m1, m2, 1.1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmast.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
-{
-  return vfmasq_m (a, b, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmast.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+foo (float32x4_t m1, float32x4_t m2, float32_t add, mve_pred16_t p)
 {
-  return vfmasq_m_n_f32 (a, b, c, p);
+  return vfmasq_m_n_f32 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmast.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmast.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c, mve_pred16_t p)
+foo1 (float32x4_t m1, float32x4_t m2, float32_t add, mve_pred16_t p)
 {
-  return vfmasq_m (a, b, c, p);
+  return vfmasq_m (m1, m2, add, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmast.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t m1, float32x4_t m2, mve_pred16_t p)
+{
+  return vfmasq_m (m1, m2, 1.1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmast.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
-{
-  return vfmasq (a, b, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfmas.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16_t c)
+foo (float16x8_t m1, float16x8_t m2, float16_t add)
 {
-  return vfmasq_n_f16 (a, b, c);
+  return vfmasq_n_f16 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vfmas.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfmas.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16_t c)
+foo1 (float16x8_t m1, float16x8_t m2, float16_t add)
 {
-  return vfmasq (a, b, c);
+  return vfmasq (m1, m2, add);
+}
+
+/*
+**foo2:
+**	...
+**	vfmas.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t m1, float16x8_t m2)
+{
+  return vfmasq (m1, m2, 1.1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfmas.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
-{
-  return vfmasq (a, b, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfmas.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32_t c)
+foo (float32x4_t m1, float32x4_t m2, float32_t add)
 {
-  return vfmasq_n_f32 (a, b, c);
+  return vfmasq_n_f32 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vfmas.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfmas.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32_t c)
+foo1 (float32x4_t m1, float32x4_t m2, float32_t add)
 {
-  return vfmasq (a, b, c);
+  return vfmasq (m1, m2, add);
+}
+
+/*
+**foo2:
+**	...
+**	vfmas.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t m1, float32x4_t m2)
+{
+  return vfmasq (m1, m2, 1.1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfmas.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfms.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2)
 {
-  return vfmsq_f16 (a, b, c);
+  return vfmsq_f16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vfms.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfms.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2)
 {
-  return vfmsq (a, b, c);
+  return vfmsq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfms.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vfms.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2)
 {
-  return vfmsq_f32 (a, b, c);
+  return vfmsq_f32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vfms.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vfms.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2)
 {
-  return vfmsq (a, b, c);
+  return vfmsq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vfms.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmst.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
 {
-  return vfmsq_m_f16 (a, b, c, p);
+  return vfmsq_m_f16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmst.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16x8_t a, float16x8_t b, float16x8_t c, mve_pred16_t p)
+foo1 (float16x8_t add, float16x8_t m1, float16x8_t m2, mve_pred16_t p)
 {
-  return vfmsq_m (a, b, c, p);
+  return vfmsq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmst.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
 {
-  return vfmsq_m_f32 (a, b, c, p);
+  return vfmsq_m_f32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vfmst.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32x4_t a, float32x4_t b, float32x4_t c, mve_pred16_t p)
+foo1 (float32x4_t add, float32x4_t m1, float32x4_t m2, mve_pred16_t p)
 {
-  return vfmsq_m (a, b, c, p);
+  return vfmsq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vfmst.f32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhaddq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhaddq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhaddq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhaddq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vhaddq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhaddq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vhaddq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhaddq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vhaddq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhaddq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhaddq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhaddq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhaddq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhaddq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhaddq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhadd.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vhaddq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhadd.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vhaddq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhadd.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vhaddq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhadd.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vhaddq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vhadd.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vhaddq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhadd.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vhaddq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vhadd.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vhaddq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhadd.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vhaddq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vhadd.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vhaddq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhadd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vhaddq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhadd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vhaddq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhadd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vhaddq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhadd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vhaddq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhadd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vhaddq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhadd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vhaddq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhadd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhadd.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhaddq_x_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhaddq_x_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhaddq_x_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhaddq_x_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vhaddq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhaddq_x_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vhaddq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhaddq_x_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vhaddq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhaddq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhaddq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhaddq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhaddq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhaddq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhaddq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhcadd.s16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vhcaddq_rot270_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhcadd.s16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vhcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhcadd.s32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vhcaddq_rot270_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhcadd.s32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vhcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhcadd.s8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vhcaddq_rot270_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhcadd.s8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vhcaddq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #270(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhcadd.s16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vhcaddq_rot90_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhcadd.s16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vhcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhcadd.s32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vhcaddq_rot90_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhcadd.s32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vhcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhcadd.s8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vhcaddq_rot90_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhcadd.s8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vhcaddq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhcadd.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhcaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhcaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+, #90(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhcaddq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhsubq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhsubq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhsubq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhsubq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vhsubq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhsubq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vhsubq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhsubq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vhsubq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhsubq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhsubq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhsubq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhsubq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhsubq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhsubq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhsub.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vhsubq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhsub.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vhsubq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhsub.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vhsubq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhsub.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vhsubq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vhsub.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vhsubq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhsub.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vhsubq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vhsub.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vhsubq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhsub.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vhsubq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vhsub.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vhsubq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhsub.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vhsubq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhsub.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vhsubq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhsub.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vhsubq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhsub.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vhsubq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhsub.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vhsubq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vhsub.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vhsubq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vhsub.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vhsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vhsub.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhsubq_x_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhsubq_x_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhsubq_x_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhsubq_x_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vhsubq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhsubq_x_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vhsubq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhsubq_x_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vhsubq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhsubq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhsubq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhsubq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhsubq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhsubq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhsubq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vhsubt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vhsubt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vhsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t a, mve_pred16_t p)
 {
-  return vidupq_m_n_u16 (inactive, a, 4, p);
+  return vidupq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t a, mve_pred16_t p)
 {
-  return vidupq_m (inactive, a, 4, p);
+  return vidupq_m (inactive, a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vidupq_m (inactive, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vidupq_m_n_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vidupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vidupq_m (inactive, 1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vidupq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t a, mve_pred16_t p)
 {
   return vidupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vidupq_m (inactive, 1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t *a, mve_pred16_t p)
 {
-  return vidupq_m_wb_u16 (inactive, a, 4, p);
+  return vidupq_m_wb_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t *a, mve_pred16_t p)
 {
-  return vidupq_m (inactive, a, 4, p);
+  return vidupq_m (inactive, a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return vidupq_m (inactive, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t *a, mve_pred16_t p)
 {
   return vidupq_m_wb_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t *a, mve_pred16_t p)
 {
   return vidupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return vidupq_m (inactive, 1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t *a, mve_pred16_t p)
 {
   return vidupq_m_wb_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t *a, mve_pred16_t p)
 {
   return vidupq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return vidupq_m (inactive, 1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vidup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a)
 {
-  return vidupq_n_u16 (a, 4);
+  return vidupq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vidup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a)
 {
-  return vidupq_u16 (a, 4);
+  return vidupq_u16 (a, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vidup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return vidupq_u16 (1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vidup.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vidup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a)
 {
   return vidupq_n_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vidup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a)
 {
   return vidupq_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vidup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return vidupq_u32 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vidup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a)
 {
   return vidupq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vidup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a)
 {
   return vidupq_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vidup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return vidupq_u8 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vidup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t *a)
 {
-  return vidupq_wb_u16 (a, 4);
+  return vidupq_wb_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vidup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t *a)
 {
-  return vidupq_u16 (a, 4);
+  return vidupq_u16 (a, 1);
+}
+
+/*
+**foo2:
+**	...
+**	vidup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return vidupq_u16 (1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vidup.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vidup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t *a)
 {
   return vidupq_wb_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vidup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t *a)
 {
   return vidupq_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vidup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return vidupq_u32 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vidup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t *a)
 {
   return vidupq_wb_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vidup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t *a)
 {
   return vidupq_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vidup.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vidup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return vidupq_u8 (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a, mve_pred16_t p)
 {
-  return vidupq_x_n_u16 (a, 4, p);
+  return vidupq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a, mve_pred16_t p)
 {
-  return vidupq_x_u16 (a, 4, p);
+  return vidupq_x_u16 (a, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return vidupq_x_u16 (1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vidupq_x_n_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a, mve_pred16_t p)
 {
   return vidupq_x_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return vidupq_x_u32 (1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a, mve_pred16_t p)
 {
   return vidupq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a, mve_pred16_t p)
 {
   return vidupq_x_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return vidupq_x_u8 (1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c
@@ -1,25 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint32_t *a;
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (mve_pred16_t p)
+foo (uint32_t *a, mve_pred16_t p)
 {
-  return vidupq_x_wb_u16 (a, 8, p);
+  return vidupq_x_wb_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (mve_pred16_t p)
+foo1 (uint32_t *a, mve_pred16_t p)
 {
-  return vidupq_x_u16 (a, 8, p);
+  return vidupq_x_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return vidupq_x_u16 (1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c
@@ -1,25 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint32_t *a;
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (mve_pred16_t p)
+foo (uint32_t *a, mve_pred16_t p)
 {
-  return vidupq_x_wb_u32 (a, 2, p);
+  return vidupq_x_wb_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (mve_pred16_t p)
+foo1 (uint32_t *a, mve_pred16_t p)
 {
-  return vidupq_x_u32 (a, 2, p);
+  return vidupq_x_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return vidupq_x_u32 (1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c
@@ -1,25 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-uint32_t * a;
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (mve_pred16_t p)
+foo (uint32_t *a, mve_pred16_t p)
 {
-  return vidupq_x_wb_u8 (a, 2, p);
+  return vidupq_x_wb_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (mve_pred16_t p)
+foo1 (uint32_t *a, mve_pred16_t p)
 {
-  return vidupq_x_u8 (a, 2, p);
+  return vidupq_x_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vidupt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vidupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return vidupq_x_u8 (1, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m_n_u16 (inactive, a, b, 2, p);
+  return viwdupq_m_n_u16 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m (inactive, a, b, 2, p);
+  return viwdupq_m (inactive, a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return viwdupq_m (inactive, 1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m_n_u32 (inactive, a, b, 4, p);
+  return viwdupq_m_n_u32 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m (inactive, a, b, 4, p);
+  return viwdupq_m (inactive, a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return viwdupq_m (inactive, 1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m_n_u8 (inactive, a, b, 8, p);
+  return viwdupq_m_n_u8 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m (inactive, a, b, 8, p);
+  return viwdupq_m (inactive, a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return viwdupq_m (inactive, 1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m_wb_u16 (inactive, a, b, 2, p);
+  return viwdupq_m_wb_u16 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m (inactive, a, b, 2, p);
+  return viwdupq_m (inactive, a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, mve_pred16_t p)
+{
+  return viwdupq_m (inactive, 1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m_wb_u32 (inactive, a, b, 4, p);
+  return viwdupq_m_wb_u32 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m (inactive, a, b, 4, p);
+  return viwdupq_m (inactive, a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, mve_pred16_t p)
+{
+  return viwdupq_m (inactive, 1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m_wb_u8 (inactive, a, b, 8, p);
+  return viwdupq_m_wb_u8 (inactive, a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_m (inactive, a, b, 8, p);
+  return viwdupq_m (inactive, a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, mve_pred16_t p)
+{
+  return viwdupq_m (inactive, 1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	viwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a, uint32_t b)
 {
-  return viwdupq_n_u16 (a, b, 2);
+  return viwdupq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	viwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a, uint32_t b)
 {
-  return viwdupq_u16 (a, b, 2);
+  return viwdupq_u16 (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	viwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return viwdupq_u16 (1, 1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "viwdup.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	viwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, uint32_t b)
 {
-  return viwdupq_n_u32 (a, b, 4);
+  return viwdupq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	viwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a, uint32_t b)
 {
-  return viwdupq_u32 (a, b, 4);
+  return viwdupq_u32 (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	viwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return viwdupq_u32 (1, 1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "viwdup.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	viwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a, uint32_t b)
 {
   return viwdupq_n_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	viwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a, uint32_t b)
 {
   return viwdupq_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u8"  }  } */
+/*
+**foo2:
+**	...
+**	viwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return viwdupq_u8 (1, 1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	viwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint32_t * a, uint32_t b)
+foo (uint32_t *a, uint32_t b)
 {
-  return viwdupq_wb_u16 (a, b, 4);
+  return viwdupq_wb_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	viwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint32_t * a, uint32_t b)
+foo1 (uint32_t *a, uint32_t b)
 {
-  return viwdupq_u16 (a, b, 4);
+  return viwdupq_u16 (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	viwdup.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 ()
+{
+  return viwdupq_u16 (1, 1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "viwdup.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	viwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t * a, uint32_t b)
+foo (uint32_t *a, uint32_t b)
 {
-  return viwdupq_wb_u32 (a, b, 8);
+  return viwdupq_wb_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	viwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t * a, uint32_t b)
+foo1 (uint32_t *a, uint32_t b)
 {
-  return viwdupq_u32 (a, b, 8);
+  return viwdupq_u32 (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	viwdup.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 ()
+{
+  return viwdupq_u32 (1, 1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "viwdup.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	viwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint32_t * a, uint32_t b)
+foo (uint32_t *a, uint32_t b)
 {
-  return viwdupq_wb_u8 (a, b, 2);
+  return viwdupq_wb_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "viwdup.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	viwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint32_t * a, uint32_t b)
+foo1 (uint32_t *a, uint32_t b)
 {
-  return viwdupq_u8 (a, b, 2);
+  return viwdupq_u8 (a, b, 1);
+}
+
+/*
+**foo2:
+**	...
+**	viwdup.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 ()
+{
+  return viwdupq_u8 (1, 1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "viwdup.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_n_u16 (a, b, 2, p);
+  return viwdupq_x_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_u16 (a, b, 2, p);
+  return viwdupq_x_u16 (a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return viwdupq_x_u16 (1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_n_u32 (a, b, 4, p);
+  return viwdupq_x_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_u32 (a, b, 4, p);
+  return viwdupq_x_u32 (a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return viwdupq_x_u32 (1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_n_u8 (a, b, 8, p);
+  return viwdupq_x_n_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint32_t a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_u8 (a, b, 8, p);
+  return viwdupq_x_u8 (a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return viwdupq_x_u8 (1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_wb_u16 (a, b, 8, p);
+  return viwdupq_x_wb_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_u16 (a, b, 8, p);
+  return viwdupq_x_u16 (a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u16	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (mve_pred16_t p)
+{
+  return viwdupq_x_u16 (1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_wb_u32 (a, b, 2, p);
+  return viwdupq_x_wb_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_u32 (a, b, 2, p);
+  return viwdupq_x_u32 (a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u32	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (mve_pred16_t p)
+{
+  return viwdupq_x_u32 (1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_wb_u8 (a, b, 4, p);
+  return viwdupq_x_wb_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint32_t * a, uint32_t b, mve_pred16_t p)
+foo1 (uint32_t *a, uint32_t b, mve_pred16_t p)
 {
-  return viwdupq_x_u8 (a, b, 4, p);
+  return viwdupq_x_u8 (a, b, 1, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	viwdupt.u8	q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (mve_pred16_t p)
+{
+  return viwdupq_x_u8 (1, 1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "viwdupt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base)
+foo (float16_t const *base)
 {
   return vld1q_f16 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16_t const * base)
+foo1 (float16_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.16" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base)
+foo (float32_t const *base)
 {
   return vld1q_f32 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32_t const * base)
+foo1 (float32_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrw.32" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base)
+foo (int16_t const *base)
 {
   return vld1q_s16 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16_t const * base)
+foo1 (int16_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.16" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base)
+foo (int32_t const *base)
 {
   return vld1q_s32 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32_t const * base)
+foo1 (int32_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrw.32" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8_t const * base)
+foo (int8_t const *base)
 {
   return vld1q_s8 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8_t const * base)
+foo1 (int8_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrb.8" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base)
+foo (uint16_t const *base)
 {
   return vld1q_u16 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16_t const * base)
+foo1 (uint16_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.16" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base)
+foo (uint32_t const *base)
 {
   return vld1q_u32 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t const * base)
+foo1 (uint32_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrw.32" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c
@@ -1,20 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8_t const * base)
+foo (uint8_t const *base)
 {
   return vld1q_u8 (base);
 }
 
+
+/*
+**foo1:
+**	...
+**	vldrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8_t const * base)
+foo1 (uint8_t const *base)
 {
   return vld1q (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrb.8" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base, mve_pred16_t p)
+foo (float16_t const *base, mve_pred16_t p)
 {
   return vld1q_z_f16 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16_t const * base, mve_pred16_t p)
+foo1 (float16_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrht.16" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base, mve_pred16_t p)
+foo (float32_t const *base, mve_pred16_t p)
 {
   return vld1q_z_f32 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32_t const * base, mve_pred16_t p)
+foo1 (float32_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base, mve_pred16_t p)
+foo (int16_t const *base, mve_pred16_t p)
 {
   return vld1q_z_s16 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16_t const * base, mve_pred16_t p)
+foo1 (int16_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrht.16" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base, mve_pred16_t p)
+foo (int32_t const *base, mve_pred16_t p)
 {
   return vld1q_z_s32 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32_t const * base, mve_pred16_t p)
+foo1 (int32_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8_t const * base, mve_pred16_t p)
+foo (int8_t const *base, mve_pred16_t p)
 {
   return vld1q_z_s8 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8_t const * base, mve_pred16_t p)
+foo1 (int8_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrbt.8" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base, mve_pred16_t p)
+foo (uint16_t const *base, mve_pred16_t p)
 {
   return vld1q_z_u16 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16_t const * base, mve_pred16_t p)
+foo1 (uint16_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrht.16" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base, mve_pred16_t p)
+foo (uint32_t const *base, mve_pred16_t p)
 {
   return vld1q_z_u32 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t const * base, mve_pred16_t p)
+foo1 (uint32_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8_t const * base, mve_pred16_t p)
+foo (uint8_t const *base, mve_pred16_t p)
 {
   return vld1q_z_u8 (base, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8_t const * base, mve_pred16_t p)
+foo1 (uint8_t const *base, mve_pred16_t p)
 {
   return vld1q_z (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 2 }  } */
-/* { dg-final { scan-assembler-times "vldrbt.8" 2 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8x2_t
-foo (float16_t const * addr)
+foo (float16_t const *addr)
 {
   return vld2q_f16 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.16"  }  } */
-/* { dg-final { scan-assembler "vld21.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8x2_t
-foo1 (float16_t const * addr)
+foo1 (float16_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4x2_t
-foo (float32_t const * addr)
+foo (float32_t const *addr)
 {
   return vld2q_f32 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.32"  }  } */
-/* { dg-final { scan-assembler "vld21.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4x2_t
-foo1 (float32_t const * addr)
+foo1 (float32_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8x2_t
-foo (int16_t const * addr)
+foo (int16_t const *addr)
 {
   return vld2q_s16 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.16"  }  } */
-/* { dg-final { scan-assembler "vld21.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8x2_t
-foo1 (int16_t const * addr)
+foo1 (int16_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4x2_t
-foo (int32_t const * addr)
+foo (int32_t const *addr)
 {
   return vld2q_s32 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.32"  }  } */
-/* { dg-final { scan-assembler "vld21.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4x2_t
-foo1 (int32_t const * addr)
+foo1 (int32_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16x2_t
-foo (int8_t const * addr)
+foo (int8_t const *addr)
 {
   return vld2q_s8 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.8"  }  } */
-/* { dg-final { scan-assembler "vld21.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16x2_t
-foo1 (int8_t const * addr)
+foo1 (int8_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8x2_t
-foo (uint16_t const * addr)
+foo (uint16_t const *addr)
 {
   return vld2q_u16 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.16"  }  } */
-/* { dg-final { scan-assembler "vld21.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8x2_t
-foo1 (uint16_t const * addr)
+foo1 (uint16_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4x2_t
-foo (uint32_t const * addr)
+foo (uint32_t const *addr)
 {
   return vld2q_u32 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.32"  }  } */
-/* { dg-final { scan-assembler "vld21.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4x2_t
-foo1 (uint32_t const * addr)
+foo1 (uint32_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16x2_t
-foo (uint8_t const * addr)
+foo (uint8_t const *addr)
 {
   return vld2q_u8 (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.8"  }  } */
-/* { dg-final { scan-assembler "vld21.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vld21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16x2_t
-foo1 (uint8_t const * addr)
+foo1 (uint8_t const *addr)
 {
   return vld2q (addr);
 }
 
-/* { dg-final { scan-assembler "vld20.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 float16x8x4_t
-foo (float16_t const * addr)
+foo (float16_t const *addr)
 {
   return vld4q_f16 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.16"  }  } */
-/* { dg-final { scan-assembler "vld41.16"  }  } */
-/* { dg-final { scan-assembler "vld42.16"  }  } */
-/* { dg-final { scan-assembler "vld43.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 float16x8x4_t
-foo1 (float16_t const * addr)
+foo1 (float16_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 float32x4x4_t
-foo (float32_t const * addr)
+foo (float32_t const *addr)
 {
   return vld4q_f32 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.32"  }  } */
-/* { dg-final { scan-assembler "vld41.32"  }  } */
-/* { dg-final { scan-assembler "vld42.32"  }  } */
-/* { dg-final { scan-assembler "vld43.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 float32x4x4_t
-foo1 (float32_t const * addr)
+foo1 (float32_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 int16x8x4_t
-foo (int16_t const * addr)
+foo (int16_t const *addr)
 {
   return vld4q_s16 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.16"  }  } */
-/* { dg-final { scan-assembler "vld41.16"  }  } */
-/* { dg-final { scan-assembler "vld42.16"  }  } */
-/* { dg-final { scan-assembler "vld43.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 int16x8x4_t
-foo1 (int16_t const * addr)
+foo1 (int16_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 int32x4x4_t
-foo (int32_t const * addr)
+foo (int32_t const *addr)
 {
   return vld4q_s32 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.32"  }  } */
-/* { dg-final { scan-assembler "vld41.32"  }  } */
-/* { dg-final { scan-assembler "vld42.32"  }  } */
-/* { dg-final { scan-assembler "vld43.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 int32x4x4_t
-foo1 (int32_t const * addr)
+foo1 (int32_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 int8x16x4_t
-foo (int8_t const * addr)
+foo (int8_t const *addr)
 {
   return vld4q_s8 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.8"  }  } */
-/* { dg-final { scan-assembler "vld41.8"  }  } */
-/* { dg-final { scan-assembler "vld42.8"  }  } */
-/* { dg-final { scan-assembler "vld43.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 int8x16x4_t
-foo1 (int8_t const * addr)
+foo1 (int8_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 uint16x8x4_t
-foo (uint16_t const * addr)
+foo (uint16_t const *addr)
 {
   return vld4q_u16 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.16"  }  } */
-/* { dg-final { scan-assembler "vld41.16"  }  } */
-/* { dg-final { scan-assembler "vld42.16"  }  } */
-/* { dg-final { scan-assembler "vld43.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 uint16x8x4_t
-foo1 (uint16_t const * addr)
+foo1 (uint16_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 uint32x4x4_t
-foo (uint32_t const * addr)
+foo (uint32_t const *addr)
 {
   return vld4q_u32 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.32"  }  } */
-/* { dg-final { scan-assembler "vld41.32"  }  } */
-/* { dg-final { scan-assembler "vld42.32"  }  } */
-/* { dg-final { scan-assembler "vld43.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 uint32x4x4_t
-foo1 (uint32_t const * addr)
+foo1 (uint32_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c
@@ -1,24 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vld40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 uint8x16x4_t
-foo (uint8_t const * addr)
+foo (uint8_t const *addr)
 {
   return vld4q_u8 (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.8"  }  } */
-/* { dg-final { scan-assembler "vld41.8"  }  } */
-/* { dg-final { scan-assembler "vld42.8"  }  } */
-/* { dg-final { scan-assembler "vld43.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vld40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vld43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 uint8x16x4_t
-foo1 (uint8_t const * addr)
+foo1 (uint8_t const *addr)
 {
   return vld4q (addr);
 }
 
-/* { dg-final { scan-assembler "vld40.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.s16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int8_t const * base, uint16x8_t offset)
+foo (int8_t const *base, uint16x8_t offset)
 {
   return vldrbq_gather_offset_s16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrb.s16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int8_t const * base, uint16x8_t offset)
+foo1 (int8_t const *base, uint16x8_t offset)
 {
   return vldrbq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int8_t const * base, uint32x4_t offset)
+foo (int8_t const *base, uint32x4_t offset)
 {
   return vldrbq_gather_offset_s32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrb.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int8_t const * base, uint32x4_t offset)
+foo1 (int8_t const *base, uint32x4_t offset)
 {
   return vldrbq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8_t const * base, uint8x16_t offset)
+foo (int8_t const *base, uint8x16_t offset)
 {
   return vldrbq_gather_offset_s8 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrb.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8_t const * base, uint8x16_t offset)
+foo1 (int8_t const *base, uint8x16_t offset)
 {
   return vldrbq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint8_t const * base, uint16x8_t offset)
+foo (uint8_t const *base, uint16x8_t offset)
 {
   return vldrbq_gather_offset_u16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrb.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint8_t const * base, uint16x8_t offset)
+foo1 (uint8_t const *base, uint16x8_t offset)
 {
   return vldrbq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint8_t const * base, uint32x4_t offset)
+foo (uint8_t const *base, uint32x4_t offset)
 {
   return vldrbq_gather_offset_u32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrb.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint8_t const * base, uint32x4_t offset)
+foo1 (uint8_t const *base, uint32x4_t offset)
 {
   return vldrbq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8_t const * base, uint8x16_t offset)
+foo (uint8_t const *base, uint8x16_t offset)
 {
   return vldrbq_gather_offset_u8 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrb.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8_t const * base, uint8x16_t offset)
+foo1 (uint8_t const *base, uint8x16_t offset)
 {
   return vldrbq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrb.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.s16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int8_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (int8_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z_s16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.s16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int8_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (int8_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int8_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int8_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z_s32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int8_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int8_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8_t const * base, uint8x16_t offset, mve_pred16_t p)
+foo (int8_t const *base, uint8x16_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z_s8 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8_t const * base, uint8x16_t offset, mve_pred16_t p)
+foo1 (int8_t const *base, uint8x16_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint8_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (uint8_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z_u16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint8_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (uint8_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint8_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint8_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z_u32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint8_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint8_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8_t const * base, uint8x16_t offset, mve_pred16_t p)
+foo (uint8_t const *base, uint8x16_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z_u8 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8_t const * base, uint8x16_t offset, mve_pred16_t p)
+foo1 (uint8_t const *base, uint8x16_t offset, mve_pred16_t p)
 {
   return vldrbq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.s16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int8_t const * base)
+foo (int8_t const *base)
 {
   return vldrbq_s16 (base);
 }
 
-/* { dg-final { scan-assembler "vldrb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int8_t const * base)
+foo (int8_t const *base)
 {
   return vldrbq_s32 (base);
 }
 
-/* { dg-final { scan-assembler "vldrb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8_t const * base)
+foo (int8_t const *base)
 {
   return vldrbq_s8 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrb.8" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint8_t const * base)
+foo (uint8_t const *base)
 {
   return vldrbq_u16 (base);
 }
 
-/* { dg-final { scan-assembler "vldrb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint8_t const * base)
+foo (uint8_t const *base)
 {
   return vldrbq_u32 (base);
 }
 
-/* { dg-final { scan-assembler "vldrb.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8_t const * base)
+foo (uint8_t const *base)
 {
   return vldrbq_u8 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrb.8" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.s16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int8_t const * base, mve_pred16_t p)
+foo (int8_t const *base, mve_pred16_t p)
 {
   return vldrbq_z_s16 (base, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int8_t const * base, mve_pred16_t p)
+foo (int8_t const *base, mve_pred16_t p)
 {
   return vldrbq_z_s32 (base, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8_t const * base, mve_pred16_t p)
+foo (int8_t const *base, mve_pred16_t p)
 {
   return vldrbq_z_s8 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrbt.8" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint8_t const * base, mve_pred16_t p)
+foo (uint8_t const *base, mve_pred16_t p)
 {
   return vldrbq_z_u16 (base, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint8_t const * base, mve_pred16_t p)
+foo (uint8_t const *base, mve_pred16_t p)
 {
   return vldrbq_z_u32 (base, p);
 }
 
-/* { dg-final { scan-assembler "vldrbt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8_t const * base, mve_pred16_t p)
+foo (uint8_t const *base, mve_pred16_t p)
 {
   return vldrbq_z_u8 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrbt.8" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (uint64x2_t addr)
 {
-  return vldrdq_gather_base_s64 (addr, 8);
+  return vldrdq_gather_base_s64 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrd.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint64x2_t addr)
 {
-  return vldrdq_gather_base_u64 (addr, 8);
+  return vldrdq_gather_base_u64 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrd.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c
@@ -1,16 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 int64x2_t
-foo (uint64x2_t * addr)
+foo (uint64x2_t *addr)
 {
-  return vldrdq_gather_base_wb_s64 (addr, 8);
+  return vldrdq_gather_base_wb_s64 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c
@@ -1,16 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo (uint64x2_t * addr)
+foo (uint64x2_t *addr)
 {
-  return vldrdq_gather_base_wb_u64 (addr, 8);
+  return vldrdq_gather_base_wb_u64 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
 #include "arm_mve.h"
 
-int64x2_t foo (uint64x2_t * addr, mve_pred16_t p)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
+int64x2_t
+foo (uint64x2_t *addr, mve_pred16_t p)
 {
-    return vldrdq_gather_base_wb_z_s64 (addr, 1016, p);
+  return vldrdq_gather_base_wb_z_s64 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
 #include "arm_mve.h"
 
-uint64x2_t foo (uint64x2_t * addr, mve_pred16_t p)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
+uint64x2_t
+foo (uint64x2_t *addr, mve_pred16_t p)
 {
-    return vldrdq_gather_base_wb_z_u64 (addr, 8, p);
+  return vldrdq_gather_base_wb_z_u64 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
-/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (uint64x2_t addr, mve_pred16_t p)
 {
-  return vldrdq_gather_base_z_s64 (addr, 8, p);
+  return vldrdq_gather_base_z_s64 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint64x2_t addr, mve_pred16_t p)
 {
-  return vldrdq_gather_base_z_u64 (addr, 8, p);
+  return vldrdq_gather_base_z_u64 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo (int64_t const * base, uint64x2_t offset)
+foo (int64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_offset_s64 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo1 (int64_t const * base, uint64x2_t offset)
+foo1 (int64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo (uint64_t const * base, uint64x2_t offset)
+foo (uint64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_offset_u64 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo1 (uint64_t const * base, uint64x2_t offset)
+foo1 (uint64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_s64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_offset_z_s64 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_z_u64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_offset_z_u64 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_s64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo (int64_t const * base, uint64x2_t offset)
+foo (int64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_shifted_offset_s64 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo1 (int64_t const * base, uint64x2_t offset)
+foo1 (int64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_u64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo (uint64_t const * base, uint64x2_t offset)
+foo (uint64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_shifted_offset_u64 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrd.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo1 (uint64_t const * base, uint64x2_t offset)
+foo1 (uint64_t const *base, uint64x2_t offset)
 {
   return vldrdq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrd.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_s64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_shifted_offset_z_s64 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 int64x2_t
-foo1 (int64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo1 (int64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shifted_offset_z_u64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_shifted_offset_z_u64 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrdt.u64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 uint64x2_t
-foo1 (uint64_t const * base, uint64x2_t offset, mve_pred16_t p)
+foo1 (uint64_t const *base, uint64x2_t offset, mve_pred16_t p)
 {
   return vldrdq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrdt.u64"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base)
+foo (float16_t const *base)
 {
   return vldrhq_f16 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.16" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base, uint16x8_t offset)
+foo (float16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_offset_f16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16_t const * base, uint16x8_t offset)
+foo1 (float16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base, uint16x8_t offset)
+foo (int16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_offset_s16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16_t const * base, uint16x8_t offset)
+foo1 (int16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int16_t const * base, uint32x4_t offset)
+foo (int16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_offset_s32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int16_t const * base, uint32x4_t offset)
+foo1 (int16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base, uint16x8_t offset)
+foo (uint16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_offset_u16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16_t const * base, uint16x8_t offset)
+foo1 (uint16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint16_t const * base, uint32x4_t offset)
+foo (uint16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_offset_u32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint16_t const * base, uint32x4_t offset)
+foo1 (uint16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z_f16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z_s16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z_s32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z_u16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z_u32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base, uint16x8_t offset)
+foo (float16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_shifted_offset_f16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16_t const * base, uint16x8_t offset)
+foo1 (float16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base, uint16x8_t offset)
+foo (int16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_shifted_offset_s16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16_t const * base, uint16x8_t offset)
+foo1 (int16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int16_t const * base, uint32x4_t offset)
+foo (int16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_shifted_offset_s32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int16_t const * base, uint32x4_t offset)
+foo1 (int16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base, uint16x8_t offset)
+foo (uint16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_shifted_offset_u16 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16_t const * base, uint16x8_t offset)
+foo1 (uint16_t const *base, uint16x8_t offset)
 {
   return vldrhq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint16_t const * base, uint32x4_t offset)
+foo (uint16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_shifted_offset_u32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrh.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint16_t const * base, uint32x4_t offset)
+foo1 (uint16_t const *base, uint32x4_t offset)
 {
   return vldrhq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrh.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z_f16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.f16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo1 (float16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (float16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z_s16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (int16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z_s32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z_u16 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p)
+foo1 (uint16_t const *base, uint16x8_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z_u32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint16_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrhq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrht.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base)
+foo (int16_t const *base)
 {
   return vldrhq_s16 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.16" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int16_t const * base)
+foo (int16_t const *base)
 {
   return vldrhq_s32 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.s32" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base)
+foo (uint16_t const *base)
 {
   return vldrhq_u16 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.16" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrh.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint16_t const * base)
+foo (uint16_t const *base)
 {
   return vldrhq_u32 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrh.u32" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float16x8_t
-foo (float16_t const * base, mve_pred16_t p)
+foo (float16_t const *base, mve_pred16_t p)
 {
   return vldrhq_z_f16 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrht.16" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16_t const * base, mve_pred16_t p)
+foo (int16_t const *base, mve_pred16_t p)
 {
   return vldrhq_z_s16 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrht.16" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.s32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int16_t const * base, mve_pred16_t p)
+foo (int16_t const *base, mve_pred16_t p)
 {
   return vldrhq_z_s32 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrht.s32" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16_t const * base, mve_pred16_t p)
+foo (uint16_t const *base, mve_pred16_t p)
 {
   return vldrhq_z_u16 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrht.16" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrht.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint16_t const * base, mve_pred16_t p)
+foo (uint16_t const *base, mve_pred16_t p)
 {
   return vldrhq_z_u32 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrht.u32" 1 }  } */
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base)
+foo (float32_t const *base)
 {
   return vldrwq_f32 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrw.32" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (uint32x4_t addr)
 {
-  return vldrwq_gather_base_f32 (addr, 4);
+  return vldrwq_gather_base_f32 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (uint32x4_t addr)
 {
-  return vldrwq_gather_base_s32 (addr, 4);
+  return vldrwq_gather_base_s32 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t addr)
 {
-  return vldrwq_gather_base_u32 (addr, 4);
+  return vldrwq_gather_base_u32 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c
@@ -1,16 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (uint32x4_t * addr)
+foo (uint32x4_t *addr)
 {
-  return vldrwq_gather_base_wb_f32 (addr, 8);
+  return vldrwq_gather_base_wb_f32 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c
@@ -1,16 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (uint32x4_t * addr)
+foo (uint32x4_t *addr)
 {
-  return vldrwq_gather_base_wb_s32 (addr, 8);
+  return vldrwq_gather_base_wb_s32 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c
@@ -1,16 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t * addr)
+foo (uint32x4_t *addr)
 {
-  return vldrwq_gather_base_wb_u32 (addr, 8);
+  return vldrwq_gather_base_wb_u32 (addr, 0);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
@@ -1,18 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (uint32x4_t * addr, mve_pred16_t p)
+foo (uint32x4_t *addr, mve_pred16_t p)
 {
-  return vldrwq_gather_base_wb_z_f32 (addr, 8, p);
+  return vldrwq_gather_base_wb_z_f32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
@@ -1,18 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (uint32x4_t * addr, mve_pred16_t p)
+foo (uint32x4_t *addr, mve_pred16_t p)
 {
-  return vldrwq_gather_base_wb_z_s32 (addr, 8, p);
+  return vldrwq_gather_base_wb_z_s32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
@@ -1,18 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t * addr, mve_pred16_t p)
+foo (uint32x4_t *addr, mve_pred16_t p)
 {
-  return vldrwq_gather_base_wb_z_u32 (addr, 8, p);
+  return vldrwq_gather_base_wb_z_u32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (uint32x4_t addr, mve_pred16_t p)
 {
-  return vldrwq_gather_base_z_f32 (addr, 4, p);
+  return vldrwq_gather_base_z_f32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (uint32x4_t addr, mve_pred16_t p)
 {
-  return vldrwq_gather_base_z_s32 (addr, 4, p);
+  return vldrwq_gather_base_z_s32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c
@@ -1,13 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t addr, mve_pred16_t p)
 {
-  return vldrwq_gather_base_z_u32 (addr, 4, p);
+  return vldrwq_gather_base_z_u32 (addr, 0, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base, uint32x4_t offset)
+foo (float32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_offset_f32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32_t const * base, uint32x4_t offset)
+foo1 (float32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base, uint32x4_t offset)
+foo (int32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_offset_s32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32_t const * base, uint32x4_t offset)
+foo1 (int32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base, uint32x4_t offset)
+foo (uint32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_offset_u32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t const * base, uint32x4_t offset)
+foo1 (uint32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_offset_z_f32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_offset_z_s32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_z_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_offset_z_u32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base, uint32x4_t offset)
+foo (float32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_shifted_offset_f32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32_t const * base, uint32x4_t offset)
+foo1 (float32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base, uint32x4_t offset)
+foo (int32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_shifted_offset_s32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32_t const * base, uint32x4_t offset)
+foo1 (int32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base, uint32x4_t offset)
+foo (uint32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_shifted_offset_u32 (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vldrw.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t const * base, uint32x4_t offset)
+foo1 (uint32_t const *base, uint32x4_t offset)
 {
   return vldrwq_gather_shifted_offset (base, offset);
 }
 
-/* { dg-final { scan-assembler "vldrw.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_shifted_offset_z_f32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo1 (float32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (float32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_shifted_offset_z_s32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (int32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shifted_offset_z_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_shifted_offset_z_u32 (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.u32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32_t const * base, uint32x4_t offset, mve_pred16_t p)
+foo1 (uint32_t const *base, uint32x4_t offset, mve_pred16_t p)
 {
   return vldrwq_gather_shifted_offset_z (base, offset, p);
 }
 
-/* { dg-final { scan-assembler "vldrwt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base)
+foo (int32_t const *base)
 {
   return vldrwq_s32 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrw.32" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c
@@ -1,14 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vldrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base)
+foo (uint32_t const *base)
 {
   return vldrwq_u32 (base);
 }
 
-/* { dg-final { scan-assembler-times "vldrw.32" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 float32x4_t
-foo (float32_t const * base, mve_pred16_t p)
+foo (float32_t const *base, mve_pred16_t p)
 {
   return vldrwq_z_f32 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32_t const * base, mve_pred16_t p)
+foo (int32_t const *base, mve_pred16_t p)
 {
   return vldrwq_z_s32 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c
@@ -1,15 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vldrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32_t const * base, mve_pred16_t p)
+foo (uint32_t const *base, mve_pred16_t p)
 {
   return vldrwq_z_u32 (base, p);
 }
 
-/* { dg-final { scan-assembler-times "vpst" 1 }  } */
-/* { dg-final { scan-assembler-times "vldrwt.32" 1 }  } */
+#ifdef __cplusplus
+}
+#endif
+
 /* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxat.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxaq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxat.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxat.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxaq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxat.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxat.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxaq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxat.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxat.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxa.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b)
 {
   return vmaxaq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxa.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxa.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b)
 {
   return vmaxaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxa.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxa.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b)
 {
   return vmaxaq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxa.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxa.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b)
 {
   return vmaxaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxa.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxa.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b)
 {
   return vmaxaq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxa.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxa.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b)
 {
   return vmaxaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxa.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, int16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (uint16_t a, int16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxavq_p (a, b, p);
 }
 
-
-int16_t
-foo2 (uint8_t a, int16x8_t b, mve_pred16_t p)
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16_t
+foo2 (int16x8_t b, mve_pred16_t p)
 {
-  return vmaxavq_p (a, b, p);
+  return vmaxavq_p (1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxavt.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (uint32_t a, int32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxavq_p (a, b, p);
 }
 
-
-int32_t
-foo2 (uint16_t a, int32x4_t b, mve_pred16_t p)
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int32x4_t b, mve_pred16_t p)
 {
-  return vmaxavq_p (a, b, p);
+  return vmaxavq_p (1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxavt.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, int8x16_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (uint8_t a, int8x16_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxavq_p (a, b, p);
 }
 
-
-int8_t
-foo2 (uint32_t a, int8x16_t b, mve_pred16_t p)
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8_t
+foo2 (int8x16_t b, mve_pred16_t p)
 {
-  return vmaxavq_p (a, b, p);
+  return vmaxavq_p (1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxavt.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxav.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, int16x8_t b)
 {
@@ -11,18 +22,32 @@ foo (uint16_t a, int16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxav.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, int16x8_t b)
 {
   return vmaxavq (a, b);
 }
 
-
-int16_t
-foo2 (uint8_t a, int16x8_t b)
+/*
+**foo2:
+**	...
+**	vmaxav.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16_t
+foo2 (int16x8_t b)
 {
-  return vmaxavq (a, b);
+  return vmaxavq (1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxav.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxav.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int32x4_t b)
 {
@@ -11,18 +22,32 @@ foo (uint32_t a, int32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxav.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int32x4_t b)
 {
   return vmaxavq (a, b);
 }
 
-
-int32_t
-foo2 (uint16_t a, int32x4_t b)
+/*
+**foo2:
+**	...
+**	vmaxav.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int32x4_t b)
 {
-  return vmaxavq (a, b);
+  return vmaxavq (1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxav.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxav.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, int8x16_t b)
 {
@@ -11,18 +22,32 @@ foo (uint8_t a, int8x16_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxav.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, int8x16_t b)
 {
   return vmaxavq (a, b);
 }
 
-
-int8_t
-foo2 (uint32_t a, int8x16_t b)
+/*
+**foo2:
+**	...
+**	vmaxav.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8_t
+foo2 (int8x16_t b)
 {
-  return vmaxavq (a, b);
+  return vmaxavq (1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxav.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxnma.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vmaxnmaq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnma.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxnma.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vmaxnmaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnma.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxnma.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vmaxnmaq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnma.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxnma.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vmaxnmaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnma.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmaq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmaq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b)
-{
-  return vmaxnmavq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxnmav.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b)
 {
@@ -11,18 +22,32 @@ foo (float16_t a, float16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxnmav.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b)
 {
   return vmaxnmavq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxnmav.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b)
+foo2 (float16x8_t b)
 {
-  return vmaxnmavq (a, b);
+  return vmaxnmavq (1.1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmav.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b)
-{
-  return vmaxnmavq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxnmav.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b)
 {
@@ -11,18 +22,32 @@ foo (float32_t a, float32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxnmav.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b)
 {
   return vmaxnmavq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxnmav.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b)
+foo2 (float32x4_t b)
 {
-  return vmaxnmavq (a, b);
+  return vmaxnmavq (1.1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmav.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
-{
-  return vmaxnmavq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmavt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmavt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmavq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmavt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b, mve_pred16_t p)
+foo2 (float16x8_t b, mve_pred16_t p)
 {
-  return vmaxnmavq_p (a, b, p);
+  return vmaxnmavq_p (1.1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmavt.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
-{
-  return vmaxnmavq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmavt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmavt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmavq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmavt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b, mve_pred16_t p)
+foo2 (float32x4_t b, mve_pred16_t p)
 {
-  return vmaxnmavq_p (a, b, p);
+  return vmaxnmavq_p (1.1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmavt.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxnm.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vmaxnmq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnm.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxnm.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vmaxnmq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnm.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxnm.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vmaxnmq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnm.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmaxnm.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vmaxnmq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmaxnm.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmt.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmt.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxnmt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b)
-{
-  return vmaxnmvq (23.35, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxnmv.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b)
 {
@@ -11,18 +22,32 @@ foo (float16_t a, float16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxnmv.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b)
 {
   return vmaxnmvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxnmv.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b)
+foo2 (float16x8_t b)
 {
-  return vmaxnmvq (a, b);
+  return vmaxnmvq (1.1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmv.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b)
-{
-  return vmaxnmvq (34.56, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxnmv.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b)
 {
@@ -11,18 +22,32 @@ foo (float32_t a, float32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxnmv.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b)
 {
   return vmaxnmvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxnmv.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b)
+foo2 (float32x4_t b)
 {
-  return vmaxnmvq (a, b);
+  return vmaxnmvq (1.1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmv.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
-{
-  return vmaxnmvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmvt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmvt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmaxnmvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmvt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b, mve_pred16_t p)
+foo2 (float16x8_t b, mve_pred16_t p)
 {
-  return vmaxnmvq_p (a, b, p);
+  return vmaxnmvq_p (1.1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmvt.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
-{
-  return vmaxnmvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmvt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmvt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmaxnmvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxnmvt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b, mve_pred16_t p)
+foo2 (float32x4_t b, mve_pred16_t p)
 {
-  return vmaxnmvq_p (a, b, p);
+  return vmaxnmvq_p (1.1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxnmvt.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmaxq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmaxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmaxq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmaxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmaxq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmaxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmax.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmaxq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmax.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmaxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmax.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmaxq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmax.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmaxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmax.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmaxq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmax.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmaxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmax.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmaxq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmax.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmaxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmax.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vmaxq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmax.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vmaxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmax.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmaxq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmax.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmaxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmax.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmaxq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmaxq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmaxq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmaxq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmaxq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmaxt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmaxq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo (int16_t a, int16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +26,24 @@ foo (int16_t a, int16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo1 (int16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmaxvq_p (a, b, p);
 }
 
-
-int16_t
-foo2 (int8_t a, int16x8_t b, mve_pred16_t p)
-{
-  return vmaxvq_p (a, b, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxvt.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +26,24 @@ foo (int32_t a, int32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmaxvq_p (a, b, p);
 }
 
-
-int32_t
-foo2 (int16_t a, int32x4_t b, mve_pred16_t p)
-{
-  return vmaxvq_p (a, b, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxvt.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo (int8_t a, int8x16_t b, mve_pred16_t p)
 {
@@ -11,18 +26,24 @@ foo (int8_t a, int8x16_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo1 (int8_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmaxvq_p (a, b, p);
 }
 
-
-int8_t
-foo2 (int32_t a, int8x16_t b, mve_pred16_t p)
-{
-  return vmaxvq_p (a, b, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxvt.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, uint16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (uint16_t a, uint16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmaxvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
-foo2 (uint32_t a, uint16x8_t b, mve_pred16_t p)
+foo2 (uint16x8_t b, mve_pred16_t p)
 {
-  return vmaxvq_p (a, b, p);
+  return vmaxvq_p (1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxvt.u16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (uint32_t a, uint32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmaxvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo2 (uint8_t a, uint32x4_t b, mve_pred16_t p)
+foo2 (uint32x4_t b, mve_pred16_t p)
 {
-  return vmaxvq_p (a, b, p);
+  return vmaxvq_p (1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxvt.u32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, uint8x16_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (uint8_t a, uint8x16_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmaxvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmaxvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
-foo2 (uint16_t a, uint8x16_t b, mve_pred16_t p)
+foo2 (uint8x16_t b, mve_pred16_t p)
 {
-  return vmaxvq_p (a, b, p);
+  return vmaxvq_p (1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxvt.u8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxv.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo (int16_t a, int16x8_t b)
 {
@@ -11,18 +22,20 @@ foo (int16_t a, int16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxv.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo1 (int16_t a, int16x8_t b)
 {
   return vmaxvq (a, b);
 }
 
-
-int16_t
-foo2 (int8_t a, int16x8_t b)
-{
-  return vmaxvq (a, b);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxv.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxv.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b)
 {
@@ -11,18 +22,20 @@ foo (int32_t a, int32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxv.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b)
 {
   return vmaxvq (a, b);
 }
 
-
-int32_t
-foo2 (int16_t a, int32x4_t b)
-{
-  return vmaxvq (a, b);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxv.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxv.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo (int8_t a, int8x16_t b)
 {
@@ -11,18 +22,20 @@ foo (int8_t a, int8x16_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxv.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo1 (int8_t a, int8x16_t b)
 {
   return vmaxvq (a, b);
 }
 
-
-int8_t
-foo2 (int32_t a, int8x16_t b)
-{
-  return vmaxvq (a, b);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxv.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, uint16x8_t b)
 {
@@ -11,18 +22,32 @@ foo (uint16_t a, uint16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, uint16x8_t b)
 {
   return vmaxvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
-foo2 (uint32_t a, uint16x8_t b)
+foo2 (uint16x8_t b)
 {
-  return vmaxvq (a, b);
+  return vmaxvq (1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxv.u16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b)
 {
@@ -11,18 +22,32 @@ foo (uint32_t a, uint32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b)
 {
   return vmaxvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo2 (uint8_t a, uint32x4_t b)
+foo2 (uint32x4_t b)
 {
-  return vmaxvq (a, b);
+  return vmaxvq (1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxv.u32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmaxv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, uint8x16_t b)
 {
@@ -11,18 +22,32 @@ foo (uint8_t a, uint8x16_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmaxv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, uint8x16_t b)
 {
   return vmaxvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmaxv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
-foo2 (uint16_t a, uint8x16_t b)
+foo2 (uint8x16_t b)
 {
-  return vmaxvq (a, b);
+  return vmaxvq (1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vmaxv.u8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminat.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminaq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminat.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminat.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminaq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminat.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminat.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminaq_m_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminat.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminat.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmina.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b)
 {
   return vminaq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmina.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmina.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b)
 {
   return vminaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmina.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmina.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b)
 {
   return vminaq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmina.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmina.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b)
 {
   return vminaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmina.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmina.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b)
 {
   return vminaq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmina.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmina.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b)
 {
   return vminaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmina.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, int16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (uint16_t a, int16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminavq_p (a, b, p);
 }
 
-
-int16_t
-foo2 (uint8_t a, int16x8_t b, mve_pred16_t p)
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16_t
+foo2 (int16x8_t b, mve_pred16_t p)
 {
-  return vminavq_p (a, b, p);
+  return vminavq_p (1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminavt.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (uint32_t a, int32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminavq_p (a, b, p);
 }
 
-
-int32_t
-foo2 (uint16_t a, int32x4_t b, mve_pred16_t p)
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int32x4_t b, mve_pred16_t p)
 {
-  return vminavq_p (a, b, p);
+  return vminavq_p (1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminavt.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, int8x16_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (uint8_t a, int8x16_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminavq_p (a, b, p);
 }
 
-
-int8_t
-foo2 (uint32_t a, int8x16_t b, mve_pred16_t p)
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8_t
+foo2 (int8x16_t b, mve_pred16_t p)
 {
-  return vminavq_p (a, b, p);
+  return vminavq_p (1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminavt.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminav.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, int16x8_t b)
 {
@@ -11,18 +22,32 @@ foo (uint16_t a, int16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminav.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, int16x8_t b)
 {
   return vminavq (a, b);
 }
 
-
-int16_t
-foo2 (uint8_t a, int16x8_t b)
+/*
+**foo2:
+**	...
+**	vminav.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16_t
+foo2 (int16x8_t b)
 {
-  return vminavq (a, b);
+  return vminavq (1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminav.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminav.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, int32x4_t b)
 {
@@ -11,18 +22,32 @@ foo (uint32_t a, int32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminav.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, int32x4_t b)
 {
   return vminavq (a, b);
 }
 
-
-int32_t
-foo2 (uint16_t a, int32x4_t b)
+/*
+**foo2:
+**	...
+**	vminav.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (int32x4_t b)
 {
-  return vminavq (a, b);
+  return vminavq (1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminav.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminav.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, int8x16_t b)
 {
@@ -11,18 +22,32 @@ foo (uint8_t a, int8x16_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminav.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, int8x16_t b)
 {
   return vminavq (a, b);
 }
 
-
-int8_t
-foo2 (uint32_t a, int8x16_t b)
+/*
+**foo2:
+**	...
+**	vminav.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8_t
+foo2 (int8x16_t b)
 {
-  return vminavq (a, b);
+  return vminavq (1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminav.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminnma.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vminnmaq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnma.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vminnma.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vminnmaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnma.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminnma.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vminnmaq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnma.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vminnma.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vminnmaq (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnma.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmaq_m_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmaq_m_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmaq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b)
-{
-  return vminnmavq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminnmav.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b)
 {
@@ -11,18 +22,32 @@ foo (float16_t a, float16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminnmav.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b)
 {
   return vminnmavq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vminnmav.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b)
+foo2 (float16x8_t b)
 {
-  return vminnmavq (a, b);
+  return vminnmavq (1.1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmav.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b)
-{
-  return vminnmavq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminnmav.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b)
 {
@@ -11,18 +22,32 @@ foo (float32_t a, float32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminnmav.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b)
 {
   return vminnmavq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vminnmav.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b)
+foo2 (float32x4_t b)
 {
-  return vminnmavq (a, b);
+  return vminnmavq (1.1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmav.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
-{
-  return vminnmavq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmavt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmavt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmavq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmavt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b, mve_pred16_t p)
+foo2 (float16x8_t b, mve_pred16_t p)
 {
-  return vminnmavq_p (a, b, p);
+  return vminnmavq_p (1.1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmavt.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
-{
-  return vminnmavq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmavt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmavt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmavq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmavt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b, mve_pred16_t p)
+foo2 (float32x4_t b, mve_pred16_t p)
 {
-  return vminnmavq_p (a, b, p);
+  return vminnmavq_p (1.1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmavt.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminnm.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vminnmq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnm.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vminnm.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vminnmq (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnm.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminnm.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vminnmq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnm.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vminnm.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vminnmq (a, b);
 }
 
-/* { dg-final { scan-assembler "vminnm.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmt.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmt.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vminnmt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b)
-{
-  return vminnmvq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminnmv.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b)
 {
@@ -11,18 +22,32 @@ foo (float16_t a, float16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminnmv.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b)
 {
   return vminnmvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vminnmv.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b)
+foo2 (float16x8_t b)
 {
-  return vminnmvq (a, b);
+  return vminnmvq (1.1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmv.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b)
-{
-  return vminnmvq (a, b);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminnmv.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b)
 {
@@ -11,18 +22,32 @@ foo (float32_t a, float32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminnmv.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b)
 {
   return vminnmvq (a, b);
 }
 
-
+/*
+**foo2:
+**	...
+**	vminnmv.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b)
+foo2 (float32x4_t b)
 {
-  return vminnmvq (a, b);
+  return vminnmvq (1.1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmv.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16_t
-foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
-{
-  return vminnmvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmvt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo (float16_t a, float16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmvt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
 foo1 (float16_t a, float16x8_t b, mve_pred16_t p)
 {
   return vminnmvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmvt.f16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float16_t
-foo2 (float32_t a, float16x8_t b, mve_pred16_t p)
+foo2 (float16x8_t b, mve_pred16_t p)
 {
-  return vminnmvq_p (a, b, p);
+  return vminnmvq_p (1.1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmvt.f16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32_t
-foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
-{
-  return vminnmvq_p (a, b, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmvt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo (float32_t a, float32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmvt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
 foo1 (float32_t a, float32x4_t b, mve_pred16_t p)
 {
   return vminnmvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminnmvt.f32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 float32_t
-foo2 (float16_t a, float32x4_t b, mve_pred16_t p)
+foo2 (float32x4_t b, mve_pred16_t p)
 {
-  return vminnmvq_p (a, b, p);
+  return vminnmvq_p (1.1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminnmvt.f32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vminq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vminq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vminq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vminq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vminq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vminq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmin.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vminq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmin.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vminq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmin.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vminq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmin.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vminq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmin.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vminq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmin.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vminq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmin.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vminq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmin.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vminq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmin.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vminq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmin.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vminq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmin.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vminq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmin.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vminq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmin.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vminq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vminq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vminq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vminq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vminq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmint.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmint.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vminq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo (int16_t a, int16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +26,24 @@ foo (int16_t a, int16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo1 (int16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vminvq_p (a, b, p);
 }
 
-
-int16_t
-foo2 (int8_t a, int16x8_t b, mve_pred16_t p)
-{
-  return vminvq_p (a, b, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminvt.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +26,24 @@ foo (int32_t a, int32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, mve_pred16_t p)
 {
   return vminvq_p (a, b, p);
 }
 
-
-int32_t
-foo2 (int16_t a, int32x4_t b, mve_pred16_t p)
-{
-  return vminvq_p (a, b, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminvt.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo (int8_t a, int8x16_t b, mve_pred16_t p)
 {
@@ -11,18 +26,24 @@ foo (int8_t a, int8x16_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo1 (int8_t a, int8x16_t b, mve_pred16_t p)
 {
   return vminvq_p (a, b, p);
 }
 
-
-int8_t
-foo2 (int32_t a, int8x16_t b, mve_pred16_t p)
-{
-  return vminvq_p (a, b, p);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminvt.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, uint16x8_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (uint16_t a, uint16x8_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vminvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
-foo2 (uint32_t a, uint16x8_t b, mve_pred16_t p)
+foo2 (uint16x8_t b, mve_pred16_t p)
 {
-  return vminvq_p (a, b, p);
+  return vminvq_p (1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminvt.u16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (uint32_t a, uint32x4_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vminvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo2 (uint8_t a, uint32x4_t b, mve_pred16_t p)
+foo2 (uint32x4_t b, mve_pred16_t p)
 {
-  return vminvq_p (a, b, p);
+  return vminvq_p (1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminvt.u32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c
@@ -1,9 +1,24 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, uint8x16_t b, mve_pred16_t p)
 {
@@ -11,18 +26,40 @@ foo (uint8_t a, uint8x16_t b, mve_pred16_t p)
 }
 
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vminvq_p (a, b, p);
 }
 
-
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vminvt.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
-foo2 (uint16_t a, uint8x16_t b, mve_pred16_t p)
+foo2 (uint8x16_t b, mve_pred16_t p)
 {
-  return vminvq_p (a, b, p);
+  return vminvq_p (1, b, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminvt.u8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminv.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo (int16_t a, int16x8_t b)
 {
@@ -11,17 +22,20 @@ foo (int16_t a, int16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminv.s16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int16_t
 foo1 (int16_t a, int16x8_t b)
 {
   return vminvq (a, b);
 }
 
-int16_t
-foo2 (int8_t a, int16x8_t b)
-{
-  return vminvq (a, b);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminv.s16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminv.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b)
 {
@@ -11,17 +22,20 @@ foo (int32_t a, int32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminv.s32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b)
 {
   return vminvq (a, b);
 }
 
-int32_t
-foo2 (int8_t a, int32x4_t b)
-{
-  return vminvq (a, b);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminv.s32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminv.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo (int8_t a, int8x16_t b)
 {
@@ -11,17 +22,20 @@ foo (int8_t a, int8x16_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminv.s8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 int8_t
 foo1 (int8_t a, int8x16_t b)
 {
   return vminvq (a, b);
 }
 
-int8_t
-foo2 (int32_t a, int8x16_t b)
-{
-  return vminvq (a, b);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminv.s8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo (uint16_t a, uint16x8_t b)
 {
@@ -11,18 +22,32 @@ foo (uint16_t a, uint16x8_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16_t
 foo1 (uint16_t a, uint16x8_t b)
 {
   return vminvq (a, b);
 }
 
-
-uint8_t
-foo2 (uint32_t a, uint16x8_t b)
+/*
+**foo2:
+**	...
+**	vminv.u16	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16_t
+foo2 (uint16x8_t b)
 {
-  return vminvq (a, b);
+  return vminvq (1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminv.u16" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo (uint32_t a, uint32x4_t b)
 {
@@ -11,17 +22,32 @@ foo (uint32_t a, uint32x4_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
 foo1 (uint32_t a, uint32x4_t b)
 {
   return vminvq (a, b);
 }
 
+/*
+**foo2:
+**	...
+**	vminv.u32	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo2 (uint16_t a, uint32x4_t b)
+foo2 (uint32x4_t b)
 {
-  return vminvq (a, b);
+  return vminvq (1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminv.u32" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c
@@ -1,9 +1,20 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vminv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo (uint8_t a, uint8x16_t b)
 {
@@ -11,18 +22,32 @@ foo (uint8_t a, uint8x16_t b)
 }
 
 
+/*
+**foo1:
+**	...
+**	vminv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8_t
 foo1 (uint8_t a, uint8x16_t b)
 {
   return vminvq (a, b);
 }
 
-
-uint16_t
-foo2 (uint32_t a, uint8x16_t b)
+/*
+**foo2:
+**	...
+**	vminv.u8	(?:ip|fp|r[0-9]+), q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8_t
+foo2 (uint8x16_t b)
 {
-  return vminvq (a, b);
+  return vminvq (1, b);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
-/* { dg-final { scan-assembler-times "vminv.u8" 3 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p_s16 (a, b, c, p);
+  return vmladavaq_p_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo1 (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p (a, b, c, p);
+  return vmladavaq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavat.s16"  }  } */
-/* { dg-final { scan-assembler "vmladavat.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p_s32 (a, b, c, p);
+  return vmladavaq_p_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo1 (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p (a, b, c, p);
+  return vmladavaq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavat.s32"  }  } */
-/* { dg-final { scan-assembler "vmladavat.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+foo (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p_s8 (a, b, c, p);
+  return vmladavaq_p_s8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+foo1 (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p (a, b, c, p);
+  return vmladavaq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavat.s8"  }  } */
-/* { dg-final { scan-assembler "vmladavat.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c
@@ -1,22 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+foo (uint32_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p_u16 (a, b, c, p);
+  return vmladavaq_p_u16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+foo1 (uint32_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p (a, b, c, p);
+  return vmladavaq_p (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
+{
+  return vmladavaq_p (1, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavat.u16"  }  } */
-/* { dg-final { scan-assembler "vmladavat.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c
@@ -1,22 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+foo (uint32_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p_u32 (a, b, c, p);
+  return vmladavaq_p_u32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+foo1 (uint32_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p (a, b, c, p);
+  return vmladavaq_p (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
+{
+  return vmladavaq_p (1, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavat.u32"  }  } */
-/* { dg-final { scan-assembler "vmladavat.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c
@@ -1,22 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p)
+foo (uint32_t add, uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p_u8 (a, b, c, p);
+  return vmladavaq_p_u8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavat.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p)
+foo1 (uint32_t add, uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
 {
-  return vmladavaq_p (a, b, c, p);
+  return vmladavaq_p (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavat.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
+{
+  return vmladavaq_p (1, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavat.u8"  }  } */
-/* { dg-final { scan-assembler "vmladavat.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladava.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int16x8_t b, int16x8_t c)
+foo (int32_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmladavaq_s16 (a, b, c);
+  return vmladavaq_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladava.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladava.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int16x8_t b, int16x8_t c)
+foo1 (int32_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmladavaq (a, b, c);
+  return vmladavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladava.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladava.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int32x4_t b, int32x4_t c)
+foo (int32_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmladavaq_s32 (a, b, c);
+  return vmladavaq_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladava.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladava.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int32x4_t b, int32x4_t c)
+foo1 (int32_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmladavaq (a, b, c);
+  return vmladavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladava.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladava.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int8x16_t b, int8x16_t c)
+foo (int32_t add, int8x16_t m1, int8x16_t m2)
 {
-  return vmladavaq_s8 (a, b, c);
+  return vmladavaq_s8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladava.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladava.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int8x16_t b, int8x16_t c)
+foo1 (int32_t add, int8x16_t m1, int8x16_t m2)
 {
-  return vmladavaq (a, b, c);
+  return vmladavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladava.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladava.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32_t a, uint16x8_t b, uint16x8_t c)
+foo (uint32_t add, uint16x8_t m1, uint16x8_t m2)
 {
-  return vmladavaq_u16 (a, b, c);
+  return vmladavaq_u16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladava.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladava.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32_t a, uint16x8_t b, uint16x8_t c)
+foo1 (uint32_t add, uint16x8_t m1, uint16x8_t m2)
 {
-  return vmladavaq (a, b, c);
+  return vmladavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmladava.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint16x8_t m1, uint16x8_t m2)
+{
+  return vmladavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladava.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladava.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32_t a, uint32x4_t b, uint32x4_t c)
+foo (uint32_t add, uint32x4_t m1, uint32x4_t m2)
 {
-  return vmladavaq_u32 (a, b, c);
+  return vmladavaq_u32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladava.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladava.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32_t a, uint32x4_t b, uint32x4_t c)
+foo1 (uint32_t add, uint32x4_t m1, uint32x4_t m2)
 {
-  return vmladavaq (a, b, c);
+  return vmladavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmladava.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint32x4_t m1, uint32x4_t m2)
+{
+  return vmladavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladava.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladava.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32_t a, uint8x16_t b, uint8x16_t c)
+foo (uint32_t add, uint8x16_t m1, uint8x16_t m2)
 {
-  return vmladavaq_u8 (a, b, c);
+  return vmladavaq_u8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladava.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladava.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32_t a, uint8x16_t b, uint8x16_t c)
+foo1 (uint32_t add, uint8x16_t m1, uint8x16_t m2)
 {
-  return vmladavaq (a, b, c);
+  return vmladavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmladava.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32_t
+foo2 (uint8x16_t m1, uint8x16_t m2)
+{
+  return vmladavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladava.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavaxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavaxq_p_s16 (a, b, c, p);
+  return vmladavaxq_p_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavaxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavaxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo1 (int32_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavaxq_p (a, b, c, p);
+  return vmladavaxq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavaxt.s16"  }  } */
-/* { dg-final { scan-assembler "vmladavaxt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavaxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavaxq_p_s32 (a, b, c, p);
+  return vmladavaxq_p_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavaxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo1 (int32_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavaxq_p (a, b, c, p);
+  return vmladavaxq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavaxt.s32"  }  } */
-/* { dg-final { scan-assembler "vmladavaxt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavaxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+foo (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavaxq_p_s8 (a, b, c, p);
+  return vmladavaxq_p_s8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavaxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavaxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
+foo1 (int32_t add, int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavaxq_p (a, b, c, p);
+  return vmladavaxq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavaxt.s8"  }  } */
-/* { dg-final { scan-assembler "vmladavaxt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladavax.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int16x8_t b, int16x8_t c)
+foo (int32_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmladavaxq_s16 (a, b, c);
+  return vmladavaxq_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavax.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladavax.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int16x8_t b, int16x8_t c)
+foo1 (int32_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmladavaxq (a, b, c);
+  return vmladavaxq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavax.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladavax.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int32x4_t b, int32x4_t c)
+foo (int32_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmladavaxq_s32 (a, b, c);
+  return vmladavaxq_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladavax.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int32x4_t b, int32x4_t c)
+foo1 (int32_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmladavaxq (a, b, c);
+  return vmladavaxq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavax.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladavax.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32_t a, int8x16_t b, int8x16_t c)
+foo (int32_t add, int8x16_t m1, int8x16_t m2)
 {
-  return vmladavaxq_s8 (a, b, c);
+  return vmladavaxq_s8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavax.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladavax.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32_t a, int8x16_t b, int8x16_t c)
+foo1 (int32_t add, int8x16_t m1, int8x16_t m2)
 {
-  return vmladavaxq (a, b, c);
+  return vmladavaxq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavax.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavq_p_s16 (a, b, p);
+  return vmladavq_p_s16 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavq_p (a, b, p);
+  return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavq_p_s32 (a, b, p);
+  return vmladavq_p_s32 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavq_p (a, b, p);
+  return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavq_p_s8 (a, b, p);
+  return vmladavq_p_s8 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavq_p (a, b, p);
+  return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmladavq_p_u16 (a, b, p);
+  return vmladavq_p_u16 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo1 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmladavq_p (a, b, p);
+  return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmladavq_p_u32 (a, b, p);
+  return vmladavq_p_u32 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo1 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmladavq_p (a, b, p);
+  return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+foo (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
 {
-  return vmladavq_p_u8 (a, b, p);
+  return vmladavq_p_u8 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavt.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+foo1 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
 {
-  return vmladavq_p (a, b, p);
+  return vmladavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
 {
-  return vmladavq_s16 (a, b);
+  return vmladavq_s16 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladav.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
 {
-  return vmladavq (a, b);
+  return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladav.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
 {
-  return vmladavq_s32 (a, b);
+  return vmladavq_s32 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladav.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
 {
-  return vmladavq (a, b);
+  return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladav.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int8x16_t a, int8x16_t b)
+foo (int8x16_t m1, int8x16_t m2)
 {
-  return vmladavq_s8 (a, b);
+  return vmladavq_s8 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladav.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int8x16_t a, int8x16_t b)
+foo1 (int8x16_t m1, int8x16_t m2)
 {
-  return vmladavq (a, b);
+  return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladav.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladav.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint16x8_t a, uint16x8_t b)
+foo (uint16x8_t m1, uint16x8_t m2)
 {
-  return vmladavq_u16 (a, b);
+  return vmladavq_u16 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladav.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladav.u16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint16x8_t a, uint16x8_t b)
+foo1 (uint16x8_t m1, uint16x8_t m2)
 {
-  return vmladavq (a, b);
+  return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladav.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladav.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint32x4_t a, uint32x4_t b)
+foo (uint32x4_t m1, uint32x4_t m2)
 {
-  return vmladavq_u32 (a, b);
+  return vmladavq_u32 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladav.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladav.u32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint32x4_t a, uint32x4_t b)
+foo1 (uint32x4_t m1, uint32x4_t m2)
 {
-  return vmladavq (a, b);
+  return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladav.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladav.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo (uint8x16_t a, uint8x16_t b)
+foo (uint8x16_t m1, uint8x16_t m2)
 {
-  return vmladavq_u8 (a, b);
+  return vmladavq_u8 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladav.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladav.u8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32_t
-foo1 (uint8x16_t a, uint8x16_t b)
+foo1 (uint8x16_t m1, uint8x16_t m2)
 {
-  return vmladavq (a, b);
+  return vmladavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladav.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavxq_p_s16 (a, b, p);
+  return vmladavxq_p_s16 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmladavxq_p (a, b, p);
+  return vmladavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavxt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavxq_p_s32 (a, b, p);
+  return vmladavxq_p_s32 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmladavxq_p (a, b, p);
+  return vmladavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavxt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavxq_p_s8 (a, b, p);
+  return vmladavxq_p_s8 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmladavxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmladavxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, mve_pred16_t p)
 {
-  return vmladavxq_p (a, b, p);
+  return vmladavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavxt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladavx.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
 {
-  return vmladavxq_s16 (a, b);
+  return vmladavxq_s16 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladavx.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
 {
-  return vmladavxq (a, b);
+  return vmladavxq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavx.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladavx.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
 {
-  return vmladavxq_s32 (a, b);
+  return vmladavxq_s32 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladavx.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
 {
-  return vmladavxq (a, b);
+  return vmladavxq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavx.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmladavx.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo (int8x16_t a, int8x16_t b)
+foo (int8x16_t m1, int8x16_t m2)
 {
-  return vmladavxq_s8 (a, b);
+  return vmladavxq_s8 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmladavx.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmladavx.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
-foo1 (int8x16_t a, int8x16_t b)
+foo1 (int8x16_t m1, int8x16_t m2)
 {
-  return vmladavxq (a, b);
+  return vmladavxq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmladavx.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p_s16 (a, b, c, p);
+  return vmlaldavaq_p_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p (a, b, c, p);
+  return vmlaldavaq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavat.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p_s32 (a, b, c, p);
+  return vmlaldavaq_p_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p (a, b, c, p);
+  return vmlaldavaq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavat.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+foo (uint64_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p_u16 (a, b, c, p);
+  return vmlaldavaq_p_u16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavat.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+foo1 (uint64_t add, uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p (a, b, c, p);
+  return vmlaldavaq_p (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
+{
+  return vmlaldavaq_p (1, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavat.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+foo (uint64_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p_u32 (a, b, c, p);
+  return vmlaldavaq_p_u32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavat.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+foo1 (uint64_t add, uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavaq_p (a, b, c, p);
+  return vmlaldavaq_p (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
+{
+  return vmlaldavaq_p (1, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavat.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldava.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int16x8_t b, int16x8_t c)
+foo (int64_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavaq_s16 (a, b, c);
+  return vmlaldavaq_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldava.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldava.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int16x8_t b, int16x8_t c)
+foo1 (int64_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavaq (a, b, c);
+  return vmlaldavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldava.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldava.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int32x4_t b, int32x4_t c)
+foo (int64_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavaq_s32 (a, b, c);
+  return vmlaldavaq_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldava.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldava.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int32x4_t b, int32x4_t c)
+foo1 (int64_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavaq (a, b, c);
+  return vmlaldavaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldava.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldava.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint64_t a, uint16x8_t b, uint16x8_t c)
+foo (uint64_t add, uint16x8_t m1, uint16x8_t m2)
 {
-  return vmlaldavaq_u16 (a, b, c);
+  return vmlaldavaq_u16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldava.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldava.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint64_t a, uint16x8_t b, uint16x8_t c)
+foo1 (uint64_t add, uint16x8_t m1, uint16x8_t m2)
 {
-  return vmlaldavaq (a, b, c);
+  return vmlaldavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmlaldava.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint16x8_t m1, uint16x8_t m2)
+{
+  return vmlaldavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldava.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldava.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint64_t a, uint32x4_t b, uint32x4_t c)
+foo (uint64_t add, uint32x4_t m1, uint32x4_t m2)
 {
-  return vmlaldavaq_u32 (a, b, c);
+  return vmlaldavaq_u32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldava.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldava.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint64_t a, uint32x4_t b, uint32x4_t c)
+foo1 (uint64_t add, uint32x4_t m1, uint32x4_t m2)
 {
-  return vmlaldavaq (a, b, c);
+  return vmlaldavaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmlaldava.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint32x4_t m1, uint32x4_t m2)
+{
+  return vmlaldavaq (1, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldava.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavaxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavaxq_p_s16 (a, b, c, p);
+  return vmlaldavaxq_p_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavaxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavaxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+foo1 (int64_t add, int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavaxq_p (a, b, c, p);
+  return vmlaldavaxq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavaxt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavaxq_p_s32 (a, b, c, p);
+  return vmlaldavaxq_p_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+foo1 (int64_t add, int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavaxq_p (a, b, c, p);
+  return vmlaldavaxq_p (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavaxt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldavax.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int16x8_t b, int16x8_t c)
+foo (int64_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavaxq_s16 (a, b, c);
+  return vmlaldavaxq_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldavax.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldavax.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int16x8_t b, int16x8_t c)
+foo1 (int64_t add, int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavaxq (a, b, c);
+  return vmlaldavaxq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavax.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldavax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int64_t a, int32x4_t b, int32x4_t c)
+foo (int64_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavaxq_s32 (a, b, c);
+  return vmlaldavaxq_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldavax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldavax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int64_t a, int32x4_t b, int32x4_t c)
+foo1 (int64_t add, int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavaxq (a, b, c);
+  return vmlaldavaxq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavax.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p_s16 (a, b, p);
+  return vmlaldavq_p_s16 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p (a, b, p);
+  return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p_s32 (a, b, p);
+  return vmlaldavq_p_s32 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p (a, b, p);
+  return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p_u16 (a, b, p);
+  return vmlaldavq_p_u16 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+foo1 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p (a, b, p);
+  return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p_u32 (a, b, p);
+  return vmlaldavq_p_u32 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavt.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+foo1 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavq_p (a, b, p);
+  return vmlaldavq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldav.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavq_s16 (a, b);
+  return vmlaldavq_s16 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldav.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldav.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavq (a, b);
+  return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldav.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldav.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavq_s32 (a, b);
+  return vmlaldavq_s32 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldav.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldav.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavq (a, b);
+  return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldav.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldav.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint16x8_t a, uint16x8_t b)
+foo (uint16x8_t m1, uint16x8_t m2)
 {
-  return vmlaldavq_u16 (a, b);
+  return vmlaldavq_u16 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldav.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldav.u16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint16x8_t a, uint16x8_t b)
+foo1 (uint16x8_t m1, uint16x8_t m2)
 {
-  return vmlaldavq (a, b);
+  return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldav.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldav.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo (uint32x4_t a, uint32x4_t b)
+foo (uint32x4_t m1, uint32x4_t m2)
 {
-  return vmlaldavq_u32 (a, b);
+  return vmlaldavq_u32 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldav.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldav.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
-foo1 (uint32x4_t a, uint32x4_t b)
+foo1 (uint32x4_t m1, uint32x4_t m2)
 {
-  return vmlaldavq (a, b);
+  return vmlaldavq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldav.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavxq_p_s16 (a, b, p);
+  return vmlaldavxq_p_s16 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, mve_pred16_t p)
 {
-  return vmlaldavxq_p (a, b, p);
+  return vmlaldavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavxt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavxq_p_s32 (a, b, p);
+  return vmlaldavxq_p_s32 (m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vmlaldavxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlaldavxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, mve_pred16_t p)
 {
-  return vmlaldavxq_p (a, b, p);
+  return vmlaldavxq_p (m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavxt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldavx.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int16x8_t a, int16x8_t b)
+foo (int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavxq_s16 (a, b);
+  return vmlaldavxq_s16 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldavx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldavx.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int16x8_t a, int16x8_t b)
+foo1 (int16x8_t m1, int16x8_t m2)
 {
-  return vmlaldavxq (a, b);
+  return vmlaldavxq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavx.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlaldavx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo (int32x4_t a, int32x4_t b)
+foo (int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavxq_s32 (a, b);
+  return vmlaldavxq_s32 (m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmlaldavx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlaldavx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
-foo1 (int32x4_t a, int32x4_t b)
+foo1 (int32x4_t m1, int32x4_t m2)
 {
-  return vmlaldavxq (a, b);
+  return vmlaldavxq (m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlaldavx.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
 {
-  return vmlaq_m_n_s16 (a, b, c, p);
+  return vmlaq_m_n_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
 {
-  return vmlaq_m (a, b, c, p);
+  return vmlaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
 {
-  return vmlaq_m_n_s32 (a, b, c, p);
+  return vmlaq_m_n_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
 {
-  return vmlaq_m (a, b, c, p);
+  return vmlaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
 {
-  return vmlaq_m_n_s8 (a, b, c, p);
+  return vmlaq_m_n_s8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
 {
-  return vmlaq_m (a, b, c, p);
+  return vmlaq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+foo (uint16x8_t add, uint16x8_t m1, uint16_t m2, mve_pred16_t p)
 {
-  return vmlaq_m_n_u16 (a, b, c, p);
+  return vmlaq_m_n_u16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+foo1 (uint16x8_t add, uint16x8_t m1, uint16_t m2, mve_pred16_t p)
 {
-  return vmlaq_m (a, b, c, p);
+  return vmlaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t add, uint16x8_t m1, mve_pred16_t p)
+{
+  return vmlaq_m (add, m1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+foo (uint32x4_t add, uint32x4_t m1, uint32_t m2, mve_pred16_t p)
 {
-  return vmlaq_m_n_u32 (a, b, c, p);
+  return vmlaq_m_n_u32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+foo1 (uint32x4_t add, uint32x4_t m1, uint32_t m2, mve_pred16_t p)
 {
-  return vmlaq_m (a, b, c, p);
+  return vmlaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t add, uint32x4_t m1, mve_pred16_t p)
+{
+  return vmlaq_m (add, m1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+foo (uint8x16_t add, uint8x16_t m1, uint8_t m2, mve_pred16_t p)
 {
-  return vmlaq_m_n_u8 (a, b, c, p);
+  return vmlaq_m_n_u8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+foo1 (uint8x16_t add, uint8x16_t m1, uint8_t m2, mve_pred16_t p)
 {
-  return vmlaq_m (a, b, c, p);
+  return vmlaq_m (add, m1, m2, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlat.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t add, uint8x16_t m1, mve_pred16_t p)
+{
+  return vmlaq_m (add, m1, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlat.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmla.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t add, int16x8_t m1, int16_t m2)
 {
-  return vmlaq_n_s16 (a, b, c);
+  return vmlaq_n_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmla.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmla.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2)
 {
-  return vmlaq (a, b, c);
+  return vmlaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmla.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmla.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t add, int32x4_t m1, int32_t m2)
 {
-  return vmlaq_n_s32 (a, b, c);
+  return vmlaq_n_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmla.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmla.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2)
 {
-  return vmlaq (a, b, c);
+  return vmlaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmla.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmla.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t add, int8x16_t m1, int8_t m2)
 {
-  return vmlaq_n_s8 (a, b, c);
+  return vmlaq_n_s8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmla.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmla.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2)
 {
-  return vmlaq (a, b, c);
+  return vmlaq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmla.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmla.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t a, uint16x8_t b, uint16_t c)
+foo (uint16x8_t add, uint16x8_t m1, uint16_t m2)
 {
-  return vmlaq_n_u16 (a, b, c);
+  return vmlaq_n_u16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmla.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmla.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c)
+foo1 (uint16x8_t add, uint16x8_t m1, uint16_t m2)
 {
-  return vmlaq (a, b, c);
+  return vmlaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmla.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t add, uint16x8_t m1)
+{
+  return vmlaq (add, m1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmla.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmla.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, uint32_t c)
+foo (uint32x4_t add, uint32x4_t m1, uint32_t m2)
 {
-  return vmlaq_n_u32 (a, b, c);
+  return vmlaq_n_u32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmla.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmla.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c)
+foo1 (uint32x4_t add, uint32x4_t m1, uint32_t m2)
 {
-  return vmlaq (a, b, c);
+  return vmlaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmla.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t add, uint32x4_t m1)
+{
+  return vmlaq (add, m1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmla.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmla.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t a, uint8x16_t b, uint8_t c)
+foo (uint8x16_t add, uint8x16_t m1, uint8_t m2)
 {
-  return vmlaq_n_u8 (a, b, c);
+  return vmlaq_n_u8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vmla.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmla.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c)
+foo1 (uint8x16_t add, uint8x16_t m1, uint8_t m2)
 {
-  return vmlaq (a, b, c);
+  return vmlaq (add, m1, m2);
+}
+
+/*
+**foo2:
+**	...
+**	vmla.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t add, uint8x16_t m1)
+{
+  return vmlaq (add, m1, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmla.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
 {
-  return vmlasq_m_n_s16 (a, b, c, p);
+  return vmlasq_m_n_s16 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
 {
-  return vmlasq_m (a, b, c, p);
+  return vmlasq_m (m1, m2, add, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
 {
-  return vmlasq_m_n_s32 (a, b, c, p);
+  return vmlasq_m_n_s32 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
 {
-  return vmlasq_m (a, b, c, p);
+  return vmlasq_m (m1, m2, add, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
 {
-  return vmlasq_m_n_s8 (a, b, c, p);
+  return vmlasq_m_n_s8 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
 {
-  return vmlasq_m (a, b, c, p);
+  return vmlasq_m (m1, m2, add, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+foo (uint16x8_t m1, uint16x8_t m2, uint16_t add, mve_pred16_t p)
 {
-  return vmlasq_m_n_u16 (a, b, c, p);
+  return vmlasq_m_n_u16 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c, mve_pred16_t p)
+foo1 (uint16x8_t m1, uint16x8_t m2, uint16_t add, mve_pred16_t p)
 {
-  return vmlasq_m (a, b, c, p);
+  return vmlasq_m (m1, m2, add, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t m1, uint16x8_t m2, mve_pred16_t p)
+{
+  return vmlasq_m (m1, m2, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+foo (uint32x4_t m1, uint32x4_t m2, uint32_t add, mve_pred16_t p)
 {
-  return vmlasq_m_n_u32 (a, b, c, p);
+  return vmlasq_m_n_u32 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred16_t p)
+foo1 (uint32x4_t m1, uint32x4_t m2, uint32_t add, mve_pred16_t p)
 {
-  return vmlasq_m (a, b, c, p);
+  return vmlasq_m (m1, m2, add, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t m1, uint32x4_t m2, mve_pred16_t p)
+{
+  return vmlasq_m (m1, m2, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+foo (uint8x16_t m1, uint8x16_t m2, uint8_t add, mve_pred16_t p)
 {
-  return vmlasq_m_n_u8 (a, b, c, p);
+  return vmlasq_m_n_u8 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c, mve_pred16_t p)
+foo1 (uint8x16_t m1, uint8x16_t m2, uint8_t add, mve_pred16_t p)
 {
-  return vmlasq_m (a, b, c, p);
+  return vmlasq_m (m1, m2, add, p);
+}
+
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlast.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t m1, uint8x16_t m2, mve_pred16_t p)
+{
+  return vmlasq_m (m1, m2, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmlast.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlas.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t m1, int16x8_t m2, int16_t add)
 {
-  return vmlasq_n_s16 (a, b, c);
+  return vmlasq_n_s16 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlas.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t m1, int16x8_t m2, int16_t add)
 {
-  return vmlasq (a, b, c);
+  return vmlasq (m1, m2, add);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlas.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlas.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t m1, int32x4_t m2, int32_t add)
 {
-  return vmlasq_n_s32 (a, b, c);
+  return vmlasq_n_s32 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlas.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t m1, int32x4_t m2, int32_t add)
 {
-  return vmlasq (a, b, c);
+  return vmlasq (m1, m2, add);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlas.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlas.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t m1, int8x16_t m2, int8_t add)
 {
-  return vmlasq_n_s8 (a, b, c);
+  return vmlasq_n_s8 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlas.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t m1, int8x16_t m2, int8_t add)
 {
-  return vmlasq (a, b, c);
+  return vmlasq (m1, m2, add);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlas.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlas.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t a, uint16x8_t b, uint16_t c)
+foo (uint16x8_t m1, uint16x8_t m2, uint16_t add)
 {
-  return vmlasq_n_u16 (a, b, c);
+  return vmlasq_n_u16 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlas.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t a, uint16x8_t b, uint16_t c)
+foo1 (uint16x8_t m1, uint16x8_t m2, uint16_t add)
 {
-  return vmlasq (a, b, c);
+  return vmlasq (m1, m2, add);
+}
+
+/*
+**foo2:
+**	...
+**	vmlas.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t m1, uint16x8_t m2)
+{
+  return vmlasq (m1, m2, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlas.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlas.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, uint32_t c)
+foo (uint32x4_t m1, uint32x4_t m2, uint32_t add)
 {
-  return vmlasq_n_u32 (a, b, c);
+  return vmlasq_n_u32 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlas.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, uint32_t c)
+foo1 (uint32x4_t m1, uint32x4_t m2, uint32_t add)
 {
-  return vmlasq (a, b, c);
+  return vmlasq (m1, m2, add);
+}
+
+/*
+**foo2:
+**	...
+**	vmlas.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t m1, uint32x4_t m2)
+{
+  return vmlasq (m1, m2, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlas.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlas.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t a, uint8x16_t b, uint8_t c)
+foo (uint8x16_t m1, uint8x16_t m2, uint8_t add)
 {
-  return vmlasq_n_u8 (a, b, c);
+  return vmlasq_n_u8 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vmlas.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlas.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t a, uint8x16_t b, uint8_t c)
+foo1 (uint8x16_t m1, uint8x16_t m2, uint8_t add)
 {
-  return vmlasq (a, b, c);
+  return vmlasq (m1, m2, add);
+}
+
+/*
+**foo2:
+**	...
+**	vmlas.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t m1, uint8x16_t m2)
+{
+  return vmlasq (m1, m2, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmlas.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavat.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsdavaq_p_s16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavat.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsdavaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavat.s16"  }  } */
-/* { dg-final { scan-assembler "vmlsdavat.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavat.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsdavaq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavat.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsdavaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavat.s32"  }  } */
-/* { dg-final { scan-assembler "vmlsdavat.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavat.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
 {
   return vmlsdavaq_p_s8 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavat.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavat.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
 {
   return vmlsdavaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavat.s8"  }  } */
-/* { dg-final { scan-assembler "vmlsdavat.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdava.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsdavaq_s16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdava.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdava.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsdavaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdava.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdava.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsdavaq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdava.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdava.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsdavaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdava.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdava.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int8x16_t b, int8x16_t c)
 {
   return vmlsdavaq_s8 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdava.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdava.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int8x16_t b, int8x16_t c)
 {
   return vmlsdavaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdava.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavaxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsdavaxq_p_s16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavaxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavaxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsdavaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavaxt.s16"  }  } */
-/* { dg-final { scan-assembler "vmlsdavaxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavaxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsdavaxq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavaxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsdavaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavaxt.s32"  }  } */
-/* { dg-final { scan-assembler "vmlsdavaxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavaxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
 {
   return vmlsdavaxq_p_s8 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavaxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavaxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p)
 {
   return vmlsdavaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavaxt.s8"  }  } */
-/* { dg-final { scan-assembler "vmlsdavaxt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdavax.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsdavaxq_s16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdavax.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdavax.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsdavaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdavax.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdavax.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsdavaxq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdavax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdavax.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsdavaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdavax.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdavax.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32_t a, int8x16_t b, int8x16_t c)
 {
   return vmlsdavaxq_s8 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdavax.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdavax.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32_t a, int8x16_t b, int8x16_t c)
 {
   return vmlsdavaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsdavax.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsdavq_p_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsdavq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsdavq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsdavq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmlsdavq_p_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmlsdavq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmlsdavq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdav.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdav.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmlsdavq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdav.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmlsdavq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdav.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdav.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmlsdavq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdav.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmlsdavq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdav.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdav.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmlsdavq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdav.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsdavxq_p_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavxt.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsdavxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsdavxq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavxt.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsdavxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmlsdavxq_p_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsdavxt.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmlsdavxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsdavxt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdavx.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmlsdavxq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdavx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdavx.s16	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmlsdavxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdavx.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdavx.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmlsdavxq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdavx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdavx.s32	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmlsdavxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdavx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsdavx.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmlsdavxq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdavx.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsdavx.s8	(?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmlsdavxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsdavx.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavat.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsldavaq_p_s16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavat.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavat.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsldavaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavat.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsldavaq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsldavaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavat.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldava.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsldavaq_s16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldava.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldava.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsldavaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldava.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldava.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsldavaq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldava.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldava.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsldavaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldava.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavaxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsldavaxq_p_s16 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavaxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavaxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
 {
   return vmlsldavaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavaxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsldavaxq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vmlsldavaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavaxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldavax.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsldavaxq_s16 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldavax.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldavax.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int16x8_t b, int16x8_t c)
 {
   return vmlsldavaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldavax.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldavax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsldavaxq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldavax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldavax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vmlsldavaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vmlsldavax.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsldavq_p_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsldavq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsldavq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsldavq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldav.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmlsldavq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldav.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldav.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmlsldavq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldav.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldav.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmlsldavq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldav.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldav.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmlsldavq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldav.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsldavxq_p_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavxt.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmlsldavxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsldavxq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmlsldavxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmlsldavxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vmlsldavxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldavx.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmlsldavxq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldavx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldavx.s16	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmlsldavxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldavx.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmlsldavx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmlsldavxq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldavx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmlsldavx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmlsldavxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmlsldavx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_m_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlb.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a)
 {
   return vmovlbq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlb.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a)
 {
   return vmovlbq (a);
 }
 
-/* { dg-final { scan-assembler "vmovlb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlb.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a)
 {
   return vmovlbq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlb.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlb.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a)
 {
   return vmovlbq (a);
 }
 
-/* { dg-final { scan-assembler "vmovlb.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlb.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a)
 {
-    return vmovlbq_u16 (a);
+  return vmovlbq_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlb.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a)
 {
-    return vmovlbq (a);
+  return vmovlbq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmovlb.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlb.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a)
 {
-    return vmovlbq_u8 (a);
+  return vmovlbq_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlb.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlb.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a)
 {
-    return vmovlbq (a);
+  return vmovlbq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmovlb.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_x_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vmovlbq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovlbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovlbt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vmovlbq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vmovltq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vmovltq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vmovltq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vmovltq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vmovltq_m_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vmovltq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vmovltq_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vmovltq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a)
 {
   return vmovltq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a)
 {
   return vmovltq (a);
 }
 
-/* { dg-final { scan-assembler "vmovlt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a)
 {
   return vmovltq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a)
 {
   return vmovltq (a);
 }
 
-/* { dg-final { scan-assembler "vmovlt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a)
 {
-    return vmovltq_u16 (a);
+  return vmovltq_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a)
 {
-    return vmovltq (a);
+  return vmovltq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmovlt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovlt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a)
 {
-    return vmovltq_u8 (a);
+  return vmovltq_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vmovlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovlt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a)
 {
-    return vmovltq (a);
+  return vmovltq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmovlt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vmovltq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vmovltq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vmovltq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vmovltq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vmovltq_x_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vmovltq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vmovltq_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovltt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovltt.u8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vmovltq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmovnbq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmovnbq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmovnbq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmovnbq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovnbt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovnbt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnb.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vmovnbq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnb.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnb.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vmovnbq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnb.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnb.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vmovnbq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnb.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnb.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vmovnbq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnb.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnb.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmovntq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmovntq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmovntq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmovntq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmovntt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmovntt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vmovntq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vmovntq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vmovntq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnt.i16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmovnt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vmovntq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmovnt.i32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmovnt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulhq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulhq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulhq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmulhq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmulhq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmulhq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmulh.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmulhq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmulh.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmulh.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vmulhq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmulh.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmulh.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmulhq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmulh.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmulh.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulhq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulhq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulhq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulhq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulhq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulhq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulht.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmullbq_int_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmullbq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmullbq_int_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmullbq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmullbq_int_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmullbq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmullbq_int_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmullbq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vmullbq_int_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vmullbq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmullbq_int_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmullbq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmullbq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_poly_m_p16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.p16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_poly_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.p16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_poly_m_p8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.p8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_poly_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.p8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmullbq_poly_p16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.p16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmullbq_poly (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.p16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullb.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmullbq_poly_p8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.p8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullb.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmullbq_poly (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullb.p8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_poly_x_p16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.p16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmullbq_poly_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_poly_x_p8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmullbt.p8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmullbt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmullbq_poly_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint64x2_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmulltq_int_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmulltq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmulltq_int_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmulltq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmulltq_int_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmulltq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmulltq_int_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmulltq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vmulltq_int_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vmulltq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmulltq_int_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmulltq_int (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulltq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_int_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_poly_m_p16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.p16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_poly_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.p16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_poly_m_p8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.p8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_poly_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.p8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmulltq_poly_p16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.p16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmulltq_poly (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.p16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmullt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmulltq_poly_p8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.p8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmullt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmulltq_poly (a, b);
 }
 
-/* { dg-final { scan-assembler "vmullt.p8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_poly_x_p16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.p16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulltq_poly_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_poly_x_p8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmulltt.p8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmulltt.p8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulltq_poly_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vmulq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vmulq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmulq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmulq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vmulq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vmulq_m_n_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vmulq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vmulq_m_n_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vmulq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vmulq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vmulq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vmulq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vmulq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vmulq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vmulq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vmulq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b)
 {
   return vmulq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmul.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t a)
+{
+  return vmulq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vmulq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b)
 {
   return vmulq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmul.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t a)
+{
+  return vmulq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vmulq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vmulq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vmulq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vmulq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vmulq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vmulq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vmulq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vmulq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vmulq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vmulq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vmulq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vmulq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vmulq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vmulq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vmulq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmul.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vmul.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmulq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmulq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vmulq_x (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vmulq_x_n_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vmulq_x (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vmulq_x (a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vmulq_x_n_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vmulq_x (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vmulq_x_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vmulq_x_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vmulq_x_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vmulq_x_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vmulq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vmulq_x_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vmulq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vmulq_x_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vmulq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmult.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmult.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m_n_s16 (inactive, 2, p);
+  return vmvnq_m_n_s16 (inactive, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m (inactive, 2, p);
+  return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m_n_s32 (inactive, 2, p);
+  return vmvnq_m_n_s32 (inactive, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m (inactive, 2, p);
+  return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m_n_u16 (inactive, 4, p);
+  return vmvnq_m_n_u16 (inactive, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m (inactive, 4, p);
+  return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m_n_u32 (inactive, 4, p);
+  return vmvnq_m_n_u32 (inactive, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, mve_pred16_t p)
 {
-  return vmvnq_m (inactive, 4, p);
+  return vmvnq_m (inactive, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vmvnq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vmvnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vmvnq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vmvnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vmvnq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vmvnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vmvnq_m_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vmvnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vmvnq_m_u32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vmvnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vmvnq_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vmvnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo ()
 {
   return vmvnq_n_s16 (1);
 }
 
-/* { dg-final { scan-assembler "vmvn.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo ()
 {
-  return vmvnq_n_s32 (2);
+  return vmvnq_n_s32 (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmvn.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo ()
 {
-    return vmvnq_n_u16 (1);
+  return vmvnq_n_u16 (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmvn.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c
@@ -1,13 +1,28 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo ()
 {
-    return vmvnq_n_u32 (2);
+  return vmvnq_n_u32 (1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmvn.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vmvnq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vmvnq (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vmvnq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vmvnq (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vmvnq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vmvnq (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-    return vmvnq_u16 (a);
+  return vmvnq_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-    return vmvnq (a);
+  return vmvnq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
-    return vmvnq_u32 (a);
+  return vmvnq_u32 (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
-    return vmvnq (a);
+  return vmvnq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-    return vmvnq_u8 (a);
+  return vmvnq_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmvn	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-    return vmvnq (a);
+  return vmvnq (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vmvn"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (mve_pred16_t p)
 {
-  return vmvnq_x_n_s16 (2, p);
+  return vmvnq_x_n_s16 (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (mve_pred16_t p)
 {
-  return vmvnq_x_n_s32 (2, p);
+  return vmvnq_x_n_s32 (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (mve_pred16_t p)
 {
-  return vmvnq_x_n_u16 (4, p);
+  return vmvnq_x_n_u16 (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c
@@ -1,14 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (mve_pred16_t p)
 {
-  return vmvnq_x_n_u32 (4, p);
+  return vmvnq_x_n_u32 (1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vmvnq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vmvnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vmvnq_x_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vmvnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vmvnq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vmvnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vmvnq_x_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vmvnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vmvnq_x_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vmvnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vmvnq_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vmvnt	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vmvnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vmvnt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vneg.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vnegq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vneg.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vneg.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vnegq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vneg.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vnegq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vneg.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vneg.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vnegq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vnegq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vnegq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vnegq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vnegq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vnegq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vneg.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vnegq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vneg.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vneg.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vnegq (a);
 }
 
-/* { dg-final { scan-assembler "vneg.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vneg.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vnegq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vneg.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vneg.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vnegq (a);
 }
 
-/* { dg-final { scan-assembler "vneg.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vneg.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vnegq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vneg.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vneg.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vnegq (a);
 }
 
-/* { dg-final { scan-assembler "vneg.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vnegq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vnegq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vnegq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vnegq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vnegq_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vnegq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vnegq_x_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vnegq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vnegq_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vnegt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vnegt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vnegq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vornq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vornq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vornq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vornq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vornq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vornq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vornq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vornq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vornq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vornq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vornq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vornq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vornq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vornq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vornq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vornq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vornq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorn	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vornq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorn"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vornq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vornq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vornq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vornq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vornq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vornq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vornq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vornq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vornt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vornt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vornq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vorrq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vorrq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vorrq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vorrq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-  return vorrq_m_n_s16 (a, 253, p);
+  return vorrq_m_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
-  return vorrq_m_n (a, 253, p);
+  return vorrq_m_n (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vorrq_m_n_s32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vorrq_m_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vorrq_m_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vorrq_m_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vorrq_m_n_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vorrq_m_n (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vorrq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vorrq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vorrq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vorrq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vorrq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vorrq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vorrq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vorrq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vorr.i16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vorr.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16x8_t a)
+{
+  return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vorrq_n_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vorr.i32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vorr.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32x4_t a)
+{
+  return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
   return vorrq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vorr.i16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vorr.i16	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16x8_t a)
+{
+  return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
-  return vorrq_n_u32 (a, 44);
+  return vorrq_n_u32 (a, 1);
+}
+
+
+/*
+**foo1:
+**	...
+**	vorr.i32	q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32x4_t a)
+{
+  return vorrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vorr.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vorrq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vorrq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vorrq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vorrq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vorrq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vorrq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
 
+/*
+**foo1:
+**	...
+**	vorr	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vorrq (a, b);
 }
 
-/* { dg-final { scan-assembler "vorr"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vorrq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vorrq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vorrq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vorrq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vorrq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vorrq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vorrq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vorrq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vorrt"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vorrt	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vorrq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
@@ -1,21 +1,32 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpnot(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), p0(?:	@.*|)
+**	...
+*/
 mve_pred16_t
 foo (mve_pred16_t a)
 {
   return vpnot (a);
 }
 
-/* { dg-final { scan-assembler "vpnot"  }  } */
-
-mve_pred16_t
-foo1 (mve_pred16_t a)
-{
-  return vpnot (a);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpnot"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vpselq_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vpselq_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vpselq_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vpselq_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t a, int64x2_t b, mve_pred16_t p)
 {
   return vpselq_s64 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t a, int64x2_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vpselq_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vpselq_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vpselq_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint64x2_t a, uint64x2_t b, mve_pred16_t p)
 {
   return vpselq_u64 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo1 (uint64x2_t a, uint64x2_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c
@@ -1,21 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vpselq_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpsel	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vpselq (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpsel"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqabst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vqabsq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqabst.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqabst.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vqabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqabst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vqabsq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqabst.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqabst.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vqabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqabst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vqabsq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqabst.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqabst.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vqabsq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqabs.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vqabsq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vqabs.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqabs.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vqabsq (a);
 }
 
-/* { dg-final { scan-assembler "vqabs.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqabs.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vqabsq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vqabs.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqabs.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vqabsq (a);
 }
 
-/* { dg-final { scan-assembler "vqabs.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqabs.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vqabsq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vqabs.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqabs.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vqabsq (a);
 }
 
-/* { dg-final { scan-assembler "vqabs.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqaddq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqaddq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqaddq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vqaddq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vqaddq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vqaddq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vqaddq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vqaddq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vqaddq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqaddq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqaddq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqaddq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqaddq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqaddq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vqaddq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vqaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqaddt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqadd.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vqaddq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqadd.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vqaddq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqadd.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vqaddq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqadd.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vqaddq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vqadd.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vqaddq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqadd.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vqaddq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vqadd.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vqaddq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqadd.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vqaddq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vqadd.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vqaddq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqadd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqaddq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqadd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqaddq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqadd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vqaddq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqadd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vqaddq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqadd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vqaddq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqadd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vqaddq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqadd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vqaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqadd.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmladhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmladhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmladhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmladhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmladhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmladhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmladh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmladhq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmladh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmladhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmladh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmladhq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmladh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmladhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmladh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmladhq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmladh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmladhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmladhxq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladhxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmladhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladhxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmladhxq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladhxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmladhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladhxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmladhxq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladhxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmladhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmladhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmladhxt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmladhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmladhxq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladhx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmladhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmladhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladhx.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmladhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmladhxq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladhx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmladhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmladhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladhx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmladhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmladhxq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladhx.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmladhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmladhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmladhx.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlaht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
 {
-  return vqdmlahq_m_n_s16 (a, b, c, p);
+  return vqdmlahq_m_n_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlaht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlaht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
 {
-  return vqdmlahq_m (a, b, c, p);
+  return vqdmlahq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlaht.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlaht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
 {
-  return vqdmlahq_m_n_s32 (a, b, c, p);
+  return vqdmlahq_m_n_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlaht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlaht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
 {
-  return vqdmlahq_m (a, b, c, p);
+  return vqdmlahq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlaht.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlaht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
 {
-  return vqdmlahq_m_n_s8 (a, b, c, p);
+  return vqdmlahq_m_n_s8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlaht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlaht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
 {
-  return vqdmlahq_m (a, b, c, p);
+  return vqdmlahq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlaht.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlah.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t add, int16x8_t m1, int16_t m2)
 {
-  return vqdmlahq_n_s16 (a, b, c);
+  return vqdmlahq_n_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqdmlah.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlah.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2)
 {
-  return vqdmlahq (a, b, c);
+  return vqdmlahq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqdmlah.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlah.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t add, int32x4_t m1, int32_t m2)
 {
-  return vqdmlahq_n_s32 (a, b, c);
+  return vqdmlahq_n_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqdmlah.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlah.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2)
 {
-  return vqdmlahq (a, b, c);
+  return vqdmlahq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqdmlah.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlah.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t add, int8x16_t m1, int8_t m2)
 {
-  return vqdmlahq_n_s8 (a, b, c);
+  return vqdmlahq_n_s8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqdmlah.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlah.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2)
 {
-  return vqdmlahq (a, b, c);
+  return vqdmlahq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqdmlah.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlasht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
 {
-  return vqdmlashq_m_n_s16 (a, b, c, p);
+  return vqdmlashq_m_n_s16 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlasht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlasht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
 {
-  return vqdmlashq_m (a, b, c, p);
+  return vqdmlashq_m (m1, m2, add, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlasht.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlasht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
 {
-  return vqdmlashq_m_n_s32 (a, b, c, p);
+  return vqdmlashq_m_n_s32 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlasht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlasht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
 {
-  return vqdmlashq_m (a, b, c, p);
+  return vqdmlashq_m (m1, m2, add, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlasht.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlasht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
 {
-  return vqdmlashq_m_n_s8 (a, b, c, p);
+  return vqdmlashq_m_n_s8 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlasht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlasht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
 {
-  return vqdmlashq_m (a, b, c, p);
+  return vqdmlashq_m (m1, m2, add, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlasht.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlash.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t m1, int16x8_t m2, int16_t add)
 {
-  return vqdmlashq_n_s16 (a, b, c);
+  return vqdmlashq_n_s16 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqdmlash.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlash.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t m1, int16x8_t m2, int16_t add)
 {
-  return vqdmlashq (a, b, c);
+  return vqdmlashq (m1, m2, add);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqdmlash.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlash.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t m1, int32x4_t m2, int32_t add)
 {
-  return vqdmlashq_n_s32 (a, b, c);
+  return vqdmlashq_n_s32 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqdmlash.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlash.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t m1, int32x4_t m2, int32_t add)
 {
-  return vqdmlashq (a, b, c);
+  return vqdmlashq (m1, m2, add);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqdmlash.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlash.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t m1, int8x16_t m2, int8_t add)
 {
-  return vqdmlashq_n_s8 (a, b, c);
+  return vqdmlashq_n_s8 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqdmlash.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlash.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t m1, int8x16_t m2, int8_t add)
 {
-  return vqdmlashq (a, b, c);
+  return vqdmlashq (m1, m2, add);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqdmlash.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmlsdhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmlsdhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmlsdhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmlsdhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmlsdhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmlsdhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlsdh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmlsdhq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlsdh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmlsdhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlsdh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmlsdhq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlsdh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmlsdhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlsdh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmlsdhq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlsdh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmlsdhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmlsdhxq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdhxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmlsdhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdhxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmlsdhxq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdhxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmlsdhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdhxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmlsdhxq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdhxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmlsdhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmlsdhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmlsdhxt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlsdhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmlsdhxq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdhx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlsdhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqdmlsdhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdhx.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlsdhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmlsdhxq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdhx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlsdhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqdmlsdhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdhx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmlsdhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmlsdhxq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdhx.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmlsdhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqdmlsdhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmlsdhx.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqdmulhq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqdmulhq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqdmulhq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmulhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmulhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmulhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmulh.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vqdmulhq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmulh.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vqdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmulh.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vqdmulhq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmulh.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmulh.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vqdmulhq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmulh.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vqdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqdmulhq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqdmulhq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vqdmulhq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vqdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmulh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqdmullbq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqdmullbq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqdmullbq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqdmullbq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmullbq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmullbq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmullbq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmullbt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmullbq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmullbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmullb.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16_t b)
 {
   return vqdmullbq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullb.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vqdmullbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmullb.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32_t b)
 {
   return vqdmullbq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullb.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqdmullbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmullb.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqdmullbq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullb.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqdmullbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmullb.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqdmullbq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullb.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqdmullbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqdmulltq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqdmulltq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqdmulltq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqdmulltq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmulltq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqdmulltq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmulltq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqdmulltt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqdmulltq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqdmulltt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmullt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16_t b)
 {
   return vqdmulltq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vqdmulltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmullt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32_t b)
 {
   return vqdmulltq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqdmulltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmullt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqdmulltq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqdmulltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqdmullt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqdmulltq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqdmullt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqdmulltq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqdmullt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovnbq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovnbq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqmovnbq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqmovnbq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovnbt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovnbt.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqmovnbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnb.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vqmovnbq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnb.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vqmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnb.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vqmovnbq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnb.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vqmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnb.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vqmovnbq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnb.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vqmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnb.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vqmovnbq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnb.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vqmovnbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnb.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovntq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovntq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqmovntq_m_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqmovntq_m_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovntt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovntt.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqmovntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vqmovntq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vqmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vqmovntq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vqmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vqmovntq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnt.u16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vqmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovnt.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vqmovntq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovnt.u32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vqmovntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovnt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovunbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovunbq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovunbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovunbt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovunbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovunbt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovunbq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovunbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovunbt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovunbq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovunb.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b)
 {
   return vqmovunbq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovunb.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b)
 {
   return vqmovunbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovunb.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b)
 {
   return vqmovunbq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovunb.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b)
 {
   return vqmovunbq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovuntt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovuntq_m_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovuntt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovuntt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqmovuntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovuntt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovuntq_m_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqmovuntt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqmovuntt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqmovuntq_m (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovunt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b)
 {
   return vqmovuntq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovunt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b)
 {
   return vqmovuntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqmovunt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b)
 {
   return vqmovuntq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqmovunt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b)
 {
   return vqmovuntq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqmovunt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqnegt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vqnegq_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqnegt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqnegt.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vqnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqnegt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vqnegq_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqnegt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqnegt.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vqnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqnegt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vqnegq_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqnegt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqnegt.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vqnegq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqneg.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vqnegq_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vqneg.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqneg.s16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vqnegq (a);
 }
 
-/* { dg-final { scan-assembler "vqneg.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqneg.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vqnegq_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vqneg.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqneg.s32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vqnegq (a);
 }
 
-/* { dg-final { scan-assembler "vqneg.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqneg.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vqnegq_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vqneg.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqneg.s8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vqnegq (a);
 }
 
-/* { dg-final { scan-assembler "vqneg.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmladhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmladhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmladhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmladhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmladhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmladhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmladh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmladhq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmladh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmladhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmladh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmladhq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmladh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmladhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmladh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmladhq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmladh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmladhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmladhxq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladhxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmladhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladhxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmladhxq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladhxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmladhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladhxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmladhxq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladhxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmladhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmladhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmladhxt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmladhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmladhxq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladhx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmladhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmladhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladhx.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmladhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmladhxq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladhx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmladhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmladhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladhx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmladhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmladhxq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladhx.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmladhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmladhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmladhx.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlaht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
 {
-  return vqrdmlahq_m_n_s16 (a, b, c, p);
+  return vqrdmlahq_m_n_s16 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlaht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlaht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2, mve_pred16_t p)
 {
-  return vqrdmlahq_m (a, b, c, p);
+  return vqrdmlahq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlaht.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlaht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
 {
-  return vqrdmlahq_m_n_s32 (a, b, c, p);
+  return vqrdmlahq_m_n_s32 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlaht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlaht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2, mve_pred16_t p)
 {
-  return vqrdmlahq_m (a, b, c, p);
+  return vqrdmlahq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlaht.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlaht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
 {
-  return vqrdmlahq_m_n_s8 (a, b, c, p);
+  return vqrdmlahq_m_n_s8 (add, m1, m2, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlaht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlaht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2, mve_pred16_t p)
 {
-  return vqrdmlahq_m (a, b, c, p);
+  return vqrdmlahq_m (add, m1, m2, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlaht.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlah.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t add, int16x8_t m1, int16_t m2)
 {
-  return vqrdmlahq_n_s16 (a, b, c);
+  return vqrdmlahq_n_s16 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqrdmlah.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlah.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t add, int16x8_t m1, int16_t m2)
 {
-  return vqrdmlahq (a, b, c);
+  return vqrdmlahq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqrdmlah.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlah.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t add, int32x4_t m1, int32_t m2)
 {
-  return vqrdmlahq_n_s32 (a, b, c);
+  return vqrdmlahq_n_s32 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqrdmlah.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlah.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t add, int32x4_t m1, int32_t m2)
 {
-  return vqrdmlahq (a, b, c);
+  return vqrdmlahq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqrdmlah.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlah.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t add, int8x16_t m1, int8_t m2)
 {
-  return vqrdmlahq_n_s8 (a, b, c);
+  return vqrdmlahq_n_s8 (add, m1, m2);
 }
 
-/* { dg-final { scan-assembler "vqrdmlah.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlah.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t add, int8x16_t m1, int8_t m2)
 {
-  return vqrdmlahq (a, b, c);
+  return vqrdmlahq (add, m1, m2);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqrdmlah.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlasht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
 {
-  return vqrdmlashq_m_n_s16 (a, b, c, p);
+  return vqrdmlashq_m_n_s16 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlasht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlasht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p)
+foo1 (int16x8_t m1, int16x8_t m2, int16_t add, mve_pred16_t p)
 {
-  return vqrdmlashq_m (a, b, c, p);
+  return vqrdmlashq_m (m1, m2, add, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlasht.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlasht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
 {
-  return vqrdmlashq_m_n_s32 (a, b, c, p);
+  return vqrdmlashq_m_n_s32 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlasht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlasht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p)
+foo1 (int32x4_t m1, int32x4_t m2, int32_t add, mve_pred16_t p)
 {
-  return vqrdmlashq_m (a, b, c, p);
+  return vqrdmlashq_m (m1, m2, add, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlasht.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlasht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
 {
-  return vqrdmlashq_m_n_s8 (a, b, c, p);
+  return vqrdmlashq_m_n_s8 (m1, m2, add, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlasht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlasht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p)
+foo1 (int8x16_t m1, int8x16_t m2, int8_t add, mve_pred16_t p)
 {
-  return vqrdmlashq_m (a, b, c, p);
+  return vqrdmlashq_m (m1, m2, add, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlasht.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlash.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, int16x8_t b, int16_t c)
+foo (int16x8_t m1, int16x8_t m2, int16_t add)
 {
-  return vqrdmlashq_n_s16 (a, b, c);
+  return vqrdmlashq_n_s16 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqrdmlash.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlash.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, int16x8_t b, int16_t c)
+foo1 (int16x8_t m1, int16x8_t m2, int16_t add)
 {
-  return vqrdmlashq (a, b, c);
+  return vqrdmlashq (m1, m2, add);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqrdmlash.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlash.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, int32_t c)
+foo (int32x4_t m1, int32x4_t m2, int32_t add)
 {
-  return vqrdmlashq_n_s32 (a, b, c);
+  return vqrdmlashq_n_s32 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqrdmlash.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlash.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, int32_t c)
+foo1 (int32x4_t m1, int32x4_t m2, int32_t add)
 {
-  return vqrdmlashq (a, b, c);
+  return vqrdmlashq (m1, m2, add);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqrdmlash.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlash.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, int8x16_t b, int8_t c)
+foo (int8x16_t m1, int8x16_t m2, int8_t add)
 {
-  return vqrdmlashq_n_s8 (a, b, c);
+  return vqrdmlashq_n_s8 (m1, m2, add);
 }
 
-/* { dg-final { scan-assembler "vqrdmlash.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlash.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, int8x16_t b, int8_t c)
+foo1 (int8x16_t m1, int8x16_t m2, int8_t add)
 {
-  return vqrdmlashq (a, b, c);
+  return vqrdmlashq (m1, m2, add);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqrdmlash.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmlsdhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmlsdhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmlsdhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmlsdhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmlsdhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmlsdhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlsdh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmlsdhq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlsdh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmlsdhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlsdh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmlsdhq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlsdh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmlsdhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlsdh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmlsdhq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlsdh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmlsdhq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmlsdhxq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdhxt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdhxt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmlsdhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdhxt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmlsdhxq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdhxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdhxt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmlsdhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdhxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmlsdhxq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdhxt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmlsdhxt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmlsdhxq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmlsdhxt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlsdhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmlsdhxq_s16 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdhx.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlsdhx.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b)
 {
   return vqrdmlsdhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdhx.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlsdhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmlsdhxq_s32 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdhx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlsdhx.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b)
 {
   return vqrdmlsdhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdhx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmlsdhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmlsdhxq_s8 (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdhx.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmlsdhx.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b)
 {
   return vqrdmlsdhxq (inactive, a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmlsdhx.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrdmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrdmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrdmulht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmulh.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vqrdmulhq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmulh.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vqrdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmulh.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vqrdmulhq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmulh.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqrdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmulh.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vqrdmulhq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmulh.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vqrdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqrdmulhq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqrdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqrdmulhq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqrdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrdmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vqrdmulhq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrdmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vqrdmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshlq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshlq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrshlq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshlq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshlq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrshlq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshlt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b)
 {
   return vqrshlq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vqrshlq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b)
 {
   return vqrshlq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b)
 {
   return vqrshlq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b)
 {
   return vqrshlq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b)
 {
   return vqrshlq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqrshlq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqrshlq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vqrshlq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b)
 {
   return vqrshlq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b)
 {
   return vqrshlq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b)
 {
   return vqrshlq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b)
 {
   return vqrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqrshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrnbt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrnbt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vqrshrnbq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vqrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vqrshrnbq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vqrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnb.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vqrshrnbq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnb.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vqrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnb.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vqrshrnbq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnb.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vqrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnb.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshrntq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshrntq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqrshrntq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqrshrntq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrntt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrntt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vqrshrntq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vqrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vqrshrntq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vqrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vqrshrntq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vqrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrnt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vqrshrntq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrnt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vqrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrnt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrunbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshrunbq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrunbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshrunbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrunbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshrunbq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshrunbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshrunbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshrunbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrunb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b)
 {
   return vqrshrunbq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrunb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b)
 {
   return vqrshrunbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrunb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b)
 {
   return vqrshrunbq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrunb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b)
 {
   return vqrshrunbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshruntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshruntq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshruntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqrshruntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshruntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshruntq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqrshruntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqrshruntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqrshruntt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrunt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b)
 {
   return vqrshruntq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrunt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b)
 {
   return vqrshruntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqrshrunt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b)
 {
   return vqrshruntq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqrshrunt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b)
 {
   return vqrshruntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqrshrunt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vqshlq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vqshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vqshlq_m_n_s32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vqshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vqshlq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vqshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vqshlq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vqshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vqshlq_m_n_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vqshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vqshlq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vqshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vqshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshlq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshlq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqshlq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshlq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshlq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqshlq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vqshlq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vqshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vqshlq_n_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vqshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vqshlq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vqshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
   return vqshlq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
   return vqshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
   return vqshlq_n_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
   return vqshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
   return vqshlq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
   return vqshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b)
 {
   return vqshlq_r_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b)
 {
   return vqshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vqshlq_r_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b)
 {
   return vqshlq_r_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b)
 {
   return vqshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b)
 {
   return vqshlq_r_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b)
 {
   return vqshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b)
 {
   return vqshlq_r_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b)
 {
   return vqshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b)
 {
   return vqshlq_r_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b)
 {
   return vqshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqshlq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqshlq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vqshlq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vqshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b)
 {
   return vqshlq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b)
 {
   return vqshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b)
 {
   return vqshlq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b)
 {
   return vqshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b)
 {
   return vqshlq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b)
 {
   return vqshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlut.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
-  return vqshluq_m_n_s16 (inactive, a, 7, p);
+  return vqshluq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlut.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlut.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
-  return vqshluq_m (inactive, a, 7, p);
+  return vqshluq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlut.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
-  return vqshluq_m_n_s32 (inactive, a, 7, p);
+  return vqshluq_m_n_s32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlut.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlut.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
-  return vqshluq_m (inactive, a, 7, p);
+  return vqshluq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlut.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
-  return vqshluq_m_n_s8 (inactive, a, 7, p);
+  return vqshluq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshlut.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshlut.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
-  return vqshluq_m (inactive, a, 7, p);
+  return vqshluq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshlu.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (int16x8_t a)
 {
-  return vqshluq_n_s16 (a, 7);
+  return vqshluq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshlu.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshlu.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (int16x8_t a)
 {
-  return vqshluq (a, 7);
+  return vqshluq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqshlu.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshlu.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (int32x4_t a)
 {
-  return vqshluq_n_s32 (a, 7);
+  return vqshluq_n_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshlu.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshlu.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (int32x4_t a)
 {
-  return vqshluq (a, 7);
+  return vqshluq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqshlu.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshlu.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (int8x16_t a)
 {
-  return vqshluq_n_s8 (a, 7);
+  return vqshluq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vqshlu.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshlu.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (int8x16_t a)
 {
-  return vqshluq (a, 7);
+  return vqshluq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqshlu.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vqshrnbq_m_n_s16 (a, b, 7, p);
+  return vqshrnbq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vqshrnbq_m (a, b, 7, p);
+  return vqshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vqshrnbq_m_n_s32 (a, b, 11, p);
+  return vqshrnbq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vqshrnbq_m (a, b, 11, p);
+  return vqshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqshrnbq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqshrnbq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrnbt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrnbt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vqshrnbq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vqshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
-  return vqshrnbq_n_s32 (a, b, 2);
+  return vqshrnbq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
-  return vqshrnbq (a, b, 2);
+  return vqshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqshrnb.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnb.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vqshrnbq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnb.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vqshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnb.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
-  return vqshrnbq_n_u32 (a, b, 15);
+  return vqshrnbq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnb.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnb.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
-  return vqshrnbq (a, b, 15);
+  return vqshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vqshrnb.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshrntq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshrntq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqshrntq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqshrntq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrntt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrntt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vqshrntq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vqshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vqshrntq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vqshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vqshrntq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vqshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrnt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vqshrntq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrnt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vqshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrnt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrunbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshrunbq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrunbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshrunbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrunbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshrunbq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshrunbt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshrunbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshrunbt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrunb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b)
 {
   return vqshrunbq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrunb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b)
 {
   return vqshrunbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrunb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b)
 {
   return vqshrunbq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunb.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrunb.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b)
 {
   return vqshrunbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunb.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshruntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshruntq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshruntt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqshruntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshruntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshruntq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqshruntt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqshruntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqshruntt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrunt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int16x8_t b)
 {
   return vqshruntq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrunt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int16x8_t b)
 {
   return vqshruntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqshrunt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32x4_t b)
 {
   return vqshruntq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqshrunt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32x4_t b)
 {
   return vqshruntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vqshrunt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqsubq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqsubq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqsubq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vqsubq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vqsubq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vqsubq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vqsubq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vqsubq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vqsubq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqsubq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqsubq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqsubq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqsubq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqsubq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vqsubq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vqsubt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vqsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vqsubt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqsub.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vqsubq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.s16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqsub.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vqsubq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.s32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqsub.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vqsubq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.s8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqsub.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vqsubq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u16"  }  } */
+/*
+**foo2:
+**	...
+**	vqsub.u16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vqsubq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqsub.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vqsubq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vqsub.u32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vqsubq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqsub.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vqsubq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u8"  }  } */
+/*
+**foo2:
+**	...
+**	vqsub.u8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vqsubq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqsub.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vqsubq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqsub.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vqsubq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqsub.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vqsubq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqsub.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vqsubq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqsub.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vqsubq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vqsub.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vqsubq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vqsub.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vqsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vqsub.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vrev16q_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vrev16q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vrev16q_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vrev16q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev16.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vrev16q_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vrev16.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev16.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vrev16q (a);
 }
 
-/* { dg-final { scan-assembler "vrev16.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev16.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-    return vrev16q_u8 (a);
+  return vrev16q_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vrev16.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev16.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-    return vrev16q (a);
+  return vrev16q (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrev16.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vrev16q_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vrev16q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vrev16q_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev16t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev16t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vrev16q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev32.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrev32q_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrev32.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrev32q (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrev32q_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrev32q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vrev32q_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vrev32q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vrev32q_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vrev32q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vrev32q_m_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vrev32q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vrev32q_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vrev32q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c
@@ -1,21 +1,41 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev32.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vrev32q_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev32.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vrev32q (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev32.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vrev32q_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev32.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vrev32q (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev32.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-    return vrev32q_u16 (a);
+  return vrev32q_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev32.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-    return vrev32q (a);
+  return vrev32q (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrev32.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev32.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-    return vrev32q_u8 (a);
+  return vrev32q_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vrev32.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev32.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-    return vrev32q (a);
+  return vrev32q (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrev32.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrev32q_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrev32q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vrev32q_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vrev32q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vrev32q_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vrev32q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vrev32q_x_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vrev32q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vrev32q_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev32t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev32t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vrev32q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrev64q_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrev64.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrev64q (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrev64q_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrev64.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrev64q (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrev64q_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrev64q_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c
@@ -0,0 +1,17 @@
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, mve_pred16_t p)
+{
+  return vrev64q_m_s16 (a, a, p);
+}
+
+float16x8_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vrev64q_m_f16 (a, a, p);
+}
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vrev64q_m_s16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vrev64q_m_s32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vrev64q_m_s8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vrev64q_m_u16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vrev64q_m_u32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vrev64q_m_u8 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vrev64q_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vrev64q_s16 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev64.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vrev64q (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
   return vrev64q_s32 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev64.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
   return vrev64q (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vrev64q_s8 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev64.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vrev64q (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-    return vrev64q_u16 (a);
+  return vrev64q_u16 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev64.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-    return vrev64q (a);
+  return vrev64q (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrev64.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
-    return vrev64q_u32 (a);
+  return vrev64q_u32 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev64.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
-    return vrev64q (a);
+  return vrev64q (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrev64.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrev64.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-    return vrev64q_u8 (a);
+  return vrev64q_u8 (a);
 }
 
-/* { dg-final { scan-assembler "vrev64.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrev64.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-    return vrev64q (a);
+  return vrev64q (a);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrev64.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrev64q_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrev64q_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
   return vrev64q_x_s16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
   return vrev64q_x_s32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
   return vrev64q_x_s8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
   return vrev64q_x_u16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
   return vrev64q_x_u32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
   return vrev64q_x_u8 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrev64t.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrev64t.8	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
   return vrev64q_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrhadd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vrhaddq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrhadd.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vrhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrhadd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrhaddq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrhadd.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrhadd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vrhaddq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrhadd.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vrhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrhadd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vrhaddq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrhadd.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vrhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrhadd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vrhaddq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrhadd.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vrhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrhadd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vrhaddq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrhadd.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vrhaddq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrhadd.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrhaddt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrhaddt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrhaddq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhat.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
@@ -1,21 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaq_p_u32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhat.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhat.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+{
+  return vrmlaldavhaq_p (1, b, c, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlaldavha.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlaldavhaq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavha.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlaldavha.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlaldavhaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavha.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlaldavha.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint64_t a, uint32x4_t b, uint32x4_t c)
 {
   return vrmlaldavhaq_u32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavha.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlaldavha.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint64_t a, uint32x4_t b, uint32x4_t c)
 {
   return vrmlaldavhaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavha.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vrmlaldavha.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint32x4_t b, uint32x4_t c)
+{
+  return vrmlaldavhaq (1, b, c);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaxq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhaxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlaldavhax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlaldavhaxq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlaldavhax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlaldavhaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhax.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavht.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlaldavhq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavht.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlaldavhq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavht.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrmlaldavhq_p_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavht.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrmlaldavhq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavht.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlaldavh.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrmlaldavhq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlaldavh.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrmlaldavhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlaldavh.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vrmlaldavhq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavh.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlaldavh.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vrmlaldavhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavh.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlaldavhxq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlaldavhxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlaldavhx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrmlaldavhxq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlaldavhx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrmlaldavhxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavhat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlsldavhaq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavhat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlsldavhaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhat.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlsldavha.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlsldavhaq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavha.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlsldavha.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlsldavhaq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavha.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavhaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlsldavhaxq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhaxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavhaxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlsldavhaxq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhaxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlsldavhax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlsldavhaxq_s32 (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhax.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlsldavhax.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c)
 {
   return vrmlsldavhaxq (a, b, c);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhax.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavht.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlsldavhq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavht.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlsldavhq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlsldavh.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrmlsldavhq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlsldavh.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrmlsldavhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavhxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlsldavhxq_p_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhxt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlsldavhxt.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmlsldavhxq_p (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhxt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmlsldavhx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrmlsldavhxq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhx.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmlsldavhx.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrmlsldavhxq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmlsldavhx.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vrmulhq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmulh.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vrmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrmulhq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmulh.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vrmulhq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmulh.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vrmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmulh.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vrmulhq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmulh.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vrmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmulh.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vrmulhq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmulh.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vrmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrmulh.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vrmulhq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrmulh.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vrmulhq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrmulh.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrmulht.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmulht.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vrmulhq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrinta.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrndaq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrinta.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrinta.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrndaq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrinta.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrndaq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrinta.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrinta.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrndaq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndaq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndaq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndaq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndaq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrndaq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrndaq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrndaq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintat.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintat.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrndaq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintm.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrndmq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrintm.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintm.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrndmq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintm.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrndmq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrintm.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintm.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrndmq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndmq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndmq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndmq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndmq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrndmq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrndmq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrndmq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintmt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintmt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrndmq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintn.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrndnq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrintn.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintn.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrndnq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintn.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrndnq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrintn.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintn.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrndnq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndnq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndnq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndnq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrndnq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrndnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrndnq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintnt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintnt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrndnq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintp.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrndpq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrintp.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintp.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrndpq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintp.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrndpq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrintp.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintp.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrndpq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndpq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndpq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndpq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndpq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrndpq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrndpq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrndpq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintpt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintpt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrndpq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintz.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrndq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrintz.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintz.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrndq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintz.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrndq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrintz.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintz.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrndq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrndq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrndq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrndq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintzt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintzt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrndq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintx.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a)
 {
   return vrndxq_f16 (a);
 }
 
-/* { dg-final { scan-assembler "vrintx.f16"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintx.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a)
+{
+  return vrndxq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
@@ -1,13 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrintx.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a)
 {
   return vrndxq_f32 (a);
 }
 
-/* { dg-final { scan-assembler "vrintx.f32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vrintx.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a)
+{
+  return vrndxq (a);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndxq_m_f16 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
 {
   return vrndxq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndxq_m_f32 (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
 {
   return vrndxq_m (inactive, a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, mve_pred16_t p)
 {
   return vrndxq_x_f16 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f16	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, mve_pred16_t p)
 {
   return vrndxq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, mve_pred16_t p)
 {
   return vrndxq_x_f32 (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrintxt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrintxt.f32	q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, mve_pred16_t p)
 {
   return vrndxq_x (a, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vrshlq_m_n (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b)
 {
   return vrshlq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vrshlq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b)
 {
   return vrshlq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b)
 {
   return vrshlq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b)
 {
   return vrshlq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b)
 {
   return vrshlq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vrshlq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vrshlq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vrshlq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b)
 {
   return vrshlq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b)
 {
   return vrshlq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b)
 {
   return vrshlq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b)
 {
   return vrshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vrshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshlq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshlq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vrshlq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshrnbq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshrnbq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrshrnbq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrshrnbq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrshrnbq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrnbt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vrshrnbq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vrshrnbq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vrshrnbq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vrshrnbq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vrshrnbq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnb.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshrntq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
   return vrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshrntq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
   return vrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrshrntq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrshrntq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vrshrntq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrntt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
   return vrshrntq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
   return vrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
   return vrshrntq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
   return vrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
   return vrshrntq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
   return vrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
   return vrshrntq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
   return vrshrntq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vrshrnt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_m_n_s16 (inactive, a, 16, p);
+  return vrshrq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_m (inactive, a, 16, p);
+  return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_m_n_s32 (inactive, a, 32, p);
+  return vrshrq_m_n_s32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_m (inactive, a, 32, p);
+  return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_m_n_s8 (inactive, a, 8, p);
+  return vrshrq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_m (inactive, a, 8, p);
+  return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_m_n_u16 (inactive, a, 16, p);
+  return vrshrq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_m (inactive, a, 16, p);
+  return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_m_n_u32 (inactive, a, 32, p);
+  return vrshrq_m_n_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_m (inactive, a, 32, p);
+  return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_m_n_u8 (inactive, a, 8, p);
+  return vrshrq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_m (inactive, a, 8, p);
+  return vrshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshr.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
-  return vrshrq_n_s16 (a, 16);
+  return vrshrq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vrshr.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshr.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
-  return vrshrq (a, 16);
+  return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrshr.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshr.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
-  return vrshrq_n_s32 (a, 32);
+  return vrshrq_n_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vrshr.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshr.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
-  return vrshrq (a, 32);
+  return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrshr.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshr.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
-  return vrshrq_n_s8 (a, 8);
+  return vrshrq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vrshr.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshr.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
-  return vrshrq (a, 8);
+  return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrshr.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshr.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-  return vrshrq_n_u16 (a, 16);
+  return vrshrq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vrshr.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshr.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-  return vrshrq (a, 16);
+  return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrshr.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshr.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
-  return vrshrq_n_u32 (a, 32);
+  return vrshrq_n_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vrshr.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshr.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
-  return vrshrq (a, 32);
+  return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrshr.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vrshr.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-  return vrshrq_n_u8 (a, 8);
+  return vrshrq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vrshr.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vrshr.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-  return vrshrq (a, 8);
+  return vrshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vrshr.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_x_n_s16 (a, 16, p);
+  return vrshrq_x_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_x (a, 16, p);
+  return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_x_n_s32 (a, 32, p);
+  return vrshrq_x_n_s32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_x (a, 32, p);
+  return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_x_n_s8 (a, 8, p);
+  return vrshrq_x_n_s8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_x (a, 8, p);
+  return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_x_n_u16 (a, 16, p);
+  return vrshrq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, mve_pred16_t p)
 {
-  return vrshrq_x (a, 16, p);
+  return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_x_n_u32 (a, 32, p);
+  return vrshrq_x_n_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, mve_pred16_t p)
 {
-  return vrshrq_x (a, 32, p);
+  return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_x_n_u8 (a, 8, p);
+  return vrshrq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, mve_pred16_t p)
 {
-  return vrshrq_x (a, 8, p);
+  return vrshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vrshrt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vsbciq_m_s32 (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32"  } } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vsbciq_m (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32"  } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
@@ -1,23 +1,57 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vsbciq_m_u32 (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbcit.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
 {
   return vsbciq_m (inactive, a, b, carry_out, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbcit.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsbci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
 {
   return vsbciq_s32 (a, b, carry_out);
 }
 
-/* { dg-final { scan-assembler "vsbci.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsbci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry_out)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry_out)
 {
-  return vsbciq_s32 (a, b, carry_out);
+  return vsbciq (a, b, carry_out);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsbci.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsbci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 {
   return vsbciq_u32 (a, b, carry_out);
 }
 
-/* { dg-final { scan-assembler "vsbci.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsbci.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry_out)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
 {
-  return vsbciq_u32 (a, b, carry_out);
+  return vsbciq (a, b, carry_out);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsbci.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
@@ -1,23 +1,77 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
 {
-    return vsbcq_m_s32 (inactive, a, b, carry, p);
+  return vsbcq_m_s32 (inactive, a, b, carry, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
 {
-    return vsbcq_m (inactive, a, b, carry, p);
+  return vsbcq_m (inactive, a, b, carry, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
@@ -1,22 +1,77 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
 {
-    return vsbcq_m_u32 (inactive, a, b, carry, p);
+  return vsbcq_m_u32 (inactive, a, b, carry, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32"  }  } */
+
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsbct.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)
+foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p)
 {
-    return vsbcq_m (inactive, a, b, carry, p);
+  return vsbcq_m (inactive, a, b, carry, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsbct.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
@@ -1,21 +1,69 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vsbc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, int32x4_t b, unsigned * carry)
+foo (int32x4_t a, int32x4_t b, unsigned *carry)
 {
   return vsbcq_s32 (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vsbc.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vsbc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, int32x4_t b, unsigned * carry)
+foo1 (int32x4_t a, int32x4_t b, unsigned *carry)
 {
   return vsbcq (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vsbc.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
@@ -1,21 +1,69 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vsbc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
 {
   return vsbcq_u32 (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vsbc.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	lsls	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29(?:	@.*|)
+**	...
+**	and	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #536870912(?:	@.*|)
+**	...
+**	orrs	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vmsr	FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vsbc.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+**	vmrs	(?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?:	@.*|)
+**	...
+**	ubfx	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32x4_t b, unsigned * carry)
+foo1 (uint32x4_t a, uint32x4_t b, unsigned *carry)
 {
   return vsbcq (a, b, carry);
 }
 
-/* { dg-final { scan-assembler "vsbc.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo (float16_t a, float16x8_t b)
-{
-  return vsetq_lane (23.26, b, 0);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c
@@ -1,15 +1,53 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16_t a, float16x8_t b)
 {
-    return vsetq_lane_f16 (a, b, 0);
+  return vsetq_lane_f16 (a, b, 1);
+}
+
+
+/*
+**foo1:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16_t a, float16x8_t b)
+{
+  return vsetq_lane (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.16"  }  } */
+/*
+**foo2:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t b)
+{
+  return vsetq_lane (1.1, b, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
 
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo (float32_t a, float32x4_t b)
-{
-    return vsetq_lane (23.34, b, 0);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c
@@ -1,15 +1,53 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32_t a, float32x4_t b)
 {
-    return vsetq_lane_f32 (a, b, 0);
+  return vsetq_lane_f32 (a, b, 1);
+}
+
+
+/*
+**foo1:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32_t a, float32x4_t b)
+{
+  return vsetq_lane (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.32"  }  } */
+/*
+**foo2:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t b)
+{
+  return vsetq_lane (1.1, b, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
 
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c
@@ -1,15 +1,41 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16_t a, int16x8_t b)
 {
-    return vsetq_lane_s16 (a, b, 0);
+  return vsetq_lane_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16_t a, int16x8_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c
@@ -1,15 +1,41 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32_t a, int32x4_t b)
 {
-    return vsetq_lane_s32 (a, b, 0);
+  return vsetq_lane_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32_t a, int32x4_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c
@@ -1,16 +1,41 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
-/* { dg-require-effective-target arm_hard_ok } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-mfloat-abi=hard -O2" } */
+/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int64x2_t
 foo (int64_t a, int64x2_t b)
 {
-    return vsetq_lane_s64 (a, b, 0);
+  return vsetq_lane_s64 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler {vmov\td0, r[1-9]*[0-9], r[1-9]*[0-9]}  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int64x2_t
+foo1 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c
@@ -1,15 +1,41 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov.8	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8_t a, int8x16_t b)
 {
-    return vsetq_lane_s8 (a, b, 0);
+  return vsetq_lane_s8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmov.8	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int8x16_t
+foo1 (int8_t a, int8x16_t b)
+{
+  return vsetq_lane (a, b, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c
@@ -1,15 +1,53 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16_t a, uint16x8_t b)
 {
-    return vsetq_lane_u16 (a, b, 0);
+  return vsetq_lane_u16 (a, b, 1);
+}
+
+
+/*
+**foo1:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16_t a, uint16x8_t b)
+{
+  return vsetq_lane (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.16"  }  } */
+/*
+**foo2:
+**	...
+**	vmov.16	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t b)
+{
+  return vsetq_lane (1, b, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
 
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c
@@ -1,15 +1,53 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32_t a, uint32x4_t b)
 {
-    return vsetq_lane_u32 (a, b, 0);
+  return vsetq_lane_u32 (a, b, 1);
+}
+
+
+/*
+**foo1:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32_t a, uint32x4_t b)
+{
+  return vsetq_lane (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.32"  }  } */
+/*
+**foo2:
+**	...
+**	vmov.32	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t b)
+{
+  return vsetq_lane (1, b, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
 
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c
@@ -1,16 +1,53 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
-/* { dg-require-effective-target arm_hard_ok } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-mfloat-abi=hard -O2" } */
+/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint64x2_t
 foo (uint64_t a, uint64x2_t b)
 {
-    return vsetq_lane_u64 (a, b, 0);
+  return vsetq_lane_u64 (a, b, 1);
+}
+
+
+/*
+**foo1:
+**	...
+**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint64x2_t
+foo1 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane (a, b, 1);
 }
 
-/* { dg-final { scan-assembler {vmov\td0, r[1-9]*[0-9], r[1-9]*[0-9]}  }  } */
+/*
+**foo2:
+**	...
+**	vmov	d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint64x2_t
+foo2 (uint64x2_t b)
+{
+  return vsetq_lane (1, b, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
 
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c
@@ -1,15 +1,53 @@
-/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmov.8	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8_t a, uint8x16_t b)
 {
-    return vsetq_lane_u8 (a, b, 0);
+  return vsetq_lane_u8 (a, b, 1);
+}
+
+
+/*
+**foo1:
+**	...
+**	vmov.8	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint8_t a, uint8x16_t b)
+{
+  return vsetq_lane (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vmov.8"  }  } */
+/*
+**foo2:
+**	...
+**	vmov.8	q[0-9]+\[1\], (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t b)
+{
+  return vsetq_lane (1, b, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
 
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, uint32_t * b, mve_pred16_t p)
+foo (int16x8_t a, uint32_t *b, mve_pred16_t p)
 {
-  return vshlcq_m_s16 (a, b, 32, p);
+  return vshlcq_m_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, uint32_t * b, mve_pred16_t p)
+foo1 (int16x8_t a, uint32_t *b, mve_pred16_t p)
 {
-  return vshlcq_m (a, b, 32, p);
+  return vshlcq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, uint32_t * b, mve_pred16_t p)
+foo (int32x4_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, uint32_t * b, mve_pred16_t p)
+foo1 (int32x4_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, uint32_t * b, mve_pred16_t p)
+foo (int8x16_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m_s8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, uint32_t * b, mve_pred16_t p)
+foo1 (int8x16_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t a, uint32_t * b, mve_pred16_t p)
+foo (uint16x8_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t a, uint32_t * b, mve_pred16_t p)
+foo1 (uint16x8_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32_t * b, mve_pred16_t p)
+foo (uint32x4_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32_t * b, mve_pred16_t p)
+foo1 (uint32x4_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t a, uint32_t * b, mve_pred16_t p)
+foo (uint8x16_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlct	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t a, uint32_t * b, mve_pred16_t p)
+foo1 (uint8x16_t a, uint32_t *b, mve_pred16_t p)
 {
   return vshlcq_m (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlct"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo (int16x8_t a, uint32_t * b)
+foo (int16x8_t a, uint32_t *b)
 {
   return vshlcq_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
-foo1 (int16x8_t a, uint32_t * b)
+foo1 (int16x8_t a, uint32_t *b)
 {
   return vshlcq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo (int32x4_t a, uint32_t * b)
+foo (int32x4_t a, uint32_t *b)
 {
   return vshlcq_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
-foo1 (int32x4_t a, uint32_t * b)
+foo1 (int32x4_t a, uint32_t *b)
 {
   return vshlcq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo (int8x16_t a, uint32_t * b)
+foo (int8x16_t a, uint32_t *b)
 {
   return vshlcq_s8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
-foo1 (int8x16_t a, uint32_t * b)
+foo1 (int8x16_t a, uint32_t *b)
 {
   return vshlcq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo (uint16x8_t a, uint32_t * b)
+foo (uint16x8_t a, uint32_t *b)
 {
   return vshlcq_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
-foo1 (uint16x8_t a, uint32_t * b)
+foo1 (uint16x8_t a, uint32_t *b)
 {
   return vshlcq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo (uint32x4_t a, uint32_t * b)
+foo (uint32x4_t a, uint32_t *b)
 {
   return vshlcq_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
-foo1 (uint32x4_t a, uint32_t * b)
+foo1 (uint32x4_t a, uint32_t *b)
 {
   return vshlcq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo (uint8x16_t a, uint32_t * b)
+foo (uint8x16_t a, uint32_t *b)
 {
   return vshlcq_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshlc	q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
-foo1 (uint8x16_t a, uint32_t * b)
+foo1 (uint8x16_t a, uint32_t *b)
 {
   return vshlcq (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshlc"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vshllbq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vshllbq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vshllbq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vshllbq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vshllbq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vshllbq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vshllbq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vshllbq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a)
 {
   return vshllbq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllb.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a)
 {
   return vshllbq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllb.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a)
 {
   return vshllbq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllb.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a)
 {
   return vshllbq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllb.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a)
 {
   return vshllbq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllb.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a)
 {
   return vshllbq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllb.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a)
 {
   return vshllbq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllb.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a)
 {
   return vshllbq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllb.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-    return vshllbq_x_n_s16 (a, 1, p);
+  return vshllbq_x_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+  return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, mve_pred16_t p)
 {
-    return vshllbq_x_n_s8 (a, 1, p);
+  return vshllbq_x_n_s8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+  return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
-    return vshllbq_x_n_u16 (a, 1, p);
+  return vshllbq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+  return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
-    return vshllbq_x_n_u8 (a, 1, p);
+  return vshllbq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshllbt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshllbt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+  return vshllbq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vshlltq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vshlltq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vshlltq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vshlltq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vshlltq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vshlltq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vshlltq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vshlltq_m (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a)
 {
   return vshlltq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int16x8_t a)
 {
   return vshlltq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a)
 {
   return vshlltq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int8x16_t a)
 {
   return vshlltq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a)
 {
   return vshlltq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint16x8_t a)
 {
   return vshlltq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshllt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a)
 {
   return vshlltq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshllt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint8x16_t a)
 {
   return vshlltq (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshllt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-    return vshlltq_x_n_s16 (a, 1, p);
+  return vshlltq_x_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+  return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int8x16_t a, mve_pred16_t p)
 {
-    return vshlltq_x_n_s8 (a, 1, p);
+  return vshlltq_x_n_s8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+  return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
-    return vshlltq_x_n_u16 (a, 1, p);
+  return vshlltq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+  return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
-    return vshlltq_x_n_u8 (a, 1, p);
+  return vshlltq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlltt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlltt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+  return vshlltq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vshlq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
   return vshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vshlq_m_n_s32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
   return vshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vshlq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
   return vshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vshlq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
   return vshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vshlq_m_n_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
   return vshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vshlq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
   return vshlq_m_n (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
 {
   return vshlq_m_r (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vshlq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vshlq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vshlq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vshlq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vshlq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vshlq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vshlq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
   return vshlq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
   return vshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
-  return vshlq_n_s32 (a, 16);
+  return vshlq_n_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
-  return vshlq_n (a, 16);
+  return vshlq_n (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshl.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
   return vshlq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
   return vshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-  return vshlq_n_u16 (a, 11);
+  return vshlq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-  return vshlq_n (a, 11);
+  return vshlq_n (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshl.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
   return vshlq_n_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
   return vshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
   return vshlq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
   return vshlq_n (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32_t b)
 {
   return vshlq_r_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32_t b)
 {
   return vshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vshlq_r_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int32_t b)
 {
   return vshlq_r_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int32_t b)
 {
   return vshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int32_t b)
 {
   return vshlq_r_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u16	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int32_t b)
 {
   return vshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32_t b)
 {
   return vshlq_r_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u32	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32_t b)
 {
   return vshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int32_t b)
 {
   return vshlq_r_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u8	q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int32_t b)
 {
   return vshlq_r (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vshlq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vshlq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vshlq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.s8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b)
 {
   return vshlq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, int16x8_t b)
 {
   return vshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b)
 {
   return vshlq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, int32x4_t b)
 {
   return vshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b)
 {
   return vshlq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshl.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, int8x16_t b)
 {
   return vshlq (a, b);
 }
 
-/* { dg-final { scan-assembler "vshl.u8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-    return vshlq_x_n_s16 (a, 1, p);
+  return vshlq_x_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+  return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
-    return vshlq_x_n_s32 (a, 1, p);
+  return vshlq_x_n_s32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32x4_t a, mve_pred16_t p)
+{
+  return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
-    return vshlq_x_n_s8 (a, 1, p);
+  return vshlq_x_n_s8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int8x16_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+  return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
-    return vshlq_x_n_u16 (a, 1, p);
+  return vshlq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+  return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, mve_pred16_t p)
 {
-    return vshlq_x_n_u32 (a, 1, p);
+  return vshlq_x_n_u32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, mve_pred16_t p)
+{
+  return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
-    return vshlq_x_n_u8 (a, 1, p);
+  return vshlq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+  return vshlq_x_n (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-    return vshlq_x_s16 (a, b, p);
+  return vshlq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-    return vshlq_x_s32 (a, b, p);
+  return vshlq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-    return vshlq_x_s8 (a, b, p);
+  return vshlq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.s8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+  return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-    return vshlq_x_u16 (a, b, p);
+  return vshlq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-    return vshlq_x_u32 (a, b, p);
+  return vshlq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-    return vshlq_x_u8 (a, b, p);
+  return vshlq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshlt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshlt.u8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+  return vshlq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vshrnbq_m_n_s16 (a, b, 8, p);
+  return vshrnbq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vshrnbq_m (a, b, 8, p);
+  return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vshrnbq_m_n_s32 (a, b, 16, p);
+  return vshrnbq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vshrnbq_m (a, b, 16, p);
+  return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vshrnbq_m_n_u16 (a, b, 8, p);
+  return vshrnbq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vshrnbq_m (a, b, 8, p);
+  return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vshrnbq_m_n_u32 (a, b, 16, p);
+  return vshrnbq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrnbt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vshrnbq_m (a, b, 16, p);
+  return vshrnbq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrnbt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
-  return vshrnbq_n_s16 (a, b, 8);
+  return vshrnbq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnb.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
-  return vshrnbq (a, b, 8);
+  return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnb.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
-  return vshrnbq_n_s32 (a, b, 16);
+  return vshrnbq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnb.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
-  return vshrnbq (a, b, 16);
+  return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnb.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
-  return vshrnbq_n_u16 (a, b, 8);
+  return vshrnbq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnb.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnb.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
-  return vshrnbq (a, b, 8);
+  return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnb.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
-  return vshrnbq_n_u32 (a, b, 16);
+  return vshrnbq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnb.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnb.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
-  return vshrnbq (a, b, 16);
+  return vshrnbq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnb.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vshrntq_m_n_s16 (a, b, 8, p);
+  return vshrntq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vshrntq_m (a, b, 8, p);
+  return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vshrntq_m_n_s32 (a, b, 16, p);
+  return vshrntq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vshrntq_m (a, b, 16, p);
+  return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vshrntq_m_n_u16 (a, b, 8, p);
+  return vshrntq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vshrntq_m (a, b, 8, p);
+  return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vshrntq_m_n_u32 (a, b, 16, p);
+  return vshrntq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrntt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vshrntq_m (a, b, 16, p);
+  return vshrntq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrntt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int16x8_t b)
 {
-  return vshrntq_n_s16 (a, b, 8);
+  return vshrntq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int16x8_t b)
 {
-  return vshrntq (a, b, 8);
+  return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int32x4_t b)
 {
-  return vshrntq_n_s32 (a, b, 16);
+  return vshrntq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int32x4_t b)
 {
-  return vshrntq (a, b, 16);
+  return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint16x8_t b)
 {
-  return vshrntq_n_u16 (a, b, 8);
+  return vshrntq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnt.i16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint16x8_t b)
 {
-  return vshrntq (a, b, 8);
+  return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnt.i16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint32x4_t b)
 {
-  return vshrntq_n_u32 (a, b, 16);
+  return vshrntq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vshrnt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshrnt.i32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint32x4_t b)
 {
-  return vshrntq (a, b, 16);
+  return vshrntq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshrnt.i32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
-  return vshrq_m_n_s16 (inactive, a, 16, p);
+  return vshrq_m_n_s16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p)
 {
-  return vshrq_m (inactive, a, 16, p);
+  return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
-  return vshrq_m_n_s32 (inactive, a, 32, p);
+  return vshrq_m_n_s32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p)
 {
-  return vshrq_m (inactive, a, 32, p);
+  return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
-  return vshrq_m_n_s8 (inactive, a, 8, p);
+  return vshrq_m_n_s8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p)
 {
-  return vshrq_m (inactive, a, 8, p);
+  return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
-  return vshrq_m_n_u16 (inactive, a, 16, p);
+  return vshrq_m_n_u16 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
 {
-  return vshrq_m (inactive, a, 16, p);
+  return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
-  return vshrq_m_n_u32 (inactive, a, 32, p);
+  return vshrq_m_n_u32 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
 {
-  return vshrq_m (inactive, a, 32, p);
+  return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
-  return vshrq_m_n_u8 (inactive, a, 8, p);
+  return vshrq_m_n_u8 (inactive, a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
 {
-  return vshrq_m (inactive, a, 8, p);
+  return vshrq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshr.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a)
 {
-  return vshrq_n_s16 (a, 16);
+  return vshrq_n_s16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshr.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshr.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a)
 {
-  return vshrq (a, 16);
+  return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshr.s16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshr.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a)
 {
-  return vshrq_n_s32 (a, 32);
+  return vshrq_n_s32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshr.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshr.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a)
 {
-  return vshrq (a, 32);
+  return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshr.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshr.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a)
 {
-  return vshrq_n_s8 (a, 8);
+  return vshrq_n_s8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshr.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshr.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a)
 {
-  return vshrq (a, 8);
+  return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshr.s8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshr.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a)
 {
-  return vshrq_n_u16 (a, 16);
+  return vshrq_n_u16 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshr.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshr.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a)
 {
-  return vshrq (a, 16);
+  return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshr.u16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshr.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a)
 {
-  return vshrq_n_u32 (a, 32);
+  return vshrq_n_u32 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshr.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshr.u32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a)
 {
-  return vshrq (a, 32);
+  return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshr.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vshr.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a)
 {
-  return vshrq_n_u8 (a, 8);
+  return vshrq_n_u8 (a, 1);
 }
 
-/* { dg-final { scan-assembler "vshr.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vshr.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a)
 {
-  return vshrq (a, 8);
+  return vshrq (a, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vshr.u8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, mve_pred16_t p)
 {
-    return vshrq_x_n_s16 (a, 16, p);
+  return vshrq_x_n_s16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+  return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, mve_pred16_t p)
 {
-    return vshrq_x_n_s32 (a, 32, p);
+  return vshrq_x_n_s32 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32x4_t a, mve_pred16_t p)
+{
+  return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, mve_pred16_t p)
 {
-    return vshrq_x_n_s8 (a, 8, p);
+  return vshrq_x_n_s8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.s8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.s8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+int8x16_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+  return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, mve_pred16_t p)
 {
-    return vshrq_x_n_u16 (a, 16, p);
+  return vshrq_x_n_u16 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+  return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, mve_pred16_t p)
 {
-    return vshrq_x_n_u8 (a, 8, p);
+  return vshrq_x_n_u8 (a, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vshrt.u8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vshrt.u8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+  return vshrq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vsliq_m_n_s16 (a, b, 15, p);
+  return vsliq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vsliq_m (a, b, 15, p);
+  return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vsliq_m_n_s32 (a, b, 31, p);
+  return vsliq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vsliq_m (a, b, 31, p);
+  return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-  return vsliq_m_n_s8 (a, b, 7, p);
+  return vsliq_m_n_s8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-  return vsliq_m (a, b, 7, p);
+  return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vsliq_m_n_u16 (a, b, 15, p);
+  return vsliq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vsliq_m (a, b, 15, p);
+  return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vsliq_m_n_u32 (a, b, 31, p);
+  return vsliq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vsliq_m (a, b, 31, p);
+  return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
-  return vsliq_m_n_u8 (a, b, 7, p);
+  return vsliq_m_n_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vslit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
-  return vsliq_m (a, b, 7, p);
+  return vsliq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vslit.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsli.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
-  return vsliq_n_s16 (a, b, 15);
+  return vsliq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsli.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsli.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
-  return vsliq (a, b, 15);
+  return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsli.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsli.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
-  return vsliq_n_s32 (a, b, 31);
+  return vsliq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsli.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsli.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
-  return vsliq (a, b, 31);
+  return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsli.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsli.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
-  return vsliq_n_s8 (a, b, 7);
+  return vsliq_n_s8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsli.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsli.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
-  return vsliq (a, b, 7);
+  return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsli.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsli.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
-  return vsliq_n_u16 (a, b, 15);
+  return vsliq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsli.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsli.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
-  return vsliq (a, b, 15);
+  return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsli.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsli.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
-  return vsliq_n_u32 (a, b, 31);
+  return vsliq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsli.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsli.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
-  return vsliq (a, b, 31);
+  return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsli.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsli.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
-  return vsliq_n_u8 (a, b, 7);
+  return vsliq_n_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsli.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsli.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
-  return vsliq (a, b, 7);
+  return vsliq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsli.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vsriq_m_n_s16 (a, b, 4, p);
+  return vsriq_m_n_s16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-  return vsriq_m (a, b, 4, p);
+  return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vsriq_m_n_s32 (a, b, 2, p);
+  return vsriq_m_n_s32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-  return vsriq_m (a, b, 2, p);
+  return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-  return vsriq_m_n_s8 (a, b, 4, p);
+  return vsriq_m_n_s8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-  return vsriq_m (a, b, 4, p);
+  return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vsriq_m_n_u16 (a, b, 4, p);
+  return vsriq_m_n_u16 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
-  return vsriq_m (a, b, 4, p);
+  return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vsriq_m_n_u32 (a, b, 4, p);
+  return vsriq_m_n_u32 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
-  return vsriq_m (a, b, 4, p);
+  return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
-  return vsriq_m_n_u8 (a, b, 4, p);
+  return vsriq_m_n_u8 (a, b, 1, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsrit.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsrit.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
-  return vsriq_m (a, b, 4, p);
+  return vsriq_m (a, b, 1, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsri.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
-  return vsriq_n_s16 (a, b, 4);
+  return vsriq_n_s16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsri.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsri.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
-  return vsriq (a, b, 4);
+  return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsri.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsri.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
-  return vsriq_n_s32 (a, b, 4);
+  return vsriq_n_s32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsri.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsri.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
-  return vsriq (a, b, 4);
+  return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsri.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsri.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
-  return vsriq_n_s8 (a, b, 4);
+  return vsriq_n_s8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsri.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsri.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
-  return vsriq (a, b, 4);
+  return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsri.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsri.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
-  return vsriq_n_u16 (a, b, 4);
+  return vsriq_n_u16 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsri.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsri.16	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
-  return vsriq (a, b, 4);
+  return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsri.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsri.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
-  return vsriq_n_u32 (a, b, 4);
+  return vsriq_n_u32 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsri.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsri.32	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
-  return vsriq (a, b, 4);
+  return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsri.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsri.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
-  return vsriq_n_u8 (a, b, 4);
+  return vsriq_n_u8 (a, b, 1);
 }
 
-/* { dg-final { scan-assembler "vsri.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsri.8	q[0-9]+, q[0-9]+, #[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
-  return vsriq (a, b, 4);
+  return vsriq (a, b, 1);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vsri.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
@@ -1,25 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-void
-foo (float16_t * addr, float16x8_t value)
-{
-  vst1q_f16 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * addr, float16x8_t value)
+foo (float16_t *base, float16x8_t value)
 {
-  vst1q (addr, value);
+  return vst1q_f16 (base, value);
 }
 
-/* { dg-final { scan-assembler-times "vstrh.16" 2 }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo2 (float16_t a, float16x8_t x)
+foo1 (float16_t *base, float16x8_t value)
 {
-  vst1q (&a, x);
+  return vst1q (base, value);
 }
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * addr, float32x4_t value)
+foo (float32_t *base, float32x4_t value)
 {
-  vst1q_f32 (addr, value);
+  return vst1q_f32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * addr, float32x4_t value)
+foo1 (float32_t *base, float32x4_t value)
 {
-  vst1q (addr, value);
+  return vst1q (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo (float16_t *base, float16x8_t value, mve_pred16_t p)
 {
-  vst1q_p_f16 (addr, value, p);
+  return vst1q_p_f16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo1 (float16_t *base, float16x8_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo (float32_t *base, float32x4_t value, mve_pred16_t p)
 {
-  vst1q_p_f32 (addr, value, p);
+  return vst1q_p_f32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo1 (float32_t *base, float32x4_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo (int16_t *base, int16x8_t value, mve_pred16_t p)
 {
-  vst1q_p_s16 (addr, value, p);
+  return vst1q_p_s16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo1 (int16_t *base, int16x8_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo (int32_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vst1q_p_s32 (addr, value, p);
+  return vst1q_p_s32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo1 (int32_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo (int8_t *base, int8x16_t value, mve_pred16_t p)
 {
-  vst1q_p_s8 (addr, value, p);
+  return vst1q_p_s8 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo1 (int8_t *base, int8x16_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo (uint16_t *base, uint16x8_t value, mve_pred16_t p)
 {
-  vst1q_p_u16 (addr, value, p);
+  return vst1q_p_u16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint16x8_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo (uint32_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vst1q_p_u32 (addr, value, p);
+  return vst1q_p_u32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo (uint8_t *base, uint8x16_t value, mve_pred16_t p)
 {
-  vst1q_p_u8 (addr, value, p);
+  return vst1q_p_u8 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint8x16_t value, mve_pred16_t p)
 {
-  vst1q_p (addr, value, p);
+  return vst1q_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
@@ -1,25 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-void
-foo (int16_t * addr, int16x8_t value)
-{
-  vst1q_s16 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int16x8_t value)
+foo (int16_t *base, int16x8_t value)
 {
-  vst1q (addr, value);
+  return vst1q_s16 (base, value);
 }
 
-/* { dg-final { scan-assembler-times "vstrh.16" 2 }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo2 (int16_t a, int16x8_t x)
+foo1 (int16_t *base, int16x8_t value)
 {
-  vst1q (&a, x);
+  return vst1q (base, value);
 }
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * addr, int32x4_t value)
+foo (int32_t *base, int32x4_t value)
 {
-  vst1q_s32 (addr, value);
+  return vst1q_s32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * addr, int32x4_t value)
+foo1 (int32_t *base, int32x4_t value)
 {
-  vst1q (addr, value);
+  return vst1q (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
@@ -1,25 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-void
-foo (int8_t * addr, int8x16_t value)
-{
-  vst1q_s8 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int8x16_t value)
+foo (int8_t *base, int8x16_t value)
 {
-  vst1q (addr, value);
+  return vst1q_s8 (base, value);
 }
 
-/* { dg-final { scan-assembler-times "vstrb.8" 2 }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo2 (int8_t a, int8x16_t x)
+foo1 (int8_t *base, int8x16_t value)
 {
-  vst1q (&a, x);
+  return vst1q (base, value);
 }
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
@@ -1,25 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-void
-foo (uint16_t * addr, uint16x8_t value)
-{
-  vst1q_u16 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint16x8_t value)
+foo (uint16_t *base, uint16x8_t value)
 {
-  vst1q (addr, value);
+  return vst1q_u16 (base, value);
 }
 
-/* { dg-final { scan-assembler-times "vstrh.16" 2 }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo2 (uint16_t a, uint16x8_t x)
+foo1 (uint16_t *base, uint16x8_t value)
 {
-  vst1q (&a, x);
+  return vst1q (base, value);
 }
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * addr, uint32x4_t value)
+foo (uint32_t *base, uint32x4_t value)
 {
-  vst1q_u32 (addr, value);
+  return vst1q_u32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * addr, uint32x4_t value)
+foo1 (uint32_t *base, uint32x4_t value)
 {
-  vst1q (addr, value);
+  return vst1q (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
@@ -1,25 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
-void
-foo (uint8_t * addr, uint8x16_t value)
-{
-  vst1q_u8 (addr, value);
-}
+#ifdef __cplusplus
+extern "C" {
+#endif
 
+/*
+**foo:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint8x16_t value)
+foo (uint8_t *base, uint8x16_t value)
 {
-  vst1q (addr, value);
+  return vst1q_u8 (base, value);
 }
 
-/* { dg-final { scan-assembler-times "vstrb.8" 2 }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo2 (uint8_t a, uint8x16_t x)
+foo1 (uint8_t *base, uint8x16_t value)
 {
-  vst1q (&a, x);
+  return vst1q (base, value);
 }
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * addr, float16x8x2_t value)
+foo (float16_t *addr, float16x8x2_t value)
 {
-  vst2q_f16 (addr, value);
+  return vst2q_f16 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.16"  }  } */
-/* { dg-final { scan-assembler "vst21.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * addr, float16x8x2_t value)
+foo1 (float16_t *addr, float16x8x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * addr, float32x4x2_t value)
+foo (float32_t *addr, float32x4x2_t value)
 {
-  vst2q_f32 (addr, value);
+  return vst2q_f32 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.32"  }  } */
-/* { dg-final { scan-assembler "vst21.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * addr, float32x4x2_t value)
+foo1 (float32_t *addr, float32x4x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * addr, int16x8x2_t value)
+foo (int16_t *addr, int16x8x2_t value)
 {
-  vst2q_s16 (addr, value);
+  return vst2q_s16 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.16"  }  } */
-/* { dg-final { scan-assembler "vst21.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int16x8x2_t value)
+foo1 (int16_t *addr, int16x8x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * addr, int32x4x2_t value)
+foo (int32_t *addr, int32x4x2_t value)
 {
-  vst2q_s32 (addr, value);
+  return vst2q_s32 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.32"  }  } */
-/* { dg-final { scan-assembler "vst21.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * addr, int32x4x2_t value)
+foo1 (int32_t *addr, int32x4x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int8x16x2_t value)
+foo (int8_t *addr, int8x16x2_t value)
 {
-  vst2q_s8 (addr, value);
+  return vst2q_s8 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.8"  }  } */
-/* { dg-final { scan-assembler "vst21.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int8x16x2_t value)
+foo1 (int8_t *addr, int8x16x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * addr, uint16x8x2_t value)
+foo (uint16_t *addr, uint16x8x2_t value)
 {
-  vst2q_u16 (addr, value);
+  return vst2q_u16 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.16"  }  } */
-/* { dg-final { scan-assembler "vst21.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.16	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint16x8x2_t value)
+foo1 (uint16_t *addr, uint16x8x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * addr, uint32x4x2_t value)
+foo (uint32_t *addr, uint32x4x2_t value)
 {
-  vst2q_u32 (addr, value);
+  return vst2q_u32 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.32"  }  } */
-/* { dg-final { scan-assembler "vst21.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.32	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * addr, uint32x4x2_t value)
+foo1 (uint32_t *addr, uint32x4x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c
@@ -1,22 +1,45 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint8x16x2_t value)
+foo (uint8_t *addr, uint8x16x2_t value)
 {
-  vst2q_u8 (addr, value);
+  return vst2q_u8 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst20.8"  }  } */
-/* { dg-final { scan-assembler "vst21.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst20.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+**	vst21.8	{q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint8x16x2_t value)
+foo1 (uint8_t *addr, uint8x16x2_t value)
 {
-  vst2q (addr, value);
+  return vst2q (addr, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vst20.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (float16_t * addr, float16x8x4_t value)
+foo (float16_t *addr, float16x8x4_t value)
 {
-  vst4q_f16 (addr, value);
+  return vst4q_f16 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.16"  }  } */
-/* { dg-final { scan-assembler "vst41.16"  }  } */
-/* { dg-final { scan-assembler "vst42.16"  }  } */
-/* { dg-final { scan-assembler "vst43.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (float16_t * addr, float16x8x4_t value)
+foo1 (float16_t *addr, float16x8x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.16"  }  } */
-/* { dg-final { scan-assembler "vst41.16"  }  } */
-/* { dg-final { scan-assembler "vst42.16"  }  } */
-/* { dg-final { scan-assembler "vst43.16"  }  } */
-
-void
-foo2 (float16_t * addr, float16x8x4_t value)
-{
-  vst4q_f16 (addr, value);
-  addr += 32;
-  vst4q_f16 (addr, value);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (float32_t * addr, float32x4x4_t value)
+foo (float32_t *addr, float32x4x4_t value)
 {
-  vst4q_f32 (addr, value);
+  return vst4q_f32 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.32"  }  } */
-/* { dg-final { scan-assembler "vst41.32"  }  } */
-/* { dg-final { scan-assembler "vst42.32"  }  } */
-/* { dg-final { scan-assembler "vst43.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (float32_t * addr, float32x4x4_t value)
+foo1 (float32_t *addr, float32x4x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.32"  }  } */
-/* { dg-final { scan-assembler "vst41.32"  }  } */
-/* { dg-final { scan-assembler "vst42.32"  }  } */
-/* { dg-final { scan-assembler "vst43.32"  }  } */
-
-void
-foo2 (float32_t * addr, float32x4x4_t value)
-{
-  vst4q_f32 (addr, value);
-  addr += 16;
-  vst4q_f32 (addr, value);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (int16_t * addr, int16x8x4_t value)
+foo (int16_t *addr, int16x8x4_t value)
 {
-  vst4q_s16 (addr, value);
+  return vst4q_s16 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.16"  }  } */
-/* { dg-final { scan-assembler "vst41.16"  }  } */
-/* { dg-final { scan-assembler "vst42.16"  }  } */
-/* { dg-final { scan-assembler "vst43.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (int16_t * addr, int16x8x4_t value)
+foo1 (int16_t *addr, int16x8x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.16"  }  } */
-/* { dg-final { scan-assembler "vst41.16"  }  } */
-/* { dg-final { scan-assembler "vst42.16"  }  } */
-/* { dg-final { scan-assembler "vst43.16"  }  } */
-
-void
-foo2 (int16_t * addr, int16x8x4_t value)
-{
-  vst4q_s16 (addr, value);
-  addr += 32;
-  vst4q_s16 (addr, value);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (int32_t * addr, int32x4x4_t value)
+foo (int32_t *addr, int32x4x4_t value)
 {
-  vst4q_s32 (addr, value);
+  return vst4q_s32 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.32"  }  } */
-/* { dg-final { scan-assembler "vst41.32"  }  } */
-/* { dg-final { scan-assembler "vst42.32"  }  } */
-/* { dg-final { scan-assembler "vst43.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (int32_t * addr, int32x4x4_t value)
+foo1 (int32_t *addr, int32x4x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.32"  }  } */
-/* { dg-final { scan-assembler "vst41.32"  }  } */
-/* { dg-final { scan-assembler "vst42.32"  }  } */
-/* { dg-final { scan-assembler "vst43.32"  }  } */
-
-void
-foo2 (int32_t * addr, int32x4x4_t value)
-{
-  vst4q_s32 (addr, value);
-  addr += 16;
-  vst4q_s32 (addr, value); 
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (int8_t * addr, int8x16x4_t value)
+foo (int8_t *addr, int8x16x4_t value)
 {
-  vst4q_s8 (addr, value);
+  return vst4q_s8 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.8"  }  } */
-/* { dg-final { scan-assembler "vst41.8"  }  } */
-/* { dg-final { scan-assembler "vst42.8"  }  } */
-/* { dg-final { scan-assembler "vst43.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (int8_t * addr, int8x16x4_t value)
+foo1 (int8_t *addr, int8x16x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.8"  }  } */
-/* { dg-final { scan-assembler "vst41.8"  }  } */
-/* { dg-final { scan-assembler "vst42.8"  }  } */
-/* { dg-final { scan-assembler "vst43.8"  }  } */
-
-void
-foo2 (int8_t * addr, int8x16x4_t value)
-{
-  vst4q_s8 (addr, value);
-  addr += 16*4;
-  vst4q_s8 (addr, value);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (uint16_t * addr, uint16x8x4_t value)
+foo (uint16_t *addr, uint16x8x4_t value)
 {
-  vst4q_u16 (addr, value);
+  return vst4q_u16 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.16"  }  } */
-/* { dg-final { scan-assembler "vst41.16"  }  } */
-/* { dg-final { scan-assembler "vst42.16"  }  } */
-/* { dg-final { scan-assembler "vst43.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.16	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint16x8x4_t value)
+foo1 (uint16_t *addr, uint16x8x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.16"  }  } */
-/* { dg-final { scan-assembler "vst41.16"  }  } */
-/* { dg-final { scan-assembler "vst42.16"  }  } */
-/* { dg-final { scan-assembler "vst43.16"  }  } */
-
-void
-foo2 (uint16_t * addr, uint16x8x4_t value)
-{
-  vst4q_u16 (addr, value);
-  addr += 32;
-  vst4q_u16 (addr, value);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (uint32_t * addr, uint32x4x4_t value)
+foo (uint32_t *addr, uint32x4x4_t value)
 {
-  vst4q_u32 (addr, value);
+  return vst4q_u32 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.32"  }  } */
-/* { dg-final { scan-assembler "vst41.32"  }  } */
-/* { dg-final { scan-assembler "vst42.32"  }  } */
-/* { dg-final { scan-assembler "vst43.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.32	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (uint32_t * addr, uint32x4x4_t value)
+foo1 (uint32_t *addr, uint32x4x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.32"  }  } */
-/* { dg-final { scan-assembler "vst41.32"  }  } */
-/* { dg-final { scan-assembler "vst42.32"  }  } */
-/* { dg-final { scan-assembler "vst43.32"  }  } */
-
-void
-foo2 (uint32_t * addr, uint32x4x4_t value)
-{
-  vst4q_u32 (addr, value);
-  addr += 16;
-  vst4q_u32 (addr, value); 
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c
@@ -1,37 +1,47 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vst40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo (uint8_t * addr, uint8x16x4_t value)
+foo (uint8_t *addr, uint8x16x4_t value)
 {
-  vst4q_u8 (addr, value);
+  return vst4q_u8 (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.8"  }  } */
-/* { dg-final { scan-assembler "vst41.8"  }  } */
-/* { dg-final { scan-assembler "vst42.8"  }  } */
-/* { dg-final { scan-assembler "vst43.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vst40.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst41.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst42.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	vst43.8	{q[0-9+], q[0-9+], q[0-9+], q[0-9+]}, \[r[0-9+]\]
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint8x16x4_t value)
+foo1 (uint8_t *addr, uint8x16x4_t value)
 {
-  vst4q (addr, value);
+  return vst4q (addr, value);
 }
 
-/* { dg-final { scan-assembler "vst40.8"  }  } */
-/* { dg-final { scan-assembler "vst41.8"  }  } */
-/* { dg-final { scan-assembler "vst42.8"  }  } */
-/* { dg-final { scan-assembler "vst43.8"  }  } */
-
-void
-foo2 (uint8_t * addr, uint8x16x4_t value)
-{
-  vst4q_u8 (addr, value);
-  addr += 16*4;
-  vst4q_u8 (addr, value);
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!}  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int16x8_t value, mve_pred16_t p)
+foo (int8_t *base, int16x8_t value, mve_pred16_t p)
 {
-  vstrbq_p_s16 (addr, value, p);
+  return vstrbq_p_s16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int16x8_t value, mve_pred16_t p)
+foo1 (int8_t *base, int16x8_t value, mve_pred16_t p)
 {
-  vstrbq_p (addr, value, p);
+  return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int32x4_t value, mve_pred16_t p)
+foo (int8_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vstrbq_p_s32 (addr, value, p);
+  return vstrbq_p_s32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int32x4_t value, mve_pred16_t p)
+foo1 (int8_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vstrbq_p (addr, value, p);
+  return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo (int8_t *base, int8x16_t value, mve_pred16_t p)
 {
-  vstrbq_p_s8 (addr, value, p);
+  return vstrbq_p_s8 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int8x16_t value, mve_pred16_t p)
+foo1 (int8_t *base, int8x16_t value, mve_pred16_t p)
 {
-  vstrbq_p (addr, value, p);
+  return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint16x8_t value, mve_pred16_t p)
+foo (uint8_t *base, uint16x8_t value, mve_pred16_t p)
 {
-  vstrbq_p_u16 (addr, value, p);
+  return vstrbq_p_u16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint16x8_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint16x8_t value, mve_pred16_t p)
 {
-  vstrbq_p (addr, value, p);
+  return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint32x4_t value, mve_pred16_t p)
+foo (uint8_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vstrbq_p_u32 (addr, value, p);
+  return vstrbq_p_u32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint32x4_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vstrbq_p (addr, value, p);
+  return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo (uint8_t *base, uint8x16_t value, mve_pred16_t p)
 {
-  vstrbq_p_u8 (addr, value, p);
+  return vstrbq_p_u8 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint8x16_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint8x16_t value, mve_pred16_t p)
 {
-  vstrbq_p (addr, value, p);
+  return vstrbq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int16x8_t value)
+foo (int8_t *base, int16x8_t value)
 {
-  vstrbq_s16 (addr, value);
+  return vstrbq_s16 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int16x8_t value)
+foo1 (int8_t *base, int16x8_t value)
 {
-  vstrbq (addr, value);
+  return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int32x4_t value)
+foo (int8_t *base, int32x4_t value)
 {
-  vstrbq_s32 (addr, value);
+  return vstrbq_s32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int32x4_t value)
+foo1 (int8_t *base, int32x4_t value)
 {
-  vstrbq (addr, value);
+  return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * addr, int8x16_t value)
+foo (int8_t *base, int8x16_t value)
 {
-  vstrbq_s8 (addr, value);
+  return vstrbq_s8 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * addr, int8x16_t value)
+foo1 (int8_t *base, int8x16_t value)
 {
-  vstrbq (addr, value);
+  return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p_s16 (base, offset, value, p);
+  return vstrbq_scatter_offset_p_s16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo1 (int8_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p (base, offset, value, p);
+  return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p_s32 (base, offset, value, p);
+  return vstrbq_scatter_offset_p_s32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int8_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p (base, offset, value, p);
+  return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
+foo (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p_s8 (base, offset, value, p);
+  return vstrbq_scatter_offset_p_s8 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
+foo1 (int8_t *base, uint8x16_t offset, int8x16_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p (base, offset, value, p);
+  return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p_u16 (base, offset, value, p);
+  return vstrbq_scatter_offset_p_u16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p (base, offset, value, p);
+  return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p_u32 (base, offset, value, p);
+  return vstrbq_scatter_offset_p_u32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p (base, offset, value, p);
+  return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
+foo (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p_u8 (base, offset, value, p);
+  return vstrbq_scatter_offset_p_u8 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
+foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value, mve_pred16_t p)
 {
-  vstrbq_scatter_offset_p (base, offset, value, p);
+  return vstrbq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrbt.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * base, uint16x8_t offset, int16x8_t value)
+foo (int8_t *base, uint16x8_t offset, int16x8_t value)
 {
-  vstrbq_scatter_offset_s16 (base, offset, value);
+  return vstrbq_scatter_offset_s16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * base, uint16x8_t offset, int16x8_t value)
+foo1 (int8_t *base, uint16x8_t offset, int16x8_t value)
 {
-  vstrbq_scatter_offset (base, offset, value);
+  return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * base, uint32x4_t offset, int32x4_t value)
+foo (int8_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrbq_scatter_offset_s32 (base, offset, value);
+  return vstrbq_scatter_offset_s32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int8_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrbq_scatter_offset (base, offset, value);
+  return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int8_t * base, uint8x16_t offset, int8x16_t value)
+foo (int8_t *base, uint8x16_t offset, int8x16_t value)
 {
-  vstrbq_scatter_offset_s8 (base, offset, value);
+  return vstrbq_scatter_offset_s8 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int8_t * base, uint8x16_t offset, int8x16_t value)
+foo1 (int8_t *base, uint8x16_t offset, int8x16_t value)
 {
-  vstrbq_scatter_offset (base, offset, value);
+  return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * base, uint16x8_t offset, uint16x8_t value)
+foo (uint8_t *base, uint16x8_t offset, uint16x8_t value)
 {
-  vstrbq_scatter_offset_u16 (base, offset, value);
+  return vstrbq_scatter_offset_u16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * base, uint16x8_t offset, uint16x8_t value)
+foo1 (uint8_t *base, uint16x8_t offset, uint16x8_t value)
 {
-  vstrbq_scatter_offset (base, offset, value);
+  return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint8_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrbq_scatter_offset_u32 (base, offset, value);
+  return vstrbq_scatter_offset_u32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint8_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrbq_scatter_offset (base, offset, value);
+  return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * base, uint8x16_t offset, uint8x16_t value)
+foo (uint8_t *base, uint8x16_t offset, uint8x16_t value)
 {
-  vstrbq_scatter_offset_u8 (base, offset, value);
+  return vstrbq_scatter_offset_u8 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * base, uint8x16_t offset, uint8x16_t value)
+foo1 (uint8_t *base, uint8x16_t offset, uint8x16_t value)
 {
-  vstrbq_scatter_offset (base, offset, value);
+  return vstrbq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint16x8_t value)
+foo (uint8_t *base, uint16x8_t value)
 {
-  vstrbq_u16 (addr, value);
+  return vstrbq_u16 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint16x8_t value)
+foo1 (uint8_t *base, uint16x8_t value)
 {
-  vstrbq (addr, value);
+  return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint32x4_t value)
+foo (uint8_t *base, uint32x4_t value)
 {
-  vstrbq_u32 (addr, value);
+  return vstrbq_u32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint32x4_t value)
+foo1 (uint8_t *base, uint32x4_t value)
 {
-  vstrbq (addr, value);
+  return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint8_t * addr, uint8x16_t value)
+foo (uint8_t *base, uint8x16_t value)
 {
-  vstrbq_u8 (addr, value);
+  return vstrbq_u8 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrb.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint8_t * addr, uint8x16_t value)
+foo1 (uint8_t *base, uint8x16_t value)
 {
-  vstrbq (addr, value);
+  return vstrbq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrb.8"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo (uint64x2_t addr, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_p_s64 (addr, 8, value, p);
+  return vstrdq_scatter_base_p_s64 (addr, 0, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrdt.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t addr, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_p (addr, 8, value, p);
+  return vstrdq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrdt.u64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64x2_t addr, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_p_u64 (addr, 8, value, p);
+  return vstrdq_scatter_base_p_u64 (addr, 0, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrdt.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t addr, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_p (addr, 8, value, p);
+  return vstrdq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrdt.u64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t addr, const int offset, int64x2_t value)
+foo (uint64x2_t addr, int64x2_t value)
 {
-  vstrdq_scatter_base_s64 (addr, 1016, value);
+  return vstrdq_scatter_base_s64 (addr, 0, value);
 }
 
-/* { dg-final { scan-assembler "vstrd.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t addr, const int offset, int64x2_t value)
+foo1 (uint64x2_t addr, int64x2_t value)
 {
-  vstrdq_scatter_base (addr, 1016, value);
+  return vstrdq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrd.u64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t addr, const int offset, uint64x2_t value)
+foo (uint64x2_t addr, uint64x2_t value)
 {
-  vstrdq_scatter_base_u64 (addr, 8, value);
+  return vstrdq_scatter_base_u64 (addr, 0, value);
 }
 
-/* { dg-final { scan-assembler "vstrd.u64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t addr, const int offset, uint64x2_t value)
+foo1 (uint64x2_t addr, uint64x2_t value)
 {
-  vstrdq_scatter_base (addr, 8, value);
+  return vstrdq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrd.u64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c
@@ -1,19 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo (uint64x2_t *addr, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_wb_p_s64 (addr, 8, value, p);
+  return vstrdq_scatter_base_wb_p_s64 (addr, 0, value, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t *addr, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_wb_p (addr, 8, value, p);
+  return vstrdq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c
@@ -1,19 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64x2_t *addr, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_wb_p_u64 (addr, 8, value, p);
+  return vstrdq_scatter_base_wb_p_u64 (addr, 0, value, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64x2_t *addr, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_base_wb_p (addr, 8, value, p);
+  return vstrdq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c
@@ -1,19 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t * addr, const int offset, int64x2_t value)
+foo (uint64x2_t *addr, int64x2_t value)
 {
-  vstrdq_scatter_base_wb_s64 (addr, 8, value);
+  return vstrdq_scatter_base_wb_s64 (addr, 0, value);
 }
 
+
+/*
+**foo1:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t * addr, const int offset, int64x2_t value)
+foo1 (uint64x2_t *addr, int64x2_t value)
 {
-  vstrdq_scatter_base_wb (addr, 8, value);
+  return vstrdq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c
@@ -1,19 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint64x2_t * addr, const int offset, uint64x2_t value)
+foo (uint64x2_t *addr, uint64x2_t value)
 {
-  vstrdq_scatter_base_wb_u64 (addr, 8, value);
+  return vstrdq_scatter_base_wb_u64 (addr, 0, value);
 }
 
+
+/*
+**foo1:
+**	...
+**	vstrd.u64	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64x2_t * addr, const int offset, uint64x2_t value)
+foo1 (uint64x2_t *addr, uint64x2_t value)
 {
-  vstrdq_scatter_base_wb (addr, 8, value);
+  return vstrdq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_offset_p_s64 (base, offset, value, p);
+  return vstrdq_scatter_offset_p_s64 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_offset_p (base, offset, value, p);
+  return vstrdq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_offset_p_u64 (base, offset, value, p);
+  return vstrdq_scatter_offset_p_u64 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_offset_p (base, offset, value, p);
+  return vstrdq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value)
 {
-  vstrdq_scatter_offset_s64 (base, offset, value);
+  return vstrdq_scatter_offset_s64 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value)
 {
-  vstrdq_scatter_offset (base, offset, value);
+  return vstrdq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value)
 {
-  vstrdq_scatter_offset_u64 (base, offset, value);
+  return vstrdq_scatter_offset_u64 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value)
 {
-  vstrdq_scatter_offset (base, offset, value);
+  return vstrdq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p);
+  return vstrdq_scatter_shifted_offset_p_s64 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p);
+  return vstrdq_scatter_shifted_offset_p_u64 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrdt.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value, mve_pred16_t p)
 {
-  vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrdq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrdt.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo (int64_t *base, uint64x2_t offset, int64x2_t value)
 {
-  vstrdq_scatter_shifted_offset_s64 (base, offset, value);
+  return vstrdq_scatter_shifted_offset_s64 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int64_t * base, uint64x2_t offset, int64x2_t value)
+foo1 (int64_t *base, uint64x2_t offset, int64x2_t value)
 {
-  vstrdq_scatter_shifted_offset (base, offset, value);
+  return vstrdq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo (uint64_t *base, uint64x2_t offset, uint64x2_t value)
 {
-  vstrdq_scatter_shifted_offset_u64 (base, offset, value);
+  return vstrdq_scatter_shifted_offset_u64 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrd.64	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #3\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint64_t * base, uint64x2_t offset, uint64x2_t value)
+foo1 (uint64_t *base, uint64x2_t offset, uint64x2_t value)
 {
-  vstrdq_scatter_shifted_offset (base, offset, value);
+  return vstrdq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrd.64"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * addr, float16x8_t value)
+foo (float16_t *base, float16x8_t value)
 {
-  vstrhq_f16 (addr, value);
+  return vstrhq_f16 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * addr, float16x8_t value)
+foo1 (float16_t *base, float16x8_t value)
 {
-  vstrhq (addr, value);
+  return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo (float16_t *base, float16x8_t value, mve_pred16_t p)
 {
-  vstrhq_p_f16 (addr, value, p);
+  return vstrhq_p_f16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * addr, float16x8_t value, mve_pred16_t p)
+foo1 (float16_t *base, float16x8_t value, mve_pred16_t p)
 {
-  vstrhq_p (addr, value, p);
+  return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo (int16_t *base, int16x8_t value, mve_pred16_t p)
 {
-  vstrhq_p_s16 (addr, value, p);
+  return vstrhq_p_s16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int16x8_t value, mve_pred16_t p)
+foo1 (int16_t *base, int16x8_t value, mve_pred16_t p)
 {
-  vstrhq_p (addr, value, p);
+  return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * addr, int32x4_t value, mve_pred16_t p)
+foo (int16_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vstrhq_p_s32 (addr, value, p);
+  return vstrhq_p_s32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int32x4_t value, mve_pred16_t p)
+foo1 (int16_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vstrhq_p (addr, value, p);
+  return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo (uint16_t *base, uint16x8_t value, mve_pred16_t p)
 {
-  vstrhq_p_u16 (addr, value, p);
+  return vstrhq_p_u16 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint16x8_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint16x8_t value, mve_pred16_t p)
 {
-  vstrhq_p (addr, value, p);
+  return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * addr, uint32x4_t value, mve_pred16_t p)
+foo (uint16_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vstrhq_p_u32 (addr, value, p);
+  return vstrhq_p_u32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint32x4_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vstrhq_p (addr, value, p);
+  return vstrhq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * addr, int16x8_t value)
+foo (int16_t *base, int16x8_t value)
 {
-  vstrhq_s16 (addr, value);
+  return vstrhq_s16 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int16x8_t value)
+foo1 (int16_t *base, int16x8_t value)
 {
-  vstrhq (addr, value);
+  return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * addr, int32x4_t value)
+foo (int16_t *base, int32x4_t value)
 {
-  vstrhq_s32 (addr, value);
+  return vstrhq_s32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * addr, int32x4_t value)
+foo1 (int16_t *base, int32x4_t value)
 {
-  vstrhq (addr, value);
+  return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * base, uint16x8_t offset, float16x8_t value)
+foo (float16_t *base, uint16x8_t offset, float16x8_t value)
 {
-  vstrhq_scatter_offset_f16 (base, offset, value);
+  return vstrhq_scatter_offset_f16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value)
+foo1 (float16_t *base, uint16x8_t offset, float16x8_t value)
 {
-  vstrhq_scatter_offset (base, offset, value);
+  return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
+foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p_f16 (base, offset, value, p);
+  return vstrhq_scatter_offset_p_f16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
+foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p (base, offset, value, p);
+  return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p_s16 (base, offset, value, p);
+  return vstrhq_scatter_offset_p_s16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p (base, offset, value, p);
+  return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p_s32 (base, offset, value, p);
+  return vstrhq_scatter_offset_p_s32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p (base, offset, value, p);
+  return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p_u16 (base, offset, value, p);
+  return vstrhq_scatter_offset_p_u16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p (base, offset, value, p);
+  return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p_u32 (base, offset, value, p);
+  return vstrhq_scatter_offset_p_u32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_offset_p (base, offset, value, p);
+  return vstrhq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint16x8_t offset, int16x8_t value)
+foo (int16_t *base, uint16x8_t offset, int16x8_t value)
 {
-  vstrhq_scatter_offset_s16 (base, offset, value);
+  return vstrhq_scatter_offset_s16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value)
+foo1 (int16_t *base, uint16x8_t offset, int16x8_t value)
 {
-  vstrhq_scatter_offset (base, offset, value);
+  return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint32x4_t offset, int32x4_t value)
+foo (int16_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrhq_scatter_offset_s32 (base, offset, value);
+  return vstrhq_scatter_offset_s32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int16_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrhq_scatter_offset (base, offset, value);
+  return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value)
+foo (uint16_t *base, uint16x8_t offset, uint16x8_t value)
 {
-  vstrhq_scatter_offset_u16 (base, offset, value);
+  return vstrhq_scatter_offset_u16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value)
+foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value)
 {
-  vstrhq_scatter_offset (base, offset, value);
+  return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint16_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrhq_scatter_offset_u32 (base, offset, value);
+  return vstrhq_scatter_offset_u32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrhq_scatter_offset (base, offset, value);
+  return vstrhq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * base, uint16x8_t offset, float16x8_t value)
+foo (float16_t *base, uint16x8_t offset, float16x8_t value)
 {
-  vstrhq_scatter_shifted_offset_f16 (base, offset, value);
+  return vstrhq_scatter_shifted_offset_f16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value)
+foo1 (float16_t *base, uint16x8_t offset, float16x8_t value)
 {
-  vstrhq_scatter_shifted_offset (base, offset, value);
+  return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
+foo (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p_f16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float16_t * base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
+foo1 (float16_t *base, uint16x8_t offset, float16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p_s16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
+foo1 (int16_t *base, uint16x8_t offset, int16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p_s32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int16_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p_u16 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p_u32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrhq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrht.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint16x8_t offset, int16x8_t value)
+foo (int16_t *base, uint16x8_t offset, int16x8_t value)
 {
-  vstrhq_scatter_shifted_offset_s16 (base, offset, value);
+  return vstrhq_scatter_shifted_offset_s16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint16x8_t offset, int16x8_t value)
+foo1 (int16_t *base, uint16x8_t offset, int16x8_t value)
 {
-  vstrhq_scatter_shifted_offset (base, offset, value);
+  return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (int16_t * base, uint32x4_t offset, int32x4_t value)
+foo (int16_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrhq_scatter_shifted_offset_s32 (base, offset, value);
+  return vstrhq_scatter_shifted_offset_s32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int16_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int16_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrhq_scatter_shifted_offset (base, offset, value);
+  return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint16x8_t offset, uint16x8_t value)
+foo (uint16_t *base, uint16x8_t offset, uint16x8_t value)
 {
-  vstrhq_scatter_shifted_offset_u16 (base, offset, value);
+  return vstrhq_scatter_shifted_offset_u16 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint16x8_t offset, uint16x8_t value)
+foo1 (uint16_t *base, uint16x8_t offset, uint16x8_t value)
 {
-  vstrhq_scatter_shifted_offset (base, offset, value);
+  return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint16_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrhq_scatter_shifted_offset_u32 (base, offset, value);
+  return vstrhq_scatter_shifted_offset_u32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #1\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint16_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrhq_scatter_shifted_offset (base, offset, value);
+  return vstrhq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * addr, uint16x8_t value)
+foo (uint16_t *base, uint16x8_t value)
 {
-  vstrhq_u16 (addr, value);
+  return vstrhq_u16 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint16x8_t value)
+foo1 (uint16_t *base, uint16x8_t value)
 {
-  vstrhq (addr, value);
+  return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.16"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint16_t * addr, uint32x4_t value)
+foo (uint16_t *base, uint32x4_t value)
 {
-  vstrhq_u32 (addr, value);
+  return vstrhq_u32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrh.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint16_t * addr, uint32x4_t value)
+foo1 (uint16_t *base, uint32x4_t value)
 {
-  vstrhq (addr, value);
+  return vstrhq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrh.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * addr, float32x4_t value)
+foo (float32_t *base, float32x4_t value)
 {
-  vstrwq_f32 (addr, value);
+  return vstrwq_f32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * addr, float32x4_t value)
+foo1 (float32_t *base, float32x4_t value)
 {
-  vstrwq (addr, value);
+  return vstrwq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo (float32_t *base, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_p_f32 (addr, value, p);
+  return vstrwq_p_f32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p)
+foo1 (float32_t *base, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_p (addr, value, p);
+  return vstrwq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo (int32_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_p_s32 (addr, value, p);
+  return vstrwq_p_s32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p)
+foo1 (int32_t *base, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_p (addr, value, p);
+  return vstrwq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo (uint32_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_p_u32 (addr, value, p);
+  return vstrwq_p_u32 (base, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_p (addr, value, p);
+  return vstrwq_p (base, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * addr, int32x4_t value)
+foo (int32_t *base, int32x4_t value)
 {
-  vstrwq_s32 (addr, value);
+  return vstrwq_s32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * addr, int32x4_t value)
+foo1 (int32_t *base, int32x4_t value)
 {
-  vstrwq (addr, value);
+  return vstrwq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo (uint32x4_t addr, float32x4_t value)
 {
-  vstrwq_scatter_base_f32 (addr, 8, value);
+  return vstrwq_scatter_base_f32 (addr, 0, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo1 (uint32x4_t addr, float32x4_t value)
 {
-  vstrwq_scatter_base (addr, 8, value);
+  return vstrwq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_p_f32 (addr, 8, value, p);
+  return vstrwq_scatter_base_p_f32 (addr, 0, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo1 (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_p (addr, 8, value, p);
+  return vstrwq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo (uint32x4_t addr, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_p_s32 (addr, 8, value, p);
+  return vstrwq_scatter_base_p_s32 (addr, 0, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo1 (uint32x4_t addr, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_p (addr, 8, value, p);
+  return vstrwq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo (uint32x4_t addr, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_p_u32 (addr, 8, value, p);
+  return vstrwq_scatter_base_p_u32 (addr, 0, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo1 (uint32x4_t addr, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_p (addr, 8, value, p);
+  return vstrwq_scatter_base_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo (uint32x4_t addr, int32x4_t value)
 {
-  vstrwq_scatter_base_s32 (addr, 8, value);
+  return vstrwq_scatter_base_s32 (addr, 0, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo1 (uint32x4_t addr, int32x4_t value)
 {
-  vstrwq_scatter_base (addr, 8, value);
+  return vstrwq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo (uint32x4_t addr, uint32x4_t value)
 {
-  vstrwq_scatter_base_u32 (addr, 8, value);
+  return vstrwq_scatter_base_u32 (addr, 0, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\](?:	@.*|)
+**	...
+*/
 void
 foo1 (uint32x4_t addr, uint32x4_t value)
 {
-  vstrwq_scatter_base (addr, 8, value);
+  return vstrwq_scatter_base (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.u32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
@@ -1,19 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint32x4_t * addr, const int offset, float32x4_t value)
+foo (uint32x4_t *addr, float32x4_t value)
 {
-  vstrwq_scatter_base_wb_f32 (addr, 8, value);
+  return vstrwq_scatter_base_wb_f32 (addr, 0, value);
 }
 
+
+/*
+**foo1:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32x4_t * addr, const int offset, float32x4_t value)
+foo1 (uint32x4_t *addr, float32x4_t value)
 {
-  vstrwq_scatter_base_wb (addr, 8, value);
+  return vstrwq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c
@@ -1,19 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p)
+foo (uint32x4_t *addr, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_wb_p_f32 (addr, 8, value, p);
+  return vstrwq_scatter_base_wb_p_f32 (addr, 0, value, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p)
+foo1 (uint32x4_t *addr, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_wb_p (addr, 8, value, p);
+  return vstrwq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c
@@ -1,19 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p)
+foo (uint32x4_t *addr, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_wb_p_s32 (addr, 8, value, p);
+  return vstrwq_scatter_base_wb_p_s32 (addr, 0, value, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p)
+foo1 (uint32x4_t *addr, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_wb_p (addr, 8, value, p);
+  return vstrwq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c
@@ -1,19 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p)
+foo (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_wb_p_u32 (addr, 8, value, p);
+  return vstrwq_scatter_base_wb_p_u32 (addr, 0, value, p);
 }
 
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_base_wb_p (addr, 8, value, p);
+  return vstrwq_scatter_base_wb_p (addr, 0, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
@@ -1,19 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint32x4_t * addr, const int offset, int32x4_t value)
+foo (uint32x4_t *addr, int32x4_t value)
 {
-  vstrwq_scatter_base_wb_s32 (addr, 8, value);
+  return vstrwq_scatter_base_wb_s32 (addr, 0, value);
 }
 
+
+/*
+**foo1:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32x4_t * addr, const int offset, int32x4_t value)
+foo1 (uint32x4_t *addr, int32x4_t value)
 {
-  vstrwq_scatter_base_wb (addr, 8, value);
+  return vstrwq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
@@ -1,19 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo (uint32x4_t * addr, uint32x4_t value)
+foo (uint32x4_t *addr, uint32x4_t value)
 {
-  vstrwq_scatter_base_wb_u32 (addr, 8, value);
+  return vstrwq_scatter_base_wb_u32 (addr, 0, value);
 }
 
+
+/*
+**foo1:
+**	...
+**	vstrw.u32	q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32x4_t * addr, uint32x4_t value)
+foo1 (uint32x4_t *addr, uint32x4_t value)
 {
-  vstrwq_scatter_base_wb (addr, 8, value);
+  return vstrwq_scatter_base_wb (addr, 0, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * base, uint32x4_t offset, float32x4_t value)
+foo (float32_t *base, uint32x4_t offset, float32x4_t value)
 {
-  vstrwq_scatter_offset_f32 (base, offset, value);
+  return vstrwq_scatter_offset_f32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
+foo1 (float32_t *base, uint32x4_t offset, float32x4_t value)
 {
-  vstrwq_scatter_offset (base, offset, value);
+  return vstrwq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
+foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_offset_p_f32 (base, offset, value, p);
+  return vstrwq_scatter_offset_p_f32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
+foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_offset_p (base, offset, value, p);
+  return vstrwq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_offset_p_s32 (base, offset, value, p);
+  return vstrwq_scatter_offset_p_s32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_offset_p (base, offset, value, p);
+  return vstrwq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_offset_p_u32 (base, offset, value, p);
+  return vstrwq_scatter_offset_p_u32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_offset_p (base, offset, value, p);
+  return vstrwq_scatter_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * base, uint32x4_t offset, int32x4_t value)
+foo (int32_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrwq_scatter_offset_s32 (base, offset, value);
+  return vstrwq_scatter_offset_s32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int32_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrwq_scatter_offset (base, offset, value);
+  return vstrwq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint32_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrwq_scatter_offset_u32 (base, offset, value);
+  return vstrwq_scatter_offset_u32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrwq_scatter_offset (base, offset, value);
+  return vstrwq_scatter_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * base, uint32x4_t offset, float32x4_t value)
+foo (float32_t *base, uint32x4_t offset, float32x4_t value)
 {
-  vstrwq_scatter_shifted_offset_f32 (base, offset, value);
+  return vstrwq_scatter_shifted_offset_f32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
+foo1 (float32_t *base, uint32x4_t offset, float32x4_t value)
 {
-  vstrwq_scatter_shifted_offset (base, offset, value);
+  return vstrwq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
+foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p);
+  return vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
+foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p);
+  return vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
+foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c
@@ -1,21 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p);
+  return vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p);
 }
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
+foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
 {
-  vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+  return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrwt.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo (int32_t * base, uint32x4_t offset, int32x4_t value)
+foo (int32_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrwq_scatter_shifted_offset_s32 (base, offset, value);
+  return vstrwq_scatter_shifted_offset_s32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
+foo1 (int32_t *base, uint32x4_t offset, int32x4_t value)
 {
-  vstrwq_scatter_shifted_offset (base, offset, value);
+  return vstrwq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
+foo (uint32_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrwq_scatter_shifted_offset_u32 (base, offset, value);
+  return vstrwq_scatter_shifted_offset_u32 (base, offset, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
+foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value)
 {
-  vstrwq_scatter_shifted_offset (base, offset, value);
+  return vstrwq_scatter_shifted_offset (base, offset, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo (uint32_t * addr, uint32x4_t value)
+foo (uint32_t *base, uint32x4_t value)
 {
-  vstrwq_u32 (addr, value);
+  return vstrwq_u32 (base, value);
 }
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vstrw.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?:	@.*|)
+**	...
+*/
 void
-foo1 (uint32_t * addr, uint32x4_t value)
+foo1 (uint32_t *base, uint32x4_t value)
 {
-  vstrwq (addr, value);
+  return vstrwq (base, value);
+}
+
+#ifdef __cplusplus
 }
+#endif
 
-/* { dg-final { scan-assembler "vstrw.32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vsubq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vsubq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vsubq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vsubq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
-{
-  return vsubq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vsubq_m_n_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
-{
-  return vsubq_m (inactive, a, 23.23, p);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vsubq_m_n_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vsubq_m_n_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vsubq_m_n_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vsubq_m_n_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vsubq_m_n_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vsubq_m_n_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c
@@ -1,23 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vsubq_m_n_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vsubq_m (inactive, a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vsubq_m_s16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vsubq_m_s32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vsubq_m_s8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vsubq_m_u16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vsubq_m_u32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vsubq_m_u8 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
   return vsubq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo1 (float16x8_t a, float16_t b)
-{
-  return vsubq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b)
 {
   return vsubq_n_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vsub.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t a)
+{
+  return vsubq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo1 (float32x4_t a, float32_t b)
-{
-  return vsubq (a, 23.23);
-}
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c
@@ -1,21 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b)
 {
   return vsubq_n_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vsub.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t a)
+{
+  return vsubq (a, 1.1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b)
 {
   return vsubq_n_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b)
 {
   return vsubq_n_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c
@@ -1,22 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b)
 {
   return vsubq_n_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b)
 {
   return vsubq_n_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a)
+{
+  return vsubq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b)
 {
   return vsubq_n_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a)
+{
+  return vsubq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c
@@ -1,22 +1,53 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
-/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b)
 {
   return vsubq_n_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a)
+{
+  return vsubq (a, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b)
 {
   return vsubq_s16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo1 (int16x8_t a, int16x8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b)
 {
   return vsubq_s32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo1 (int32x4_t a, int32x4_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b)
 {
   return vsubq_s8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo1 (int8x16_t a, int8x16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b)
 {
   return vsubq_u16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo1 (uint16x8_t a, uint16x8_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b)
 {
   return vsubq_u32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo1 (uint32x4_t a, uint32x4_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b)
 {
   return vsubq_u8 (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vsub.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo1 (uint8x16_t a, uint8x16_t b)
 {
   return vsubq (a, b);
 }
 
-/* { dg-final { scan-assembler "vsub.i8"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
-    return vsubq_x_f16 (a, b, p);
+  return vsubq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
-    return vsubq_x_f32 (a, b, p);
+  return vsubq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float16x8_t
-foo (float16x8_t a, float16_t b, mve_pred16_t p)
-{
-    return vsubq_x_n_f16 (a, 23.23, p);
-}
-
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c
@@ -1,15 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float16x8_t
 foo (float16x8_t a, float16_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_f16 (a, b, p);
+  return vsubq_x_n_f16 (a, b, p);
+}
+
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float16x8_t
+foo2 (float16x8_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
 
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
deleted file mode 100644
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
-/* { dg-additional-options "-O2" } */
-
-#include "arm_mve.h"
-float32x4_t
-foo (float32x4_t a, float32_t b, mve_pred16_t p)
-{
-    return vsubq_x_n_f32 (a, 23.23, p);
-}
-
-
-/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c
@@ -1,15 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 float32x4_t
 foo (float32x4_t a, float32_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_f32 (a, b, p);
+  return vsubq_x_n_f32 (a, b, p);
+}
+
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.f32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.f32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+float32x4_t
+foo2 (float32x4_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1.1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
 
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_s16 (a, b, p);
+  return vsubq_x_n_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_s32 (a, b, p);
+  return vsubq_x_n_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_s8 (a, b, p);
+  return vsubq_x_n_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+int8x16_t
+foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c
@@ -1,15 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_u16 (a, b, p);
+  return vsubq_x_n_u16 (a, b, p);
+}
+
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo2 (uint16x8_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
 
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c
@@ -1,15 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_u32 (a, b, p);
+  return vsubq_x_n_u32 (a, b, p);
+}
+
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo2 (uint32x4_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
 
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c
@@ -1,15 +1,65 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
 {
-    return vsubq_x_n_u8 (a, b, p);
+  return vsubq_x_n_u8 (a, b, p);
+}
+
+
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo2 (uint8x16_t a, mve_pred16_t p)
+{
+  return vsubq_x (a, 1, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
 
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int16x8_t
 foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
 {
-    return vsubq_x_s16 (a, b, p);
+  return vsubq_x_s16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int32x4_t
 foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
 {
-    return vsubq_x_s32 (a, b, p);
+  return vsubq_x_s32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int8x16_t
 foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
 {
-    return vsubq_x_s8 (a, b, p);
+  return vsubq_x_s8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint16x8_t
 foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
 {
-    return vsubq_x_u16 (a, b, p);
+  return vsubq_x_u16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i16"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i16	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint16x8_t
+foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint32x4_t
 foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
 {
-    return vsubq_x_u32 (a, b, p);
+  return vsubq_x_u32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i32	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint32x4_t
+foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
--- a/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c
@@ -1,15 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint8x16_t
 foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
 {
-    return vsubq_x_u8 (a, b, p);
+  return vsubq_x_u8 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vsubt.i8"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vsubt.i8	q[0-9]+, q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint8x16_t
+foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+  return vsubq_x (a, b, p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c
@@ -0,0 +1,41 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_mve.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo11:
+**     ...
+**     movs	r0, #2
+**     ...
+*/
+uint32_t
+foo11 ()
+{
+  return uqshl (1, 1);
+}
+
+/*
+**foo12:
+**     ...
+**	movs	r0, #2
+**	movs	r1, #0
+**     ...
+*/
+uint64_t
+foo12 ()
+{
+  return uqshll (1, 1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
--- a/src/gcc/testsuite/gcc.target/arm/mve/mve_load_memory_modes.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/mve_load_memory_modes.c
@@ -7,7 +7,7 @@
 /*
 **off_load8_0:
 **	...
-**	vldrb.8	q0, \[r0, #16\]
+**	vldrb.8	q[0-7], \[r0, #16\]
 **	...
 */
 int8x16_t off_load8_0 (int8_t * a)
@@ -18,7 +18,7 @@ int8x16_t off_load8_0 (int8_t * a)
 /*
 **off_load8_1:
 **	...
-**	vldrb.u16	q0, \[r0, #1\]
+**	vldrb.u16	q[0-7], \[r0, #1\]
 **	...
 */
 uint16x8_t off_load8_1 (uint8_t * a)
@@ -29,7 +29,7 @@ uint16x8_t off_load8_1 (uint8_t * a)
 /*
 **off_load8_2:
 **	...
-**	vldrb.s32	q0, \[r0, #127\]
+**	vldrb.s32	q[0-7], \[r0, #127\]
 **	...
 */
 int32x4_t off_load8_2 (int8_t * a)
@@ -40,7 +40,7 @@ int32x4_t off_load8_2 (int8_t * a)
 /*
 **off_load8_3:
 **	...
-**	vldrb.8	q0, \[r0, #-127\]
+**	vldrb.8	q[0-7], \[r0, #-127\]
 **	...
 */
 uint8x16_t off_load8_3 (uint8_t * a)
@@ -51,7 +51,7 @@ uint8x16_t off_load8_3 (uint8_t * a)
 /*
 **not_off_load8_0:
 **	...
-**	vldrb.8	q0, \[r[0-9]+\]
+**	vldrb.8	q[0-7], \[r[0-7]+\]
 **	...
 */
 int8x16_t not_off_load8_0 (int8_t * a)
@@ -62,7 +62,7 @@ int8x16_t not_off_load8_0 (int8_t * a)
 /*
 **off_loadfp16_0:
 **	...
-**	vldrh.16	q0, \[r0, #-244\]
+**	vldrh.16	q[0-7], \[r0, #-244\]
 **	...
 */
 float16x8_t off_loadfp16_0 (float16_t *a)
@@ -73,7 +73,7 @@ float16x8_t off_loadfp16_0 (float16_t *a)
 /*
 **off_load16_0:
 **	...
-**	vldrh.16	q0, \[r0, #-2\]
+**	vldrh.16	q[0-7], \[r0, #-2\]
 **	...
 */
 uint16x8_t off_load16_0 (uint16_t * a)
@@ -84,7 +84,7 @@ uint16x8_t off_load16_0 (uint16_t * a)
 /*
 **off_load16_1:
 **	...
-**	vldrh.u32	q0, \[r0, #254\]
+**	vldrh.u32	q[0-7], \[r0, #254\]
 **	...
 */
 uint32x4_t off_load16_1 (uint16_t * a)
@@ -95,7 +95,7 @@ uint32x4_t off_load16_1 (uint16_t * a)
 /*
 **not_off_load16_0:
 **	...
-**	vldrh.16	q0, \[r[0-9]+\]
+**	vldrh.16	q[0-7], \[r[0-7]+\]
 **	...
 */
 int16x8_t not_off_load16_0 (int8_t * a)
@@ -106,7 +106,7 @@ int16x8_t not_off_load16_0 (int8_t * a)
 /*
 **not_off_load16_1:
 **	...
-**	vldrh.u32	q0, \[r[0-9]+\]
+**	vldrh.u32	q[0-7], \[r[0-7]+\]
 **	...
 */
 uint32x4_t not_off_load16_1 (uint16_t * a)
@@ -117,7 +117,7 @@ uint32x4_t not_off_load16_1 (uint16_t * a)
 /*
 **off_loadfp32_0:
 **	...
-**	vldrw.32	q0, \[r0, #24\]
+**	vldrw.32	q[0-7], \[r0, #24\]
 **	...
 */
 float32x4_t off_loadfp32_0 (float32_t *a)
@@ -128,7 +128,7 @@ float32x4_t off_loadfp32_0 (float32_t *a)
 /*
 **off_load32_0:
 **	...
-**	vldrw.32	q0, \[r0, #4\]
+**	vldrw.32	q[0-7], \[r0, #4\]
 **	...
 */
 uint32x4_t off_load32_0 (uint32_t * a)
@@ -139,7 +139,7 @@ uint32x4_t off_load32_0 (uint32_t * a)
 /*
 **off_load32_1:
 **	...
-**	vldrw.32	q0, \[r0, #-508\]
+**	vldrw.32	q[0-7], \[r0, #-508\]
 **	...
 */
 int32x4_t off_load32_1 (int32_t * a)
@@ -149,7 +149,7 @@ int32x4_t off_load32_1 (int32_t * a)
 /*
 **pre_load8_0:
 **	...
-**	vldrb.8	q[0-9]+, \[r0, #16\]!
+**	vldrb.8	q[0-7], \[r0, #16\]!
 **	...
 */
 int8_t* pre_load8_0 (int8_t * a, int8x16_t *v)
@@ -162,7 +162,7 @@ int8_t* pre_load8_0 (int8_t * a, int8x16_t *v)
 /*
 **pre_load8_1:
 **	...
-**	vldrb.u16	q[0-9]+, \[r0, #4\]!
+**	vldrb.u16	q[0-7], \[r0, #4\]!
 **	...
 */
 uint8_t* pre_load8_1 (uint8_t * a, uint16x8_t *v)
@@ -175,7 +175,7 @@ uint8_t* pre_load8_1 (uint8_t * a, uint16x8_t *v)
 /*
 **pre_loadfp16_0:
 **	...
-**	vldrh.16	q[0-9]+, \[r0, #128\]!
+**	vldrh.16	q[0-7], \[r0, #128\]!
 **	...
 */
 float16_t* pre_loadfp16_0 (float16_t *a, float16x8_t *v)
@@ -188,7 +188,7 @@ float16_t* pre_loadfp16_0 (float16_t *a, float16x8_t *v)
 /*
 **pre_load16_0:
 **	...
-**	vldrh.16	q[0-9]+, \[r0, #-254\]!
+**	vldrh.16	q[0-7], \[r0, #-254\]!
 **	...
 */
 int16_t* pre_load16_0 (int16_t * a, int16x8_t *v)
@@ -201,7 +201,7 @@ int16_t* pre_load16_0 (int16_t * a, int16x8_t *v)
 /*
 **pre_load16_1:
 **	...
-**	vldrh.s32	q[0-9]+, \[r0, #52\]!
+**	vldrh.s32	q[0-7], \[r0, #52\]!
 **	...
 */
 int16_t* pre_load16_1 (int16_t * a, int32x4_t *v)
@@ -214,7 +214,7 @@ int16_t* pre_load16_1 (int16_t * a, int32x4_t *v)
 /*
 **pre_loadfp32_0:
 **	...
-**	vldrw.32	q[0-9]+, \[r0, #-72\]!
+**	vldrw.32	q[0-7], \[r0, #-72\]!
 **	...
 */
 float32_t* pre_loadfp32_0 (float32_t *a, float32x4_t *v)
@@ -228,7 +228,7 @@ float32_t* pre_loadfp32_0 (float32_t *a, float32x4_t *v)
 /*
 **pre_load32_0:
 **	...
-**	vldrw.32	q[0-9]+, \[r0, #-4\]!
+**	vldrw.32	q[0-7], \[r0, #-4\]!
 **	...
 */
 uint32_t* pre_load32_0 (uint32_t * a, uint32x4_t *v)
@@ -242,7 +242,7 @@ uint32_t* pre_load32_0 (uint32_t * a, uint32x4_t *v)
 /*
 **post_load8_0:
 **	...
-**	vldrb.8	q[0-9]+, \[r0\], #26
+**	vldrb.8	q[0-7], \[r0\], #26
 **	...
 */
 uint8_t* post_load8_0 (uint8_t * a, uint8x16_t *v)
@@ -255,7 +255,7 @@ uint8_t* post_load8_0 (uint8_t * a, uint8x16_t *v)
 /*
 **post_load8_1:
 **	...
-**	vldrb.s16	q[0-9]+, \[r0\], #-1
+**	vldrb.s16	q[0-7], \[r0\], #-1
 **	...
 */
 int8_t* post_load8_1 (int8_t * a, int16x8_t *v)
@@ -268,7 +268,7 @@ int8_t* post_load8_1 (int8_t * a, int16x8_t *v)
 /*
 **post_load8_2:
 **	...
-**	vldrb.8	q[0-9]+, \[r0\], #26
+**	vldrb.8	q[0-7], \[r0\], #26
 **	...
 */
 uint8_t* post_load8_2 (uint8_t * a, uint8x16_t *v)
@@ -281,7 +281,7 @@ uint8_t* post_load8_2 (uint8_t * a, uint8x16_t *v)
 /*
 **post_load8_3:
 **	...
-**	vldrb.s16	q[0-9]+, \[r0\], #-1
+**	vldrb.s16	q[0-7], \[r0\], #-1
 **	...
 */
 int8_t* post_load8_3 (int8_t * a, int16x8_t *v)
@@ -294,7 +294,7 @@ int8_t* post_load8_3 (int8_t * a, int16x8_t *v)
 /*
 **post_loadfp16_0:
 **	...
-**	vldrh.16	q[0-9]+, \[r0\], #-24
+**	vldrh.16	q[0-7], \[r0\], #-24
 **	...
 */
 float16_t* post_loadfp16_0 (float16_t *a, float16x8_t *v)
@@ -307,7 +307,7 @@ float16_t* post_loadfp16_0 (float16_t *a, float16x8_t *v)
 /*
 **post_load16_0:
 **	...
-**	vldrh.16	q[0-9]+, \[r0\], #-126
+**	vldrh.16	q[0-7], \[r0\], #-126
 **	...
 */
 uint16_t* post_load16_0 (uint16_t * a, uint16x8_t *v)
@@ -320,7 +320,7 @@ uint16_t* post_load16_0 (uint16_t * a, uint16x8_t *v)
 /*
 **post_load16_1:
 **	...
-**	vldrh.u32	q[0-9]+, \[r0\], #16
+**	vldrh.u32	q[0-7], \[r0\], #16
 **	...
 */
 uint16_t* post_load16_1 (uint16_t * a, uint32x4_t *v)
@@ -333,7 +333,7 @@ uint16_t* post_load16_1 (uint16_t * a, uint32x4_t *v)
 /*
 **post_loadfp32_0:
 **	...
-**	vldrw.32	q[0-9]+, \[r0\], #4
+**	vldrw.32	q[0-7], \[r0\], #4
 **	...
 */
 float32_t* post_loadfp32_0 (float32_t *a, float32x4_t *v)
@@ -346,7 +346,7 @@ float32_t* post_loadfp32_0 (float32_t *a, float32x4_t *v)
 /*
 **post_load32_0:
 **	...
-**	vldrw.32	q[0-9]+, \[r0\], #-16
+**	vldrw.32	q[0-7], \[r0\], #-16
 **	...
 */
 int32_t* post_load32_0 (int32_t * a, int32x4_t *v)
--- a/src/gcc/testsuite/gcc.target/arm/mve/mve_store_memory_modes.c
+++ b/src/gcc/testsuite/gcc.target/arm/mve/mve_store_memory_modes.c
@@ -7,7 +7,7 @@
 /*
 **off_store8_0:
 **	...
-**	vstrb.8	q0, \[r0, #16\]
+**	vstrb.8	q[0-7], \[r0, #16\]
 **	...
 */
 uint8_t *off_store8_0 (uint8_t * a, uint8x16_t v)
@@ -19,7 +19,7 @@ uint8_t *off_store8_0 (uint8_t * a, uint8x16_t v)
 /*
 **off_store8_1:
 **	...
-**	vstrb.16	q0, \[r0, #-1\]
+**	vstrb.16	q[0-7], \[r0, #-1\]
 **	...
 */
 int8_t *off_store8_1 (int8_t * a, int16x8_t v)
@@ -31,7 +31,7 @@ int8_t *off_store8_1 (int8_t * a, int16x8_t v)
 /*
 **off_store8_2:
 **	...
-**	vstrb.32	q0, \[r0, #-127\]
+**	vstrb.32	q[0-7], \[r0, #-127\]
 **	...
 */
 uint8_t *off_store8_2 (uint8_t * a, uint32x4_t v)
@@ -43,7 +43,7 @@ uint8_t *off_store8_2 (uint8_t * a, uint32x4_t v)
 /*
 **off_store8_3:
 **	...
-**	vstrb.8	q0, \[r0, #127\]
+**	vstrb.8	q[0-7], \[r0, #127\]
 **	...
 */
 int8_t *off_store8_3 (int8_t * a, int8x16_t v)
@@ -55,7 +55,7 @@ int8_t *off_store8_3 (int8_t * a, int8x16_t v)
 /*
 **not_off_store8_0:
 **	...
-**	vstrb.8	q0, \[r[0-9]+\]
+**	vstrb.8	q[0-7], \[r[0-7]+\]
 **	...
 */
 uint8_t *not_off_store8_0 (uint8_t * a, uint8x16_t v)
@@ -67,7 +67,7 @@ uint8_t *not_off_store8_0 (uint8_t * a, uint8x16_t v)
 /*
 **off_storefp16_0:
 **	...
-**	vstrh.16	q0, \[r0, #250\]
+**	vstrh.16	q[0-7], \[r0, #250\]
 **	...
 */
 float16_t *off_storefp16_0 (float16_t *a, float16x8_t v)
@@ -79,7 +79,7 @@ float16_t *off_storefp16_0 (float16_t *a, float16x8_t v)
 /*
 **off_store16_0:
 **	...
-**	vstrh.16	q0, \[r0, #4\]
+**	vstrh.16	q[0-7], \[r0, #4\]
 **	...
 */
 int16_t *off_store16_0 (int16_t * a, int16x8_t v)
@@ -91,7 +91,7 @@ int16_t *off_store16_0 (int16_t * a, int16x8_t v)
 /*
 **off_store16_1:
 **	...
-**	vstrh.32	q0, \[r0, #-254\]
+**	vstrh.32	q[0-7], \[r0, #-254\]
 **	...
 */
 int16_t *off_store16_1 (int16_t * a, int32x4_t v)
@@ -103,7 +103,7 @@ int16_t *off_store16_1 (int16_t * a, int32x4_t v)
 /*
 **not_off_store16_0:
 **	...
-**	vstrh.16	q0, \[r[0-9]+\]
+**	vstrh.16	q[0-7], \[r[0-7]+\]
 **	...
 */
 uint8_t *not_off_store16_0 (uint8_t * a, uint16x8_t v)
@@ -115,7 +115,7 @@ uint8_t *not_off_store16_0 (uint8_t * a, uint16x8_t v)
 /*
 **not_off_store16_1:
 **	...
-**	vstrh.32	q0, \[r[0-9]+\]
+**	vstrh.32	q[0-7], \[r[0-7]+\]
 **	...
 */
 int16_t *not_off_store16_1 (int16_t * a, int32x4_t v)
@@ -127,7 +127,7 @@ int16_t *not_off_store16_1 (int16_t * a, int32x4_t v)
 /*
 **off_storefp32_0:
 **	...
-**	vstrw.32	q0, \[r0, #-412\]
+**	vstrw.32	q[0-7], \[r0, #-412\]
 **	...
 */
 float32_t *off_storefp32_0 (float32_t *a, float32x4_t v)
@@ -139,7 +139,7 @@ float32_t *off_storefp32_0 (float32_t *a, float32x4_t v)
 /*
 **off_store32_0:
 **	...
-**	vstrw.32	q0, \[r0, #-4\]
+**	vstrw.32	q[0-7], \[r0, #-4\]
 **	...
 */
 int32_t *off_store32_0 (int32_t * a, int32x4_t v)
@@ -151,7 +151,7 @@ int32_t *off_store32_0 (int32_t * a, int32x4_t v)
 /*
 **off_store32_1:
 **	...
-**	vstrw.32	q0, \[r0, #508\]
+**	vstrw.32	q[0-7], \[r0, #508\]
 **	...
 */
 uint32_t *off_store32_1 (uint32_t * a, uint32x4_t v)
@@ -163,7 +163,7 @@ uint32_t *off_store32_1 (uint32_t * a, uint32x4_t v)
 /*
 **pre_store8_0:
 **	...
-**	vstrb.8	q[0-9]+, \[r0, #-16\]!
+**	vstrb.8	q[0-7], \[r0, #-16\]!
 **	...
 */
 uint8_t* pre_store8_0 (uint8_t * a, uint8x16_t v)
@@ -176,7 +176,7 @@ uint8_t* pre_store8_0 (uint8_t * a, uint8x16_t v)
 /*
 **pre_store8_1:
 **	...
-**	vstrb.16	q[0-9]+, \[r0, #4\]!
+**	vstrb.16	q[0-7], \[r0, #4\]!
 **	...
 */
 int8_t* pre_store8_1 (int8_t * a, int16x8_t v)
@@ -189,7 +189,7 @@ int8_t* pre_store8_1 (int8_t * a, int16x8_t v)
 /*
 **pre_storefp16_0:
 **	...
-**	vstrh.16	q0, \[r0, #8\]!
+**	vstrh.16	q[0-7], \[r0, #8\]!
 **	...
 */
 float16_t *pre_storefp16_0 (float16_t *a, float16x8_t v)
@@ -202,7 +202,7 @@ float16_t *pre_storefp16_0 (float16_t *a, float16x8_t v)
 /*
 **pre_store16_0:
 **	...
-**	vstrh.16	q[0-9]+, \[r0, #254\]!
+**	vstrh.16	q[0-7], \[r0, #254\]!
 **	...
 */
 uint16_t* pre_store16_0 (uint16_t * a, uint16x8_t v)
@@ -215,7 +215,7 @@ uint16_t* pre_store16_0 (uint16_t * a, uint16x8_t v)
 /*
 **pre_store16_1:
 **	...
-**	vstrh.32	q[0-9]+, \[r0, #-52\]!
+**	vstrh.32	q[0-7], \[r0, #-52\]!
 **	...
 */
 int16_t* pre_store16_1 (int16_t * a, int32x4_t v)
@@ -228,7 +228,7 @@ int16_t* pre_store16_1 (int16_t * a, int32x4_t v)
 /*
 **pre_storefp32_0:
 **	...
-**	vstrw.32	q0, \[r0, #-4\]!
+**	vstrw.32	q[0-7], \[r0, #-4\]!
 **	...
 */
 float32_t *pre_storefp32_0 (float32_t *a, float32x4_t v)
@@ -241,7 +241,7 @@ float32_t *pre_storefp32_0 (float32_t *a, float32x4_t v)
 /*
 **pre_store32_0:
 **	...
-**	vstrw.32	q[0-9]+, \[r0, #4\]!
+**	vstrw.32	q[0-7], \[r0, #4\]!
 **	...
 */
 int32_t* pre_store32_0 (int32_t * a, int32x4_t v)
@@ -255,7 +255,7 @@ int32_t* pre_store32_0 (int32_t * a, int32x4_t v)
 /*
 **post_store8_0:
 **	...
-**	vstrb.8	q[0-9]+, \[r0\], #-26
+**	vstrb.8	q[0-7], \[r0\], #-26
 **	...
 */
 int8_t* post_store8_0 (int8_t * a, int8x16_t v)
@@ -268,7 +268,7 @@ int8_t* post_store8_0 (int8_t * a, int8x16_t v)
 /*
 **post_store8_1:
 **	...
-**	vstrb.16	q[0-9]+, \[r0\], #1
+**	vstrb.16	q[0-7], \[r0\], #1
 **	...
 */
 uint8_t* post_store8_1 (uint8_t * a, uint16x8_t v)
@@ -281,7 +281,7 @@ uint8_t* post_store8_1 (uint8_t * a, uint16x8_t v)
 /*
 **post_store8_2:
 **	...
-**	vstrb.8	q[0-9]+, \[r0\], #-26
+**	vstrb.8	q[0-7], \[r0\], #-26
 **	...
 */
 int8_t* post_store8_2 (int8_t * a, int8x16_t v)
@@ -294,7 +294,7 @@ int8_t* post_store8_2 (int8_t * a, int8x16_t v)
 /*
 **post_store8_3:
 **	...
-**	vstrb.16	q[0-9]+, \[r0\], #7
+**	vstrb.16	q[0-7], \[r0\], #7
 **	...
 */
 uint8_t* post_store8_3 (uint8_t * a, uint16x8_t v)
@@ -307,7 +307,7 @@ uint8_t* post_store8_3 (uint8_t * a, uint16x8_t v)
 /*
 **post_storefp16_0:
 **	...
-**	vstrh.16	q[0-9]+, \[r0\], #-16
+**	vstrh.16	q[0-7], \[r0\], #-16
 **	...
 */
 float16_t *post_storefp16_0 (float16_t *a, float16x8_t v)
@@ -320,7 +320,7 @@ float16_t *post_storefp16_0 (float16_t *a, float16x8_t v)
 /*
 **post_store16_0:
 **	...
-**	vstrh.16	q[0-9]+, \[r0\], #126
+**	vstrh.16	q[0-7], \[r0\], #126
 **	...
 */
 int16_t* post_store16_0 (int16_t * a, int16x8_t v)
@@ -333,7 +333,7 @@ int16_t* post_store16_0 (int16_t * a, int16x8_t v)
 /*
 **post_store16_1:
 **	...
-**	vstrh.32	q[0-9]+, \[r0\], #-16
+**	vstrh.32	q[0-7], \[r0\], #-16
 **	...
 */
 uint16_t* post_store16_1 (uint16_t * a, uint32x4_t v)
@@ -346,7 +346,7 @@ uint16_t* post_store16_1 (uint16_t * a, uint32x4_t v)
 /*
 **post_storefp32_0:
 **	...
-**	vstrw.32	q[0-9]+, \[r0\], #-16
+**	vstrw.32	q[0-7], \[r0\], #-16
 **	...
 */
 float32_t* post_storefp32_0 (float32_t * a, float32x4_t v)
@@ -359,7 +359,7 @@ float32_t* post_storefp32_0 (float32_t * a, float32x4_t v)
 /*
 **post_store32_0:
 **	...
-**	vstrw.32	q[0-9]+, \[r0\], #16
+**	vstrw.32	q[0-7], \[r0\], #16
 **	...
 */
 int32_t* post_store32_0 (int32_t * a, int32x4_t v)
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include <arm_mve.h>
+
+volatile int32x4_t c1;
+volatile uint32x4_t c2;
+int *carry;
+
+int
+main ()
+{
+  int32x4_t a1 = vcreateq_s32 (0, 0);
+  int32x4_t b1 = vcreateq_s32 (0, 0);
+  int32x4_t inactive1 = vcreateq_s32 (0, 0);
+
+  uint32x4_t a2 = vcreateq_u32 (0, 0);
+  uint32x4_t b2 = vcreateq_u32 (0, 0);
+  uint32x4_t inactive2 = vcreateq_u32 (0, 0);
+
+  mve_pred16_t p = 0xFFFF;
+  (*carry) = 0xFFFFFFFF;
+
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c1 = vadcq (a1, b1, carry);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c2 = vadcq (a2, b2, carry);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c1 = vsbcq (a1, b1, carry);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c2 = vsbcq (a2, b2, carry);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c1 = vadcq_m (inactive1, a1, b1, carry, p);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c2 = vadcq_m (inactive2, a2, b2, carry, p);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c1 = vsbcq_m (inactive1, a1, b1, carry, p);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+  (*carry) = 0xFFFFFFFF;
+  __builtin_arm_set_fpscr_nzcvqc (0);
+  c2 = vsbcq_m (inactive2, a2, b2, carry, p);
+  if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
+    __builtin_abort ();
+
+  return 0;
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-1-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2 --save-temps" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-1.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE uint8x16_t
+#define INTRINSIC vstrbq_u8
+#define INTRINSIC_P vstrbq_p_u8
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-10-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-10.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-10.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrhq_s32
+#define INTRINSIC_P vstrhq_p_s32
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-11-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-11.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-11.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrwq_u32
+#define INTRINSIC_P vstrwq_p_u32
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-12-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-12.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-12.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrwq_s32
+#define INTRINSIC_P vstrwq_p_s32
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-13-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+
+#include "pr108177-13.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE float16x8_t
+#define INTRINSIC vstrhq_f16
+#define INTRINSIC_P vstrhq_p_f16
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-14-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+
+#include "pr108177-14.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-14.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrwt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE float32x4_t
+#define INTRINSIC vstrwq_f32
+#define INTRINSIC_P vstrwq_p_f32
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-2-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-2.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrbt.8	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE int8x16_t
+#define INTRINSIC vstrbq_s8
+#define INTRINSIC_P vstrbq_p_s8
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-3-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-3.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-3.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE uint16x8_t
+#define INTRINSIC vstrbq_u16
+#define INTRINSIC_P vstrbq_p_u16
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-4-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-4.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrbt.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE int16x8_t
+#define INTRINSIC vstrbq_s16
+#define INTRINSIC_P vstrbq_p_s16
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-5-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-5.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-5.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrbq_u32
+#define INTRINSIC_P vstrbq_p_u32
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-6-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-6.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrbt.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE int32x4_t
+#define INTRINSIC vstrbq_s32
+#define INTRINSIC_P vstrbq_p_s32
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-7-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-7.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-7.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE uint16x8_t
+#define INTRINSIC vstrhq_u16
+#define INTRINSIC_P vstrhq_p_u16
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-8-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-8.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrht.16	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE int16x8_t
+#define INTRINSIC vstrhq_s16
+#define INTRINSIC_P vstrhq_p_s16
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-9-run.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include "pr108177-9.c"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-9.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** test:
+**...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+**	vstrht.32	q[0-9]+, \[(?:ip|fp|r[0-9]+)\]
+**...
+*/
+
+#define TYPE uint32x4_t
+#define INTRINSIC vstrhq_u32
+#define INTRINSIC_P vstrhq_p_u32
+
+#include "pr108177.x"
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177-main.x
@@ -0,0 +1,31 @@
+#include <arm_mve.h>
+extern void abort (void);
+
+__attribute__ ((noipa)) void
+write_expected (uint32x4_t v, void *a)
+{
+  TYPE _v = (TYPE) v;
+  INTRINSIC (a, _v);
+}
+
+void test (uint32x4_t, void *, mve_pred16_t, mve_pred16_t);
+
+int main(void)
+{
+  uint32x4_t v = {0, 1, 2, 3};
+  uint32_t actual[] = {0, 0, 0, 0};
+  uint32_t expected[] = {0, 0, 0, 0};
+
+  write_expected (v, &(expected[0]));
+
+  mve_pred16_t p1 = 0xff00;
+  mve_pred16_t p2 = 0x00ff;
+
+  test (v, (void *)&actual[0], p1, p2);
+
+  if (__builtin_memcmp (&actual[0], &expected[0], 16) != 0)
+    abort ();
+
+  return 0;
+}
+
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/mve/pr108177.x
@@ -0,0 +1,9 @@
+#include "pr108177-main.x"
+
+__attribute__ ((noipa)) void
+test (uint32x4_t v, void *a, mve_pred16_t p1, mve_pred16_t p2)
+{
+  TYPE _v = (TYPE) v;
+  INTRINSIC_P (a, _v, p1);
+  INTRINSIC_P (a, _v, p2);
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/pr109939.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_sat_ok } */
+/* { dg-add-options arm_sat } */
+/* { dg-additional-options "-O -Wall -Wconversion" } */
+
+#include <arm_acle.h>
+
+int dbg_ssat_out;
+int dbg_ssat_in;
+
+void test_arm_ssat(void)
+{
+    dbg_ssat_out = __ssat(dbg_ssat_in, 16);
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_hard_ok } */
+/* { dg-options "-O2 -march=armv7-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mbig-endian -mpure-code" } */
+double f() { return 5.0; }
--- a/src/gcc/testsuite/gcc.target/arm/simd/mve-compare-1.c
+++ b/src/gcc/testsuite/gcc.target/arm/simd/mve-compare-1.c
@@ -50,31 +50,31 @@ TEST_TYPE (vs32, __INT32_TYPE__, COMPARE_REG_AND_ZERO, 16)
 TEST_TYPE (vu32, __UINT32_TYPE__, COMPARE_REG, 16)
 
 /* { 8 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
-/* { dg-final { scan-assembler-times {\tvcmp.i8  eq, q[0-9]+, q[0-9]+\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i8  ne, q[0-9]+, q[0-9]+\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  lt, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  le, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  gt, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  ge, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u8  hi, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u8  cs, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i8\teq, q[0-9]+, q[0-9]+\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i8\tne, q[0-9]+, q[0-9]+\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tlt, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tle, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tgt, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tge, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u8\thi, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u8\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
 
 /* { 16 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
-/* { dg-final { scan-assembler-times {\tvcmp.i16  eq, q[0-9]+, q[0-9]+\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i16  ne, q[0-9]+, q[0-9]+\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  lt, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  le, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  gt, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  ge, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u16  hi, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u16  cs, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i16\teq, q[0-9]+, q[0-9]+\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i16\tne, q[0-9]+, q[0-9]+\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tlt, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tle, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tgt, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tge, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u16\thi, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u16\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
 
 /* { 32 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
-/* { dg-final { scan-assembler-times {\tvcmp.i32  eq, q[0-9]+, q[0-9]+\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i32  ne, q[0-9]+, q[0-9]+\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  lt, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  le, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  gt, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  ge, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u32  hi, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u32  cs, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i32\teq, q[0-9]+, q[0-9]+\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i32\tne, q[0-9]+, q[0-9]+\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tlt, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tle, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tgt, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tge, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u32\thi, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u32\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
--- a/src/gcc/testsuite/gcc.target/arm/simd/mve-compare-scalar-1.c
+++ b/src/gcc/testsuite/gcc.target/arm/simd/mve-compare-scalar-1.c
@@ -39,31 +39,31 @@ TEST_TYPE (vs32, __INT32_TYPE__, 16)
 TEST_TYPE (vu32, __UINT32_TYPE__, 16)
 
 /* { 8 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
-/* { dg-final { scan-assembler-times {\tvcmp.i8  eq, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i8  ne, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  lt, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  le, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  gt, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s8  ge, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u8  hi, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u8  cs, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i8\teq, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i8\tne, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tlt, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tle, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tgt, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s8\tge, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u8\thi, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u8\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
 
 /* { 16 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
-/* { dg-final { scan-assembler-times {\tvcmp.i16  eq, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i16  ne, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  lt, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  le, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  gt, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s16  ge, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u16  hi, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u16  cs, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i16\teq, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i16\tne, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tlt, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tle, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tgt, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s16\tge, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u16\thi, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u16\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
 
 /* { 32 bits } x { eq, ne, lt, le, gt, ge, hi, cs }.
-/* { dg-final { scan-assembler-times {\tvcmp.i32  eq, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i32  ne, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  lt, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  le, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  gt, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s32  ge, q[0-9]+, q[0-9]+\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u32  hi, q[0-9]+, q[0-9]+\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u32  cs, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i32\teq, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i32\tne, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tlt, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tle, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tgt, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s32\tge, q[0-9]+, q[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u32\thi, q[0-9]+, q[0-9]+\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u32\tcs, q[0-9]+, q[0-9]+\n} 2 } } */
--- a/src/gcc/testsuite/gcc.target/arm/simd/mve-vabs.c
+++ b/src/gcc/testsuite/gcc.target/arm/simd/mve-vabs.c
@@ -38,7 +38,7 @@ FUNC(f, float, 16, 8, vabs)
    integer optimizations actually generate a call to memmove, the other ones a
    'vabs'.  */
 /* { dg-final { scan-assembler-times {vabs.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
-/* { dg-final { scan-assembler-times {vabs.f[0-9]+  q[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vabs.f[0-9]+\tq[0-9]+, q[0-9]+} 2 } } */
 /* { dg-final { scan-assembler-times {vldr[bhw].[0-9]+\tq[0-9]+} 5 } } */
 /* { dg-final { scan-assembler-times {vstr[bhw].[0-9]+\tq[0-9]+} 5 } } */
 /* { dg-final { scan-assembler-times {memmove} 3 } } */
--- a/src/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
+++ b/src/gcc/testsuite/gcc.target/arm/simd/mve-vadd-1.c
@@ -22,9 +22,9 @@ FUNC(u, uint, 16, 8, +, vadd)
 FUNC(s, int, 8, 16, +, vadd)
 FUNC(u, uint, 8, 16, +, vadd)
 
-/* { dg-final { scan-assembler-times {vadd\.i32  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
-/* { dg-final { scan-assembler-times {vadd\.i16  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
-/* { dg-final { scan-assembler-times {vadd\.i8  q[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadd\.i32\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadd\.i16\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadd\.i8\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */
 
 void test_vadd_f32 (float * dest, float * a, float * b) {
   int i;
@@ -32,7 +32,7 @@ void test_vadd_f32 (float * dest, float * a, float * b) {
     dest[i] = a[i] + b[i];
   }
 }
-/* { dg-final { scan-assembler-times {vadd\.f32 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vadd\.f32\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
 
 void test_vadd_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
   int i;
@@ -40,4 +40,4 @@ void test_vadd_f16 (__fp16 * dest, __fp16 * a, __fp16 * b) {
     dest[i] = a[i] + b[i];
   }
 }
-/* { dg-final { scan-assembler-times {vadd\.f16 q[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vadd\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */
--- a/src/gcc/testsuite/gcc.target/arm/simd/mve-vadd-scalar-1.c
+++ b/src/gcc/testsuite/gcc.target/arm/simd/mve-vadd-scalar-1.c
@@ -24,9 +24,9 @@ FUNC_IMM(u, uint, 8, 16, +, vaddimm)
 
 /* For the moment we do not select the T2 vadd variant operating on a scalar
    final argument.  */
-/* { dg-final { scan-assembler-times {vadd\.i32  q[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */
-/* { dg-final { scan-assembler-times {vadd\.i16  q[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */
-/* { dg-final { scan-assembler-times {vadd\.i8  q[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vadd\.i32\tq[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vadd\.i16\tq[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vadd\.i8\tq[0-9]+, q[0-9]+, r[0-9]+} 2 { xfail *-*-* } } } */
 
 void test_vaddimm_f32 (float * dest, float * a) {
   int i;
@@ -34,7 +34,7 @@ void test_vaddimm_f32 (float * dest, float * a) {
     dest[i] = a[i] + 5.0;
   }
 }
-/* { dg-final { scan-assembler-times {vadd\.f32 q[0-9]+, q[0-9]+, r[0-9]+} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vadd\.f32\tq[0-9]+, q[0-9]+, r[0-9]+} 1 { xfail *-*-* } } } */
 
 /* Note that dest[i] = a[i] + 5.0f16 is not vectorized.  */
 void test_vaddimm_f16 (__fp16 * dest, __fp16 * a) {
@@ -44,4 +44,4 @@ void test_vaddimm_f16 (__fp16 * dest, __fp16 * a) {
     dest[i] = a[i] + b;
   }
 }
-/* { dg-final { scan-assembler-times {vadd\.f16 q[0-9]+, q[0-9]+, r[0-9]+} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vadd\.f16\tq[0-9]+, q[0-9]+, r[0-9]+} 1 { xfail *-*-* } } } */
--- a/src/gcc/testsuite/gcc.target/arm/simd/mve-vclz.c
+++ b/src/gcc/testsuite/gcc.target/arm/simd/mve-vclz.c
@@ -23,6 +23,6 @@ FUNC(u, uint, 8, clz)
 
 /* 16 and 8-bit versions are not vectorized because they need pack/unpack
    patterns since __builtin_clz uses 32-bit parameter and return value.  */
-/* { dg-final { scan-assembler-times {vclz\.i32  q[0-9]+, q[0-9]+} 2 } } */
-/* { dg-final { scan-assembler-times {vclz\.i16  q[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */
-/* { dg-final { scan-assembler-times {vclz\.i8  q[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vclz\.i32\tq[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vclz\.i16\tq[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {vclz\.i8\tq[0-9]+, q[0-9]+} 2 { xfail *-*-* } } } */
--- a/src/gcc/testsuite/gcc.target/arm/simd/mve-vcmp.c
+++ b/src/gcc/testsuite/gcc.target/arm/simd/mve-vcmp.c
@@ -36,15 +36,15 @@ ALL_FUNCS(>=, vcmpge)
 
 /* MVE has only 128-bit vectors, so we can vectorize only half of the
    functions above.  */
-/* { dg-final { scan-assembler-times {\tvcmp.i[0-9]+  eq, q[0-9]+, q[0-9]+\n} 6 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.i[0-9]+  ne, q[0-9]+, q[0-9]+\n} 6 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i[0-9]+\teq, q[0-9]+, q[0-9]+\n} 6 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.i[0-9]+\tne, q[0-9]+, q[0-9]+\n} 6 } } */
 
 /* lt, le, gt, ge apply to signed types, cs and hi to unsigned types.  */
 /* lt and le with unsigned types are replaced with the opposite condition, hence
    the double number of matches for cs and hi.  */
-/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+  lt, q[0-9]+, q[0-9]+\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+  le, q[0-9]+, q[0-9]+\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+  gt, q[0-9]+, q[0-9]+\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+  ge, q[0-9]+, q[0-9]+\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u[0-9]+  cs, q[0-9]+, q[0-9]+\n} 6 } } */
-/* { dg-final { scan-assembler-times {\tvcmp.u[0-9]+  hi, q[0-9]+, q[0-9]+\n} 6 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+\tlt, q[0-9]+, q[0-9]+\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+\tle, q[0-9]+, q[0-9]+\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+\tgt, q[0-9]+, q[0-9]+\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.s[0-9]+\tge, q[0-9]+, q[0-9]+\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u[0-9]+\tcs, q[0-9]+, q[0-9]+\n} 6 } } */
+/* { dg-final { scan-assembler-times {\tvcmp.u[0-9]+\thi, q[0-9]+, q[0-9]+\n} 6 } } */
--- a/src/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c
+++ b/src/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c
@@ -45,8 +45,8 @@ FUNC(f, float, 16, 8, -, vneg)
 
 /* MVE has only 128-bit vectors, so we can vectorize only half of the
    functions above.  */
-/* { dg-final { scan-assembler-times {vneg.s[0-9]+  q[0-9]+, q[0-9]+} 6 } } */
-/* { dg-final { scan-assembler-times {vneg.f[0-9]+  q[0-9]+, q[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vneg.s[0-9]+\tq[0-9]+, q[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {vneg.f[0-9]+\tq[0-9]+, q[0-9]+} 2 } } */
 /* { dg-final { scan-assembler-times {vldr[bhw].[0-9]+\tq[0-9]+} 8 } } */
 /* { dg-final { scan-assembler-times {vstr[bhw].[0-9]+\tq[0-9]+} 8 } } */
 /* { dg-final { scan-assembler-not {orr\tr[0-9]+, r[0-9]+, r[0-9]+} } } */
--- a/src/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
+++ b/src/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c
@@ -58,7 +58,7 @@ FUNC_IMM(u, uint, 8, 16, >>, vshrimm)
 /* Vector right shifts use vneg and left shifts.  */
 /* { dg-final { scan-assembler-times {vshl.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
 /* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */
-/* { dg-final { scan-assembler-times {vneg.s[0-9]+  q[0-9]+, q[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {vneg.s[0-9]+\tq[0-9]+, q[0-9]+} 6 } } */
 
 
 /* Shift by immediate.  */
--- a/src/gcc/testsuite/gcc.target/arm/simd/pr101325.c
+++ b/src/gcc/testsuite/gcc.target/arm/simd/pr101325.c
@@ -9,6 +9,6 @@ unsigned foo(int8x16_t v, int8x16_t w)
 {
   return vcmpeqq (v, w);
 }
-/* { dg-final { scan-assembler {\tvcmp.i8  eq} } } */
-/* { dg-final { scan-assembler {\tvmrs\tr[0-9]+, P0} } } */
+/* { dg-final { scan-assembler {\tvcmp.i8\teq} } } */
+/* { dg-final { scan-assembler {\tvmrs\tr[0-9]+, p0} } } */
 /* { dg-final { scan-assembler {\tuxth} } } */
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/avr/pr82931.c
@@ -0,0 +1,29 @@
+/* { dg-options "-Os" } */
+/* { dg-final { scan-assembler-times "bst" 4 } } */
+/* { dg-final { scan-assembler-times "bld" 4 } } */
+
+typedef __UINT8_TYPE__ uint8_t;
+typedef __UINT16_TYPE__ uint16_t;
+
+#define BitMask (1u << 14)
+#define Bit8Mask ((uint8_t) (1u << 4))
+
+void merge1_8 (uint8_t *dst, const uint8_t *src)
+{
+    *dst = (*src & Bit8Mask) | (*dst & ~ Bit8Mask);
+}
+
+void merge2_8 (uint8_t *dst, const uint8_t *src)
+{
+    *dst ^= (*dst ^ *src) & Bit8Mask;
+}
+
+void merge1_16 (uint16_t *dst, const uint16_t *src)
+{
+    *dst = (*src & BitMask) | (*dst & ~ BitMask);
+}
+
+void merge2_16 (uint16_t *dst, const uint16_t *src)
+{
+    *dst ^= (*dst ^ *src) & BitMask;
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/avr/torture/pr105753.c
@@ -0,0 +1,13 @@
+int digit_sum (unsigned long n)
+{
+  int sum = 0;
+
+  do
+    {
+      int x = n % 10;
+      n /= 10;
+      sum += x;
+    } while(n);
+
+  return sum;
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/avr/torture/pr109650-1.c
@@ -0,0 +1,63 @@
+/* { dg-do run } */
+/* { dg-options { -std=c99 } } */
+
+typedef _Bool bool;
+typedef __UINT8_TYPE__ uint8_t;
+
+static inline __attribute__((__always_inline__))
+bool func1a (bool p1, uint8_t p2)
+{
+  if (p1)
+    return p2 <= 8;
+  return p2 <= 2;
+}
+
+__attribute__((__noinline__, __noclone__))
+bool func1b (bool p1, uint8_t p2)
+{
+  return func1a (p1, p2);
+}
+
+static inline __attribute__((__always_inline__))
+bool func2a (bool p1, unsigned p2)
+{
+  if (p1)
+    return p2 <= 8;
+  return p2 <= 2;
+}
+
+__attribute__((__noinline__, __noclone__))
+bool func2b (bool p1, unsigned p2)
+{
+  return func2a (p1, p2);
+}
+
+void test1 (void)
+{
+  if (func1a (0, 1) != func1b (0, 1)) __builtin_abort();
+  if (func1a (0, 2) != func1b (0, 2)) __builtin_abort();
+  if (func1a (0, 3) != func1b (0, 3)) __builtin_abort();
+
+  if (func1a (1, 7) != func1b (1, 7)) __builtin_abort();
+  if (func1a (1, 8) != func1b (1, 8)) __builtin_abort();
+  if (func1a (1, 9) != func1b (1, 9)) __builtin_abort();
+}
+
+void test2 (void)
+{
+  if (func2a (0, 1) != func2b (0, 1)) __builtin_abort();
+  if (func2a (0, 2) != func2b (0, 2)) __builtin_abort();
+  if (func2a (0, 3) != func2b (0, 3)) __builtin_abort();
+
+  if (func2a (1, 7) != func2b (1, 7)) __builtin_abort();
+  if (func2a (1, 8) != func2b (1, 8)) __builtin_abort();
+  if (func2a (1, 9) != func2b (1, 9)) __builtin_abort();
+}
+
+int main (void)
+{
+  test1();
+  test2();
+
+  __builtin_exit (0);
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/avr/torture/pr109650-2.c
@@ -0,0 +1,79 @@
+/* { dg-do run } */
+
+typedef __UINT8_TYPE__ uint8_t;
+
+#define AI static __inline__ __attribute__((__always_inline__))
+#define NI __attribute__((__noinline__,__noclone__))
+
+AI uint8_t func1_eq (uint8_t c, unsigned x)
+{
+  if (x == c)
+    return 1;
+  return 0;
+}
+
+AI uint8_t func1_ne (uint8_t c, unsigned x)
+{
+  if (x != c)
+    return 1;
+  return 0;
+}
+
+AI uint8_t func1_ltu (uint8_t c, unsigned x)
+{
+  if (x < c)
+    return 1;
+  return 0;
+}
+
+AI uint8_t func1_leu (uint8_t c, unsigned x)
+{
+  if (x <= c)
+    return 1;
+  return 0;
+}
+
+AI uint8_t func1_gtu (uint8_t c, unsigned x)
+{
+  if (x > c)
+    return 1;
+  return 0;
+}
+
+AI uint8_t func1_geu (uint8_t c, unsigned x)
+{
+  if (x >= c)
+    return 1;
+  return 0;
+}
+
+NI uint8_t func2_eq (uint8_t c, unsigned x) { return func1_eq (c, x); }
+NI uint8_t func2_ne (uint8_t c, unsigned x) { return func1_ne (c, x); }
+NI uint8_t func2_ltu (uint8_t c, unsigned x) { return func1_ltu (c, x); }
+NI uint8_t func2_leu (uint8_t c, unsigned x) { return func1_leu (c, x); }
+NI uint8_t func2_gtu (uint8_t c, unsigned x) { return func1_gtu (c, x); }
+NI uint8_t func2_geu (uint8_t c, unsigned x) { return func1_geu (c, x); }
+
+AI void test4 (uint8_t c, unsigned x)
+{
+  if (func2_eq (c, x) != func1_eq (c, x)) __builtin_abort();
+  if (func2_ne (c, x) != func1_ne (c, x)) __builtin_abort();
+  if (func2_ltu (c, x) != func1_ltu (c, x)) __builtin_abort();
+  if (func2_leu (c, x) != func1_leu (c, x)) __builtin_abort();
+  if (func2_gtu (c, x) != func1_gtu (c, x)) __builtin_abort();
+  if (func2_geu (c, x) != func1_geu (c, x)) __builtin_abort();
+}
+
+int main (void)
+{
+  test4 (127, 127);
+  test4 (127, 128);
+  test4 (128, 127);
+
+  test4 (0x42, 0x142);
+  test4 (0x0, 0x100);
+  test4 (0x0, 0x0);
+  test4 (0x0, 0x1);
+
+  __builtin_exit (0);
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/i386/pr110108-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2 -funsigned-char" } */
+/* { dg-final { scan-assembler-times "vpblendvb" 2 } } */
+
+#include <immintrin.h>
+__m128i do_stuff_128(__m128i X0, __m128i X1, __m128i X2) {
+  __m128i Result = _mm_blendv_epi8(X0, X1, X2);
+  return Result;
+}
+
+__m256i do_stuff_256(__m256i X0, __m256i X1, __m256i X2) {
+  __m256i Result = _mm256_blendv_epi8(X0, X1, X2);
+  return Result;
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-0.c
@@ -0,0 +1,23 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+#include "darwin-structs-0.h"
+
+int tcd[sizeof(cd) != 12 ? -1 : 1];
+int acd[__alignof__(cd) != 4 ? -1 : 1];
+
+int sdc[sizeof(dc) != 16 ? -1 : 1];
+int adc[__alignof__(dc) != 8 ? -1 : 1];
+
+int scL[sizeof(cL) != 12 ? -1 : 1];
+int acL[__alignof__(cL) != 4 ? -1 : 1];
+
+int sLc[sizeof(Lc) != 16 ? -1 : 1];
+int aLc[__alignof__(Lc) != 8 ? -1 : 1];
+
+int scD[sizeof(cD) != 32 ? -1 : 1];
+int acD[__alignof__(cD) != 16 ? -1 : 1];
+
+int sDc[sizeof(Dc) != 32 ? -1 : 1];
+int aDc[__alignof__(Dc) != 16 ? -1 : 1];
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+#pragma pack(push, 1)
+
+#include "darwin-structs-0.h"
+
+int tcd[sizeof(cd) != 9 ? -1 : 1];
+int acd[__alignof__(cd) != 1 ? -1 : 1];
+
+int sdc[sizeof(dc) != 9 ? -1 : 1];
+int adc[__alignof__(dc) != 1 ? -1 : 1];
+
+int scL[sizeof(cL) != 9 ? -1 : 1];
+int acL[__alignof__(cL) != 1 ? -1 : 1];
+
+int sLc[sizeof(Lc) != 9 ? -1 : 1];
+int aLc[__alignof__(Lc) != 1 ? -1 : 1];
+
+int scD[sizeof(cD) != 17 ? -1 : 1];
+int acD[__alignof__(cD) != 1 ? -1 : 1];
+
+int sDc[sizeof(Dc) != 17 ? -1 : 1];
+int aDc[__alignof__(Dc) != 1 ? -1 : 1];
+
+#pragma pack(pop)
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/powerpc/darwin-abi-13-2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+#pragma pack(push, 2)
+
+#include "darwin-structs-0.h"
+
+int tcd[sizeof(cd) != 10 ? -1 : 1];
+int acd[__alignof__(cd) != 2 ? -1 : 1];
+
+int sdc[sizeof(dc) != 10 ? -1 : 1];
+int adc[__alignof__(dc) != 2 ? -1 : 1];
+
+int scL[sizeof(cL) != 10 ? -1 : 1];
+int acL[__alignof__(cL) != 2 ? -1 : 1];
+
+int sLc[sizeof(Lc) != 10 ? -1 : 1];
+int aLc[__alignof__(Lc) != 2 ? -1 : 1];
+
+int scD[sizeof(cD) != 18 ? -1 : 1];
+int acD[__alignof__(cD) != 2 ? -1 : 1];
+
+int sDc[sizeof(Dc) != 18 ? -1 : 1];
+int aDc[__alignof__(Dc) != 2 ? -1 : 1];
+
+#pragma pack(pop)
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/powerpc/darwin-structs-0.h
@@ -0,0 +1,29 @@
+typedef struct _cd {
+ char c;
+ double d;
+} cd;
+
+typedef struct _dc {
+ double d;
+ char c;
+} dc;
+
+typedef struct _cL {
+ char c;
+ long long L;
+} cL;
+
+typedef struct _Lc {
+ long long L;
+ char c;
+} Lc;
+
+typedef struct _cD {
+ char c;
+ long double D;
+} cD;
+
+typedef struct _Dc {
+ long double D;
+ char c;
+} Dc;
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/powerpc/pr109069-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vmx_hw } */
+/* { dg-options "-O2 -maltivec" } */
+
+/* Verify it run successfully.  */
+
+#include <altivec.h>
+
+__attribute__ ((noipa))
+vector signed int
+test ()
+{
+  vector signed int v = {-16, -16, -16, -16};
+  vector signed int res = vec_sld (v, v, 3);
+  return res;
+}
+
+int
+main ()
+{
+  vector signed int res = test ();
+  if (res[0] != 0xf0ffffff)
+    __builtin_abort ();
+  return 0;
+}
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/powerpc/pr109069-2-run.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vsx_hw } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Verify it doesn't generate wrong code.  */
+
+#include "pr109069-2.h"
+
+int
+main ()
+{
+  vector unsigned char res1 = test1 ();
+  for (int i = 0; i < 16; i++)
+    if (res1[i] != 0xd)
+      __builtin_abort ();
+
+  vector signed short res2 = test2 ();
+  for (int i = 0; i < 8; i++)
+    if (res2[i] != 0x7777)
+      __builtin_abort ();
+
+  vector signed int res3 = test3 ();
+  vector unsigned int res4 = test4 ();
+  vector float res6 = test6 ();
+  for (int i = 0; i < 4; i++)
+    {
+      if (res3[i] != 0xbbbbbbbb)
+	__builtin_abort ();
+      if (res4[i] != 0x7070707)
+	__builtin_abort ();
+      U32b u;
+      u.f = res6[i];
+      if (u.i != 0x17171717)
+	__builtin_abort ();
+    }
+
+  vector unsigned long long res5 = test5 ();
+  vector double res7 = test7 ();
+  for (int i = 0; i < 2; i++)
+    {
+      if (res5[i] != 0x4545454545454545ll)
+	__builtin_abort ();
+      U64b u;
+      u.f = res7[i];
+      if (u.i != 0x5454545454545454ll)
+	__builtin_abort ();
+    }
+  return 0;
+}
+
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/powerpc/pr109069-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* Disable rs6000 optimize_swaps as it drops some REG_EQUAL
+   notes on const vector and affects test point here.  */
+/* { dg-options "-O2 -mvsx -mno-optimize-swaps" } */
+
+/* Verify we can optimize away vector shifting if every byte
+   of vector is the same.  */
+
+#include "pr109069-2.h"
+
+/* { dg-final { scan-assembler-not {\mvsldoi\M} } } */
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/powerpc/pr109069-2.h
@@ -0,0 +1,83 @@
+#include <altivec.h>
+
+typedef union
+{
+  unsigned int i;
+  float f;
+} U32b;
+
+typedef union
+{
+  unsigned long long i;
+  double f;
+} U64b;
+
+__attribute__ ((noipa))
+vector unsigned char
+test1 ()
+{
+  vector unsigned char v = {0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd,
+			    0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd, 0xd};
+  vector unsigned char res = vec_sld (v, v, 3);
+  return res;
+}
+
+__attribute__ ((noipa))
+vector signed short
+test2 ()
+{
+  vector signed short v
+    = {0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777, 0x7777};
+  vector signed short res = vec_sld (v, v, 5);
+  return res;
+}
+
+__attribute__ ((noipa))
+vector signed int
+test3 ()
+{
+  vector signed int v = {0xbbbbbbbb, 0xbbbbbbbb, 0xbbbbbbbb, 0xbbbbbbbb};
+  vector signed int res = vec_sld (v, v, 7);
+  return res;
+}
+
+__attribute__ ((noipa))
+vector unsigned int
+test4 ()
+{
+  vector unsigned int v = {0x07070707, 0x07070707, 0x07070707, 0x07070707};
+  vector unsigned int res = vec_sld (v, v, 9);
+  return res;
+}
+
+__attribute__ ((noipa))
+vector unsigned long long
+test5 ()
+{
+  vector unsigned long long v = {0x4545454545454545ll, 0x4545454545454545ll};
+  vector unsigned long long res = vec_sld (v, v, 10);
+  return res;
+}
+
+__attribute__ ((noipa))
+vector float
+test6 ()
+{
+  U32b u;
+  u.i = 0x17171717;
+  vector float vf = {u.f, u.f, u.f, u.f};
+  vector float res = vec_sld (vf, vf, 11);
+  return res;
+}
+
+__attribute__ ((noipa))
+vector double
+test7 ()
+{
+  U64b u;
+  u.i = 0x5454545454545454ll;
+  vector double vf = {u.f, u.f};
+  vector double res = vec_sld (vf, vf, 13);
+  return res;
+}
+
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/powerpc/pr70243.c
@@ -0,0 +1,41 @@
+/* { dg-do compile */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* PR 70423, Make sure we don't generate vmaddfp or vnmsubfp.  These
+   instructions have different rounding modes than the VSX instructions
+   xvmaddsp and xvnmsubsp.  These tests are written where the 3 inputs and
+   target are all separate registers.  Because vmaddfp and vnmsubfp are no
+   longer generated the compiler will have to generate an xsmaddsp or xsnmsubsp
+   instruction followed by a move operation.  */
+
+#include <altivec.h>
+
+vector float
+do_add1 (vector float dummy, vector float a, vector float b, vector float c)
+{
+  return (a * b) + c;
+}
+
+vector float
+do_nsub1 (vector float dummy, vector float a, vector float b, vector float c)
+{
+  return -((a * b) - c);
+}
+
+vector float
+do_add2 (vector float dummy, vector float a, vector float b, vector float c)
+{
+  return vec_madd (a, b, c);
+}
+
+vector float
+do_nsub2 (vector float dummy, vector float a, vector float b, vector float c)
+{
+  return vec_nmsub (a, b, c);
+}
+
+/* { dg-final { scan-assembler     {\mxvmadd[am]sp\M}  } } */
+/* { dg-final { scan-assembler     {\mxvnmsub[am]sp\M} } } */
+/* { dg-final { scan-assembler-not {\mvmaddfp\M}       } } */
+/* { dg-final { scan-assembler-not {\mvnmsubfp\M}      } } */
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gfortran.dg/ptr-func-5.f90
@@ -0,0 +1,39 @@
+! { dg-do compile }
+! PR fortran/109846
+! CLASS pointer function result in variable definition context
+
+module foo
+  implicit none
+  type :: parameter_list
+  contains
+    procedure :: sublist, sublist_nores
+  end type
+contains
+  function sublist (this) result (slist)
+    class(parameter_list), intent(inout) :: this
+    class(parameter_list), pointer       :: slist
+    allocate (slist)
+  end function
+  function sublist_nores (this)
+    class(parameter_list), intent(inout) :: this
+    class(parameter_list), pointer       :: sublist_nores
+    allocate (sublist_nores)
+  end function
+end module
+
+program example
+  use foo
+  implicit none
+  type(parameter_list) :: plist
+  call sub1 (plist%sublist())
+  call sub1 (plist%sublist_nores())
+  call sub2 (plist%sublist())
+  call sub2 (plist%sublist_nores())
+contains
+  subroutine sub1 (plist)
+    type(parameter_list), intent(inout) :: plist
+  end subroutine
+  subroutine sub2 (plist)
+    type(parameter_list) :: plist
+  end subroutine
+end program
new file mode 100644
--- /dev/null
+++ b/src/gcc/testsuite/gfortran.dg/select_rank_6.f90
@@ -0,0 +1,48 @@
+! { dg-do compile }
+! PR fortran/100607 - fix diagnostics for SELECT RANK
+! Contributed by T.Burnus
+
+program p
+  implicit none
+  integer, allocatable :: A(:,:,:)
+
+  allocate(a(5:6,-2:2, 99:100))
+  call foo(a)
+  call bar(a)
+
+contains
+
+  subroutine foo(x)
+    integer, allocatable :: x(..)
+    if (rank(x) /= 3) stop 1
+    if (any (lbound(x) /= [5, -2, 99])) stop 2
+
+    select rank (x)
+    rank(3)
+      if (any (lbound(x) /= [5, -2, 99])) stop 3
+    end select
+
+    select rank (x) ! { dg-error "pointer or allocatable selector at .2." }
+    rank(*)         ! { dg-error "pointer or allocatable selector at .2." }
+      if (rank(x) /= 1) stop 4
+      if (lbound(x, 1) /= 1) stop 5
+    end select
+  end
+
+  subroutine bar(x)
+    integer :: x(..)
+    if (rank(x) /= 3) stop 6
+    if (any (lbound(x) /= 1)) stop 7
+
+    select rank (x)
+    rank(3)
+      if (any (lbound(x) /= 1)) stop 8
+    end select
+
+    select rank (x)
+    rank(*)
+      if (rank(x) /= 1) stop 9
+      if (lbound(x, 1) /= 1) stop 10
+    end select
+  end
+end
--- a/src/gcc/tree-ssa-ccp.cc
+++ b/src/gcc/tree-ssa-ccp.cc
@@ -1552,6 +1552,8 @@ bit_value_binop (enum tree_code code, signop sgn, int width,
 		  *mask = wi::lrotate (r1mask, shift, width);
 		  *val = wi::lrotate (r1val, shift, width);
 		}
+	      *mask = wi::ext (*mask, width, sgn);
+	      *val = wi::ext (*val, width, sgn);
 	    }
 	}
       else if (wi::ltu_p (r2val | r2mask, width)
@@ -1593,8 +1595,8 @@ bit_value_binop (enum tree_code code, signop sgn, int width,
 	      /* Accumulate the result.  */
 	      res_mask |= tmp_mask | (res_val ^ tmp_val);
 	    }
-	  *val = wi::bit_and_not (res_val, res_mask);
-	  *mask = res_mask;
+	  *val = wi::ext (wi::bit_and_not (res_val, res_mask), width, sgn);
+	  *mask = wi::ext (res_mask, width, sgn);
 	}
       break;
 
--- a/src/gcc/tree-vect-loop.cc
+++ b/src/gcc/tree-vect-loop.cc
@@ -2874,7 +2874,7 @@ vect_analyze_loop_1 (class loop *loop, vec_info_shared *shared,
 		     res ? "succeeded" : " failed",
 		     GET_MODE_NAME (loop_vinfo->vector_mode));
 
-  if (!main_loop_vinfo && suggested_unroll_factor > 1)
+  if (res && !main_loop_vinfo && suggested_unroll_factor > 1)
     {
       if (dump_enabled_p ())
 	dump_printf_loc (MSG_NOTE, vect_location,
--- a/src/gcc/wide-int.h
+++ b/src/gcc/wide-int.h
@@ -3169,9 +3169,11 @@ wi::lrotate (const T1 &x, const T2 &y, unsigned int width)
     width = precision;
   WI_UNARY_RESULT (T2) ymod = umod_trunc (y, width);
   WI_UNARY_RESULT (T1) left = wi::lshift (x, ymod);
-  WI_UNARY_RESULT (T1) right = wi::lrshift (x, wi::sub (width, ymod));
+  WI_UNARY_RESULT (T1) right
+    = wi::lrshift (width != precision ? wi::zext (x, width) : x,
+		   wi::sub (width, ymod));
   if (width != precision)
-    return wi::zext (left, width) | wi::zext (right, width);
+    return wi::zext (left, width) | right;
   return left | right;
 }
 
@@ -3186,10 +3188,11 @@ wi::rrotate (const T1 &x, const T2 &y, unsigned int width)
   if (width == 0)
     width = precision;
   WI_UNARY_RESULT (T2) ymod = umod_trunc (y, width);
-  WI_UNARY_RESULT (T1) right = wi::lrshift (x, ymod);
+  WI_UNARY_RESULT (T1) right
+    = wi::lrshift (width != precision ? wi::zext (x, width) : x, ymod);
   WI_UNARY_RESULT (T1) left = wi::lshift (x, wi::sub (width, ymod));
   if (width != precision)
-    return wi::zext (left, width) | wi::zext (right, width);
+    return wi::zext (left, width) | right;
   return left | right;
 }
 
--- a/src/libffi/ChangeLog
+++ b/src/libffi/ChangeLog
@@ -1,3 +1,11 @@
+2023-05-09  Dan Horák  <dan@danny.cz>
+
+	Backported from master:
+	2023-05-06  Dan Horák  <dan@danny.cz>
+
+	PR libffi/109447
+	* src/powerpc/ffi_linux64.c (ffi_prep_args64): Update arg.f128 pointer.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
--- a/src/libffi/src/powerpc/ffi_linux64.c
+++ b/src/libffi/src/powerpc/ffi_linux64.c
@@ -680,7 +680,7 @@ ffi_prep_args64 (extended_cif *ecif, unsigned long *const stack)
                     {
                       if (vecarg_count < NUM_VEC_ARG_REGISTERS64
                           && i < nfixedargs)
-		        memcpy (vec_base.f128++, arg.f128, sizeof (float128));
+		        memcpy (vec_base.f128++, arg.f128++, sizeof (float128));
                       else
 		        memcpy (next_arg.f128, arg.f128++, sizeof (float128));
                       if (++next_arg.f128 == gpr_end.f128)
--- a/src/libgcc/ChangeLog
+++ b/src/libgcc/ChangeLog
@@ -1,3 +1,19 @@
+2023-05-21  Iain Sandoe  <iain@sandoe.co.uk>
+
+	Backported from master:
+	2023-05-19  Iain Sandoe  <iain@sandoe.co.uk>
+
+	* config.host: Arrange to set min Darwin OS versions from
+	the configured host version.
+	* config/darwin10-unwind-find-enc-func.c: Do not use current
+	headers, but declare the nexessary structures locally to the
+	versions in use for Mac OSX 10.6.
+	* config/t-darwin: Amend to handle configured min OS
+	versions.
+	* config/t-darwin-min-1: New.
+	* config/t-darwin-min-5: New.
+	* config/t-darwin-min-8: New.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
--- a/src/libgcc/config.host
+++ b/src/libgcc/config.host
@@ -241,6 +241,24 @@ case ${host} in
       ;;
   esac
   tmake_file="$tmake_file t-slibgcc-darwin"
+  # newer toolsets produce warnings when building for unsupported versions.
+  case ${host} in
+    *-*-darwin1[89]* | *-*-darwin2* )
+      tmake_file="t-darwin-min-8 $tmake_file"
+      ;;
+    *-*-darwin9* | *-*-darwin1[0-7]*)
+      tmake_file="t-darwin-min-5 $tmake_file"
+      ;;
+    *-*-darwin[4-8]*)
+      tmake_file="t-darwin-min-1 $tmake_file"
+      ;;
+    *)
+      # Fall back to configuring for the oldest system known to work with
+      # all archs and the current sources.
+      tmake_file="t-darwin-min-5 $tmake_file"
+      echo "Warning: libgcc configured to support macOS 10.5" 1>&2
+      ;;
+  esac
   extra_parts="crt3.o libd10-uwfef.a crttms.o crttme.o libemutls_w.a"
   ;;
 *-*-dragonfly*)
--- a/src/libgcc/config/darwin10-unwind-find-enc-func.c
+++ b/src/libgcc/config/darwin10-unwind-find-enc-func.c
@@ -1,8 +1,34 @@
-#include "tconfig.h"
-#include "tsystem.h"
-#include "unwind-dw2-fde.h"
 #include "libgcc_tm.h"
 
+/* This shim is special, it needs to be built for Mac OSX 10.6
+   regardless of the current system version.
+   We must also build it to use the unwinder layout that was
+   present for 10.6 (and not update that).
+   So we copy the referenced structures from unwind-dw2-fde.h
+   to avoid pulling in newer system headers and/or changed
+   layouts.  */
+struct dwarf_eh_bases
+{
+  void *tbase;
+  void *dbase;
+  void *func;
+};
+
+typedef          int  sword __attribute__ ((mode (SI)));
+typedef unsigned int  uword __attribute__ ((mode (SI)));
+
+/* The first few fields of an FDE.  */
+struct dwarf_fde
+{
+  uword length;
+  sword CIE_delta;
+  unsigned char pc_begin[];
+} __attribute__ ((packed, aligned (__alignof__ (void *))));
+
+typedef struct dwarf_fde fde;
+
+extern const fde * _Unwind_Find_FDE (void *, struct dwarf_eh_bases *);
+
 void *
 _darwin10_Unwind_FindEnclosingFunction (void *pc)
 {
@@ -10,5 +36,5 @@ _darwin10_Unwind_FindEnclosingFunction (void *pc)
   const struct dwarf_fde *fde = _Unwind_Find_FDE (pc-1, &bases);
   if (fde)
     return bases.func;
-  return NULL;
+  return (void *) 0;
 }
--- a/src/libgcc/config/t-darwin
+++ b/src/libgcc/config/t-darwin
@@ -1,15 +1,15 @@
 # Set this as a minimum (unless overriden by arch t-files) since it's a
 # reasonable lowest common denominator that works for all our archs.
-HOST_LIBGCC2_CFLAGS += -mmacosx-version-min=10.4
+HOST_LIBGCC2_CFLAGS += $(DARWIN_MIN_LIB_VERSION)
 
 crt3.o: $(srcdir)/config/darwin-crt3.c
-	$(crt_compile) -mmacosx-version-min=10.4 -c $<
+	$(crt_compile) $(DARWIN_MIN_CRT_VERSION) -c $<
 
 crttms.o: $(srcdir)/config/darwin-crt-tm.c
-	$(crt_compile) -mmacosx-version-min=10.4 -DSTART -c $<
+	$(crt_compile) $(DARWIN_MIN_CRT_VERSION) -DSTART -c $<
 
 crttme.o: $(srcdir)/config/darwin-crt-tm.c
-	$(crt_compile) -mmacosx-version-min=10.4 -DEND -c $<
+	$(crt_compile) $(DARWIN_MIN_CRT_VERSION) -DEND -c $<
 
 # Make emutls weak so that we can deal with -static-libgcc, override the
 # hidden visibility when this is present in libgcc_eh.
@@ -25,6 +25,8 @@ libemutls_w.a: emutls_s.o
 	$(RANLIB_FOR_TARGET) $@
 
 # Patch to __Unwind_Find_Enclosing_Function for Darwin10.
+# This needs to be built for darwin10, regardless of the current platform
+# version.
 d10-uwfef.o: $(srcdir)/config/darwin10-unwind-find-enc-func.c libgcc_tm.h
 	$(crt_compile) -mmacosx-version-min=10.6 -c $<
 
new file mode 100644
--- /dev/null
+++ b/src/libgcc/config/t-darwin-min-1
@@ -0,0 +1,3 @@
+# Support building with -mmacosx-version-min back to 10.1.
+DARWIN_MIN_LIB_VERSION = -mmacosx-version-min=10.4
+DARWIN_MIN_CRT_VERSION = -mmacosx-version-min=10.1
new file mode 100644
--- /dev/null
+++ b/src/libgcc/config/t-darwin-min-5
@@ -0,0 +1,3 @@
+# Support building with -mmacosx-version-min back to 10.5.
+DARWIN_MIN_LIB_VERSION = -mmacosx-version-min=10.5
+DARWIN_MIN_CRT_VERSION = -mmacosx-version-min=10.5
new file mode 100644
--- /dev/null
+++ b/src/libgcc/config/t-darwin-min-8
@@ -0,0 +1,3 @@
+# Support building with -mmacosx-version-min back to 10.8.
+DARWIN_MIN_LIB_VERSION = -mmacosx-version-min=10.8
+DARWIN_MIN_CRT_VERSION = -mmacosx-version-min=10.8
--- a/src/libgo/go/syscall/libcall_linux.go
+++ b/src/libgo/go/syscall/libcall_linux.go
@@ -188,6 +188,14 @@ func Gettid() (tid int) {
 //sys	PivotRoot(newroot string, putold string) (err error)
 //pivot_root(newroot *byte, putold *byte) _C_int
 
+// Used by golang.org/x/sys/unix.
+//sys	prlimit(pid int, resource int, newlimit *Rlimit, oldlimit *Rlimit) (err error)
+//prlimit(pid Pid_t, resource _C_int, newlimit *Rlimit, oldlimit *Rlimit) _C_int
+
+func Prlimit(pid int, resource int, newlimit *Rlimit, oldlimit *Rlimit) error {
+	return prlimit(pid, resource, newlimit, oldlimit)
+}
+
 //sys	Removexattr(path string, attr string) (err error)
 //removexattr(path *byte, name *byte) _C_int
 
--- a/src/libphobos/ChangeLog
+++ b/src/libphobos/ChangeLog
@@ -1,3 +1,7 @@
+2023-06-06  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	* src/MERGE: Merge upstream phobos 8e8aaae50.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
--- a/src/libphobos/src/MERGE
+++ b/src/libphobos/src/MERGE
@@ -1,4 +1,4 @@
-5fef0d28fc873fb5a0dbfb9149759d76a7b9f1b7
+8e8aaae5080ccc2e0a2202cbe9778dca96496a95
 
 The first line of this file holds the git revision number of the last
 merge done from the dlang/phobos repository.
--- a/src/libphobos/src/std/container/array.d
+++ b/src/libphobos/src/std/container/array.d
@@ -412,9 +412,9 @@ if (!is(immutable T == immutable bool))
                     .destroy(e);
 
             static if (hasIndirections!T)
-                GC.removeRange(_payload.ptr);
+                GC.removeRange(cast(void*) _payload.ptr);
 
-            free(_payload.ptr);
+            free(cast(void*) _payload.ptr);
         }
 
         this(this) @disable;
@@ -489,14 +489,14 @@ if (!is(immutable T == immutable bool))
                 auto newPayload = newPayloadPtr[0 .. oldLength];
 
                 // copy old data over to new array
-                memcpy(newPayload.ptr, _payload.ptr, T.sizeof * oldLength);
+                memcpy(cast(void*) newPayload.ptr, cast(void*) _payload.ptr, T.sizeof * oldLength);
                 // Zero out unused capacity to prevent gc from seeing false pointers
-                memset(newPayload.ptr + oldLength,
+                memset( cast(void*) (newPayload.ptr + oldLength),
                         0,
                         (elements - oldLength) * T.sizeof);
-                GC.addRange(newPayload.ptr, sz);
-                GC.removeRange(_payload.ptr);
-                free(_payload.ptr);
+                GC.addRange(cast(void*) newPayload.ptr, sz);
+                GC.removeRange(cast(void*) _payload.ptr);
+                free(cast(void*) _payload.ptr);
                 _payload = newPayload;
             }
             else
@@ -611,12 +611,17 @@ if (!is(immutable T == immutable bool))
         return opEquals(rhs);
     }
 
+    // fix https://issues.dlang.org/show_bug.cgi?23140
+    private alias Unshared(T) = T;
+    private alias Unshared(T: shared U, U) = U;
+
     /// ditto
     bool opEquals(ref const Array rhs) const
     {
         if (empty) return rhs.empty;
         if (rhs.empty) return false;
-        return _data._payload == rhs._data._payload;
+
+        return cast(Unshared!(T)[]) _data._payload ==  cast(Unshared!(T)[]) rhs._data._payload;
     }
 
     /**
@@ -1740,6 +1745,16 @@ if (!is(immutable T == immutable bool))
     assertThrown!AssertError(array.length = 5);
 }
 
+// https://issues.dlang.org/show_bug.cgi?id=23140
+@system unittest
+{
+    shared class C
+    {
+    }
+
+    Array!C ac;
+    ac = Array!C([new C]);
+}
 ////////////////////////////////////////////////////////////////////////////////
 // Array!bool
 ////////////////////////////////////////////////////////////////////////////////
--- a/src/libphobos/src/std/typecons.d
+++ b/src/libphobos/src/std/typecons.d
@@ -3793,8 +3793,28 @@ Params:
                 sink.formatValue(_value, fmt);
             }
         }
+
+        void toString()(scope void delegate(const(char)[]) sink, scope const ref FormatSpec!char fmt) const
+        {
+            if (isNull)
+            {
+                sink.formatValue("Nullable.null", fmt);
+            }
+            else
+            {
+                sink.formatValue(_value, fmt);
+            }
+        }
     }
 
+@system unittest
+{
+    import std.conv : to;
+
+    const Nullable!(ulong, 0) x = 1;
+    assert(x.to!string == "1");
+}
+
 /**
 Check if `this` is in the null state.
 
@@ -4320,8 +4340,28 @@ Params:
                 sink.formatValue(*_value, fmt);
             }
         }
+
+        void toString()(scope void delegate(const(char)[]) sink, scope const ref FormatSpec!char fmt) const
+        {
+            if (isNull)
+            {
+                sink.formatValue("Nullable.null", fmt);
+            }
+            else
+            {
+                sink.formatValue(*_value, fmt);
+            }
+        }
     }
 
+@system unittest
+{
+    import std.conv : to;
+
+    const NullableRef!(ulong) x = new ulong(1);
+    assert(x.to!string == "1");
+}
+
 /**
 Binds the internal state to `value`.
 
--- a/src/libsanitizer/ChangeLog
+++ b/src/libsanitizer/ChangeLog
@@ -1,3 +1,11 @@
+2023-05-21  Iain Sandoe  <iain@sandoe.co.uk>
+
+	Backported from master:
+	2023-04-18  Iain Sandoe  <iain@sandoe.co.uk>
+
+	* configure.tgt: Unsupport Darwin22+ until a mechanism can be found
+	to locate dyld in the shared cache.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
--- a/src/libsanitizer/configure.tgt
+++ b/src/libsanitizer/configure.tgt
@@ -64,7 +64,7 @@ case "${target}" in
 		HWASAN_SUPPORTED=yes
 	fi
 	;;
-  x86_64-*-darwin2* | x86_64-*-darwin1[2-9]* | i?86-*-darwin1[2-9]*)
+  x86_64-*-darwin2[01]* | x86_64-*-darwin1[2-9]* | i?86-*-darwin1[2-9]*)
 	TSAN_SUPPORTED=no
 	EXTRA_CXXFLAGS="${EXTRA_CXXFLAGS} -Wl,-undefined,dynamic_lookup"
 	;;
--- a/src/libstdc++-v3/ChangeLog
+++ b/src/libstdc++-v3/ChangeLog
@@ -1,3 +1,320 @@
+2023-05-30  Alexandre Oliva  <oliva@adacore.com>
+
+	Backported from master:
+	2023-05-30  Alexandre Oliva  <oliva@adacore.com>
+
+	* testsuite/20_util/from_chars/4.cc: Skip long double test06
+	on x86_64-vxworks.
+	* testsuite/20_util/to_chars/long_double.cc: Xfail run on
+	x86_64-vxworks.
+
+2023-05-30  Alexandre Oliva  <oliva@adacore.com>
+
+	Backported from master:
+	2023-05-25  Alexandre Oliva  <oliva@adacore.com>
+
+	* testsuite/20_util/to_chars/long_double.cc: Expect execution
+	fail on x86-vxworks.
+
+2023-05-30  Alexandre Oliva  <oliva@adacore.com>
+
+	Backported from master:
+	2023-05-05  Alexandre Oliva  <oliva@adacore.com>
+
+	* testsuite/20_util/from_chars/4.cc: Skip long double test06
+	on aarch64-vxworks.
+	* testsuite/20_util/to_chars/long_double.cc: Xfail run on
+	aarch64-vxworks.
+
+2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/109822
+	* include/experimental/bits/simd.h (to_native): Use int NTTP
+	as specified in PTS2.
+	(to_compatible): Likewise. Add missing tag to call mask
+	generator ctor.
+	* testsuite/experimental/simd/pr109822_cast_functions.cc: New
+	test.
+
+2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	* testsuite/experimental/simd/tests/integer_operators.cc:
+	Compute expected value differently to avoid getting turned into
+	a vector shift.
+
+2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	* testsuite/experimental/simd/tests/operator_cvt.cc: Make long
+	double <-> (u)long conversion tests conditional on sizeof(long
+	double) and sizeof(long).
+
+2023-05-30  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-26  Matthias Kretz  <m.kretz@gsi.de>
+
+	* include/experimental/bits/simd_ppc.h (_S_bit_shift_left):
+	Negative __y is UB, so prefer signed compare.
+
+2023-05-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/109949
+	* include/experimental/bits/simd.h (__intrinsic_type): If
+	__ALTIVEC__ is defined, map gnu::vector_size types to their
+	corresponding __vector T types without losing unsignedness of
+	integer types. Also prefer long long over long.
+	* include/experimental/bits/simd_ppc.h (_S_popcount): Cast mask
+	object to the expected unsigned vector type.
+
+2023-05-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/109261
+	* include/experimental/bits/simd.h (__intrinsic_type):
+	Specialize __intrinsic_type<double, 8> and
+	__intrinsic_type<double, 16> in any case, but provide the member
+	type only with __aarch64__.
+
+2023-05-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/109261
+	* include/experimental/bits/simd_neon.h (_S_reduce): Add
+	constexpr and make NEON implementation conditional on
+	not __builtin_is_constant_evaluated.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/109261
+	* include/experimental/bits/simd.h (_SimdWrapper::_M_set):
+	Avoid vector builtin subscripting in constant expressions.
+	(resizing_simd_cast): Avoid memcpy if constant_evaluated.
+	(const_where_expression, where_expression, where)
+	(__extract_part, simd_mask, _SimdIntOperators, simd): Add either
+	_GLIBCXX_SIMD_CONSTEXPR (on public APIs), or constexpr (on
+	internal APIs).
+	* include/experimental/bits/simd_builtin.h (__vector_permute)
+	(__vector_shuffle, __extract_part, _GnuTraits::_SimdCastType1)
+	(_GnuTraits::_SimdCastType2, _SimdImplBuiltin)
+	(_MaskImplBuiltin::_S_store): Add constexpr.
+	(_CommonImplBuiltin::_S_store_bool_array)
+	(_SimdImplBuiltin::_S_load, _SimdImplBuiltin::_S_store)
+	(_SimdImplBuiltin::_S_reduce, _MaskImplBuiltin::_S_load): Add
+	constant_evaluated case.
+	* include/experimental/bits/simd_fixed_size.h
+	(_S_masked_load): Reword comment.
+	(__tuple_element_meta, __make_meta, _SimdTuple::_M_apply_r)
+	(_SimdTuple::_M_subscript_read, _SimdTuple::_M_subscript_write)
+	(__make_simd_tuple, __optimize_simd_tuple, __extract_part)
+	(__autocvt_to_simd, _Fixed::__traits::_SimdBase)
+	(_Fixed::__traits::_SimdCastType, _SimdImplFixedSize): Add
+	constexpr.
+	(_SimdTuple::operator[], _M_set): Add constexpr and add
+	constant_evaluated case.
+	(_MaskImplFixedSize::_S_load): Add constant_evaluated case.
+	* include/experimental/bits/simd_scalar.h: Add constexpr.
+	* include/experimental/bits/simd_x86.h (_CommonImplX86): Add
+	constexpr and add constant_evaluated case.
+	(_SimdImplX86::_S_equal_to, _S_not_equal_to, _S_less)
+	(_S_less_equal): Value-initialize to satisfy constexpr
+	evaluation.
+	(_MaskImplX86::_S_load): Add constant_evaluated case.
+	(_MaskImplX86::_S_store): Add constexpr and constant_evaluated
+	case. Value-initialize local variables.
+	(_MaskImplX86::_S_logical_and, _S_logical_or, _S_bit_not)
+	(_S_bit_and, _S_bit_or, _S_bit_xor): Add constant_evaluated
+	case.
+	* testsuite/experimental/simd/pr109261_constexpr_simd.cc: New
+	test.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-05-22  Matthias Kretz  <m.kretz@gsi.de>
+
+	* include/experimental/bits/simd_builtin.h (_S_fpclassify): Move
+	__infn into #ifdef'ed block.
+	* testsuite/experimental/simd/tests/fpclassify.cc: Declare
+	constants only when used.
+	* testsuite/experimental/simd/tests/frexp.cc: Likewise.
+	* testsuite/experimental/simd/tests/logarithm.cc: Likewise.
+	* testsuite/experimental/simd/tests/trunc_ceil_floor.cc:
+	Likewise.
+	* testsuite/experimental/simd/tests/ldexp_scalbn_scalbln_modf.cc:
+	Move totest and expect1 into #ifdef'ed block.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-03-28  Matthias Kretz  <m.kretz@gsi.de>
+
+	* include/experimental/bits/simd.h (is_simd_flag_type): New.
+	(_IsSimdFlagType): New.
+	(copy_from, copy_to, load ctors): Constrain _Flags using
+	_IsSimdFlagType.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-03-28  Matthias Kretz  <m.kretz@gsi.de>
+
+	* include/experimental/bits/simd_x86.h (_SimdImplX86): Use
+	_Base::_S_divides if the optimized _S_divides function is hidden
+	via the preprocessor.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-03-21  Matthias Kretz  <m.kretz@gsi.de>
+
+	* include/experimental/bits/simd_detail.h: Don't declare the
+	simd API as constexpr with Clang.
+	* include/experimental/bits/simd_x86.h (__movm): New.
+	(_S_blend_avx512): Resolve FIXME. Implement blend using __movm
+	and ?:.
+	(_SimdImplX86::_S_masked_unary): Clang does not implement the
+	same builtins. Implement the function using __movm, ?:, and -
+	operators on vector_size types instead.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-02-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	* include/experimental/bits/simd.h: Line breaks and indenting
+	fixed to follow the libstdc++ standard.
+	* include/experimental/bits/simd_builtin.h: Likewise.
+	* include/experimental/bits/simd_fixed_size.h: Likewise.
+	* include/experimental/bits/simd_neon.h: Likewise.
+	* include/experimental/bits/simd_ppc.h: Likewise.
+	* include/experimental/bits/simd_scalar.h: Likewise.
+	* include/experimental/bits/simd_x86.h: Likewise.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-02-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/108030
+	* include/experimental/bits/simd_fixed_size.h
+	(_SimdImplFixedSize::_S_broadcast): Replace inline with
+	_GLIBCXX_SIMD_INTRINSIC.
+	(_SimdImplFixedSize::_S_generate): Likewise.
+	(_SimdImplFixedSize::_S_load): Likewise.
+	(_SimdImplFixedSize::_S_masked_load): Likewise.
+	(_SimdImplFixedSize::_S_store): Likewise.
+	(_SimdImplFixedSize::_S_masked_store): Likewise.
+	(_SimdImplFixedSize::_S_min): Likewise.
+	(_SimdImplFixedSize::_S_max): Likewise.
+	(_SimdImplFixedSize::_S_complement): Likewise.
+	(_SimdImplFixedSize::_S_unary_minus): Likewise.
+	(_SimdImplFixedSize::_S_plus): Likewise.
+	(_SimdImplFixedSize::_S_minus): Likewise.
+	(_SimdImplFixedSize::_S_multiplies): Likewise.
+	(_SimdImplFixedSize::_S_divides): Likewise.
+	(_SimdImplFixedSize::_S_modulus): Likewise.
+	(_SimdImplFixedSize::_S_bit_and): Likewise.
+	(_SimdImplFixedSize::_S_bit_or): Likewise.
+	(_SimdImplFixedSize::_S_bit_xor): Likewise.
+	(_SimdImplFixedSize::_S_bit_shift_left): Likewise.
+	(_SimdImplFixedSize::_S_bit_shift_right): Likewise.
+	(_SimdImplFixedSize::_S_remquo): Add inline keyword (to be
+	explicit about not always-inline, yet).
+	(_SimdImplFixedSize::_S_isinf): Likewise.
+	(_SimdImplFixedSize::_S_isfinite): Likewise.
+	(_SimdImplFixedSize::_S_isnan): Likewise.
+	(_SimdImplFixedSize::_S_isnormal): Likewise.
+	(_SimdImplFixedSize::_S_signbit): Likewise.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-02-24  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/108856
+	* include/experimental/bits/simd_builtin.h
+	(_SimdImplBuiltin::_S_masked_unary): More efficient
+	implementation of masked inc-/decrement for integers and floats
+	without AVX2.
+	* include/experimental/bits/simd_x86.h
+	(_SimdImplX86::_S_masked_unary): New. Use AVX512 masked subtract
+	builtins for masked inc-/decrement.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-02-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	* testsuite/experimental/simd/tests/reductions.cc: Introduce
+	max_distance as the type-dependent max error.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-02-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/108030
+	* include/experimental/bits/simd_detail.h
+	(_GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA): Define as empty for
+	__clang__.
+
+2023-05-23  Matthias Kretz  <m.kretz@gsi.de>
+
+	Backported from master:
+	2023-02-16  Matthias Kretz  <m.kretz@gsi.de>
+
+	PR libstdc++/108030
+	* include/experimental/bits/simd_detail.h: Define
+	_GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA.
+	* include/experimental/bits/simd.h: Annotate lambdas with
+	_GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA.
+	* include/experimental/bits/simd_builtin.h: Ditto.
+	* include/experimental/bits/simd_converter.h: Ditto.
+	* include/experimental/bits/simd_fixed_size.h: Ditto.
+	* include/experimental/bits/simd_math.h: Ditto.
+	* include/experimental/bits/simd_neon.h: Ditto.
+	* include/experimental/bits/simd_x86.h: Ditto.
+
+2023-05-16  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2022-11-28  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR libstdc++/107801
+	* src/c++17/memory_resource.cc (chunk::_M_bytes): Change type
+	from uint32_t to bitset::size_type. Adjust static assertion.
+	(__pool_resource::_Pool::replenish): Cast to size_t after
+	multiplication instead of before.
+	(__pool_resource::_M_alloc_pools): Ensure both arguments to
+	std::max have type size_t.
+
+2023-05-11  Jonathan Wakely  <jwakely@redhat.com>
+
+	Backported from master:
+	2022-11-16  Jonathan Wakely  <jwakely@redhat.com>
+
+	* python/libstdcxx/v6/printers.py (StdExpAnyPrinter): Make
+	expansion of std::string in manager name more robust.
+
 2023-05-08  Release Manager
 
 	* GCC 12.3.0 released.
--- a/src/libstdc++-v3/include/experimental/bits/simd.h
+++ b/src/libstdc++-v3/include/experimental/bits/simd.h
@@ -180,10 +180,7 @@ struct vector_aligned_tag
   template <typename _Tp, typename _Up>
     _GLIBCXX_SIMD_INTRINSIC static constexpr _Up*
     _S_apply(_Up* __ptr)
-    {
-      return static_cast<_Up*>(
-	__builtin_assume_aligned(__ptr, _S_alignment<_Tp, _Up>));
-    }
+    { return static_cast<_Up*>(__builtin_assume_aligned(__ptr, _S_alignment<_Tp, _Up>)); }
 };
 
 template <size_t _Np> struct overaligned_tag
@@ -288,13 +285,15 @@ namespace __detail
   // expression. math_errhandling may expand to an extern symbol, in which case a constexpr value
   // must be guessed.
   template <int = math_errhandling>
-    constexpr bool __handle_fpexcept_impl(int)
+    constexpr bool
+    __handle_fpexcept_impl(int)
     { return math_errhandling & MATH_ERREXCEPT; }
 #endif
 
   // Fallback if math_errhandling doesn't work: with fast-math assume floating-point exceptions are
   // ignored, otherwise implement correct exception behavior.
-  constexpr bool __handle_fpexcept_impl(float)
+  constexpr bool
+  __handle_fpexcept_impl(float)
   {
 #if defined __FAST_MATH__
     return false;
@@ -609,28 +608,34 @@ template <size_t _Bytes>
 	  operator&(_Ip __rhs) const
 	  {
 	    return __generate_from_n_evaluations<_Np, _Ip>(
-	      [&](auto __i) { return __rhs._M_data[__i] & _M_data[__i]; });
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		return __rhs._M_data[__i] & _M_data[__i];
+	      });
 	  }
 
 	  _GLIBCXX_SIMD_INTRINSIC constexpr _Ip
 	  operator|(_Ip __rhs) const
 	  {
 	    return __generate_from_n_evaluations<_Np, _Ip>(
-	      [&](auto __i) { return __rhs._M_data[__i] | _M_data[__i]; });
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		return __rhs._M_data[__i] | _M_data[__i];
+	      });
 	  }
 
 	  _GLIBCXX_SIMD_INTRINSIC constexpr _Ip
 	  operator^(_Ip __rhs) const
 	  {
 	    return __generate_from_n_evaluations<_Np, _Ip>(
-	      [&](auto __i) { return __rhs._M_data[__i] ^ _M_data[__i]; });
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		return __rhs._M_data[__i] ^ _M_data[__i];
+	      });
 	  }
 
 	  _GLIBCXX_SIMD_INTRINSIC constexpr _Ip
 	  operator~() const
 	  {
 	    return __generate_from_n_evaluations<_Np, _Ip>(
-	      [&](auto __i) { return ~_M_data[__i]; });
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return ~_M_data[__i]; });
 	  }
 	};
 	return _Ip{};
@@ -743,8 +748,7 @@ template <typename _Tp, typename _Up>
 // __invoke_ub{{{
 template <typename... _Args>
   [[noreturn]] _GLIBCXX_SIMD_ALWAYS_INLINE void
-  __invoke_ub([[maybe_unused]] const char* __msg,
-	      [[maybe_unused]] const _Args&... __args)
+  __invoke_ub([[maybe_unused]] const char* __msg, [[maybe_unused]] const _Args&... __args)
   {
 #ifdef _GLIBCXX_DEBUG_UB
     __builtin_fprintf(stderr, __msg, __args...);
@@ -789,11 +793,14 @@ class _ExactBool
   const bool _M_data;
 
 public:
-  _GLIBCXX_SIMD_INTRINSIC constexpr _ExactBool(bool __b) : _M_data(__b) {}
+  _GLIBCXX_SIMD_INTRINSIC constexpr
+  _ExactBool(bool __b) : _M_data(__b) {}
 
   _ExactBool(int) = delete;
 
-  _GLIBCXX_SIMD_INTRINSIC constexpr operator bool() const { return _M_data; }
+  _GLIBCXX_SIMD_INTRINSIC constexpr
+  operator bool() const
+  { return _M_data; }
 };
 
 // }}}
@@ -1391,7 +1398,7 @@ template <size_t _Np, bool _Sanitized>
     operator^=(const _BitMask& __b) & noexcept
     {
       __execute_n_times<_S_array_size>(
-	[&](auto __i) { _M_bits[__i] ^= __b._M_bits[__i]; });
+	[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { _M_bits[__i] ^= __b._M_bits[__i]; });
       return *this;
     }
 
@@ -1399,7 +1406,7 @@ template <size_t _Np, bool _Sanitized>
     operator|=(const _BitMask& __b) & noexcept
     {
       __execute_n_times<_S_array_size>(
-	[&](auto __i) { _M_bits[__i] |= __b._M_bits[__i]; });
+	[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { _M_bits[__i] |= __b._M_bits[__i]; });
       return *this;
     }
 
@@ -1407,7 +1414,7 @@ template <size_t _Np, bool _Sanitized>
     operator&=(const _BitMask& __b) & noexcept
     {
       __execute_n_times<_S_array_size>(
-	[&](auto __i) { _M_bits[__i] &= __b._M_bits[__i]; });
+	[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { _M_bits[__i] &= __b._M_bits[__i]; });
       return *this;
     }
 
@@ -1482,8 +1489,7 @@ template <typename _Tp>
 
 // else, use GNU-style builtin vector types
 template <typename _Tp, size_t _Np>
-  struct __vector_type_n<_Tp, _Np,
-			 enable_if_t<__is_vectorizable_v<_Tp> && _Np >= 2>>
+  struct __vector_type_n<_Tp, _Np, enable_if_t<__is_vectorizable_v<_Tp> && _Np >= 2>>
   {
     static constexpr size_t _S_Np2 = std::__bit_ceil(_Np * sizeof(_Tp));
 
@@ -1764,8 +1770,7 @@ template <typename _To, typename _From>
 // }}}
 // __to_intrin {{{
 template <typename _Tp, typename _TVT = _VectorTraits<_Tp>,
-	  typename _R
-	  = __intrinsic_type_t<typename _TVT::value_type, _TVT::_S_full_size>>
+	  typename _R = __intrinsic_type_t<typename _TVT::value_type, _TVT::_S_full_size>>
   _GLIBCXX_SIMD_INTRINSIC constexpr _R
   __to_intrin(_Tp __x)
   {
@@ -1786,9 +1791,7 @@ template <typename _Tp, typename _TVT = _VectorTraits<_Tp>,
 template <typename _Tp, typename... _Args>
   _GLIBCXX_SIMD_INTRINSIC constexpr __vector_type_t<_Tp, sizeof...(_Args)>
   __make_vector(const _Args&... __args)
-  {
-    return __vector_type_t<_Tp, sizeof...(_Args)>{static_cast<_Tp>(__args)...};
-  }
+  { return __vector_type_t<_Tp, sizeof...(_Args)>{static_cast<_Tp>(__args)...}; }
 
 // }}}
 // __vector_broadcast{{{
@@ -1807,10 +1810,7 @@ template <size_t _Np, typename _Tp>
   template <typename _Tp, size_t _Np, typename _Gp, size_t... _I>
   _GLIBCXX_SIMD_INTRINSIC constexpr __vector_type_t<_Tp, _Np>
   __generate_vector_impl(_Gp&& __gen, index_sequence<_I...>)
-  {
-    return __vector_type_t<_Tp, _Np>{
-      static_cast<_Tp>(__gen(_SizeConstant<_I>()))...};
-  }
+  { return __vector_type_t<_Tp, _Np>{ static_cast<_Tp>(__gen(_SizeConstant<_I>()))...}; }
 
 template <typename _V, typename _VVT = _VectorTraits<_V>, typename _Gp>
   _GLIBCXX_SIMD_INTRINSIC constexpr _V
@@ -2023,8 +2023,7 @@ template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
 // }}}
 // __concat{{{
 template <typename _Tp, typename _TVT = _VectorTraits<_Tp>,
-	  typename _R = __vector_type_t<typename _TVT::value_type,
-					_TVT::_S_full_size * 2>>
+	  typename _R = __vector_type_t<typename _TVT::value_type, _TVT::_S_full_size * 2>>
   constexpr _R
   __concat(_Tp a_, _Tp b_)
   {
@@ -2168,8 +2167,7 @@ template <int _Offset,
 	  int _SplitBy,
 	  typename _Tp,
 	  typename _TVT = _VectorTraits<_Tp>,
-	  typename _R = __vector_type_t<typename _TVT::value_type,
-			  _TVT::_S_full_size / _SplitBy>>
+	  typename _R = __vector_type_t<typename _TVT::value_type, _TVT::_S_full_size / _SplitBy>>
   _GLIBCXX_SIMD_INTRINSIC constexpr _R
   __extract(_Tp __in)
   {
@@ -2206,7 +2204,7 @@ template <int _Offset,
 #endif
 	constexpr int _O = _Offset * __return_width;
 	return __call_with_subscripts<__return_width, _O>(
-	  __x, [](auto... __entries) {
+	  __x, [](auto... __entries) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    return reinterpret_cast<_R>(_Up{__entries...});
 	  });
       }
@@ -2215,8 +2213,7 @@ template <int _Offset,
 // }}}
 // __lo/__hi64[z]{{{
 template <typename _Tp,
-	  typename _R
-	  = __vector_type8_t<typename _VectorTraits<_Tp>::value_type>>
+	  typename _R = __vector_type8_t<typename _VectorTraits<_Tp>::value_type>>
   _GLIBCXX_SIMD_INTRINSIC constexpr _R
   __lo64(_Tp __x)
   {
@@ -2226,8 +2223,7 @@ template <typename _Tp,
   }
 
 template <typename _Tp,
-	  typename _R
-	  = __vector_type8_t<typename _VectorTraits<_Tp>::value_type>>
+	  typename _R = __vector_type8_t<typename _VectorTraits<_Tp>::value_type>>
   _GLIBCXX_SIMD_INTRINSIC constexpr _R
   __hi64(_Tp __x)
   {
@@ -2238,8 +2234,7 @@ template <typename _Tp,
   }
 
 template <typename _Tp,
-	  typename _R
-	  = __vector_type8_t<typename _VectorTraits<_Tp>::value_type>>
+	  typename _R = __vector_type8_t<typename _VectorTraits<_Tp>::value_type>>
   _GLIBCXX_SIMD_INTRINSIC constexpr _R
   __hi64z([[maybe_unused]] _Tp __x)
   {
@@ -2350,18 +2345,15 @@ template <>
 // the following excludes bool via __is_vectorizable
 #if _GLIBCXX_SIMD_HAVE_SSE
 template <typename _Tp, size_t _Bytes>
-  struct __intrinsic_type<_Tp, _Bytes,
-			  enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 64>>
+  struct __intrinsic_type<_Tp, _Bytes, enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 64>>
   {
     static_assert(!is_same_v<_Tp, long double>,
 		  "no __intrinsic_type support for long double on x86");
 
-    static constexpr size_t _S_VBytes = _Bytes <= 16   ? 16
-					: _Bytes <= 32 ? 32
-						       : 64;
+    static constexpr size_t _S_VBytes = _Bytes <= 16 ? 16 : _Bytes <= 32 ? 32 : 64;
 
     using type [[__gnu__::__vector_size__(_S_VBytes)]]
-    = conditional_t<is_integral_v<_Tp>, long long int, _Tp>;
+      = conditional_t<is_integral_v<_Tp>, long long int, _Tp>;
   };
 #endif // _GLIBCXX_SIMD_HAVE_SSE
 
@@ -2377,15 +2369,21 @@ template <>
   struct __intrinsic_type<float, 16, void>
   { using type = float32x4_t; };
 
-#if _GLIBCXX_SIMD_HAVE_NEON_A64
 template <>
   struct __intrinsic_type<double, 8, void>
-  { using type = float64x1_t; };
+  {
+#if _GLIBCXX_SIMD_HAVE_NEON_A64
+   using type = float64x1_t;
+#endif
+  };
 
 template <>
   struct __intrinsic_type<double, 16, void>
-  { using type = float64x2_t; };
+  {
+#if _GLIBCXX_SIMD_HAVE_NEON_A64
+    using type = float64x2_t;
 #endif
+  };
 
 #define _GLIBCXX_SIMD_ARM_INTRIN(_Bits, _Np)                                   \
 template <>                                                                    \
@@ -2407,16 +2405,19 @@ _GLIBCXX_SIMD_ARM_INTRIN(64, 2);
 #undef _GLIBCXX_SIMD_ARM_INTRIN
 
 template <typename _Tp, size_t _Bytes>
-  struct __intrinsic_type<_Tp, _Bytes,
-			  enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 16>>
+  struct __intrinsic_type<_Tp, _Bytes, enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 16>>
   {
     static constexpr int _SVecBytes = _Bytes <= 8 ? 8 : 16;
+
     using _Ip = __int_for_sizeof_t<_Tp>;
+
     using _Up = conditional_t<
       is_floating_point_v<_Tp>, _Tp,
       conditional_t<is_unsigned_v<_Tp>, make_unsigned_t<_Ip>, _Ip>>;
+
     static_assert(!is_same_v<_Tp, _Up> || _SVecBytes != _Bytes,
 		  "should use explicit specialization above");
+
     using type = typename __intrinsic_type<_Up, _SVecBytes>::type;
   };
 #endif // _GLIBCXX_SIMD_HAVE_NEON
@@ -2451,23 +2452,54 @@ _GLIBCXX_SIMD_PPC_INTRIN(unsigned long long);
 #undef _GLIBCXX_SIMD_PPC_INTRIN
 
 template <typename _Tp, size_t _Bytes>
-  struct __intrinsic_type<_Tp, _Bytes,
-			  enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 16>>
+  struct __intrinsic_type<_Tp, _Bytes, enable_if_t<__is_vectorizable_v<_Tp> && _Bytes <= 16>>
   {
     static constexpr bool _S_is_ldouble = is_same_v<_Tp, long double>;
+
     // allow _Tp == long double with -mlong-double-64
     static_assert(!(_S_is_ldouble && sizeof(long double) > sizeof(double)),
 		  "no __intrinsic_type support for 128-bit floating point on PowerPC");
+
 #ifndef __VSX__
     static_assert(!(is_same_v<_Tp, double>
 		    || (_S_is_ldouble && sizeof(long double) == sizeof(double))),
 		  "no __intrinsic_type support for 64-bit floating point on PowerPC w/o VSX");
 #endif
-    using type =
-      typename __intrinsic_type_impl<
-		 conditional_t<is_floating_point_v<_Tp>,
-			       conditional_t<_S_is_ldouble, double, _Tp>,
-			       __int_for_sizeof_t<_Tp>>>::type;
+
+    static constexpr auto __element_type()
+    {
+      if constexpr (is_floating_point_v<_Tp>)
+	{
+	  if constexpr (_S_is_ldouble)
+	    return double {};
+	  else
+	    return _Tp {};
+	}
+      else if constexpr (is_signed_v<_Tp>)
+	{
+	  if constexpr (sizeof(_Tp) == sizeof(_SChar))
+	    return _SChar {};
+	  else if constexpr (sizeof(_Tp) == sizeof(short))
+	    return short {};
+	  else if constexpr (sizeof(_Tp) == sizeof(int))
+	    return int {};
+	  else if constexpr (sizeof(_Tp) == sizeof(_LLong))
+	    return _LLong {};
+	}
+      else
+	{
+	  if constexpr (sizeof(_Tp) == sizeof(_UChar))
+	    return _UChar {};
+	  else if constexpr (sizeof(_Tp) == sizeof(_UShort))
+	    return _UShort {};
+	  else if constexpr (sizeof(_Tp) == sizeof(_UInt))
+	    return _UInt {};
+	  else if constexpr (sizeof(_Tp) == sizeof(_ULLong))
+	    return _ULLong {};
+	}
+    }
+
+    using type = typename __intrinsic_type_impl<decltype(__element_type())>::type;
   };
 #endif // __ALTIVEC__
 
@@ -2483,22 +2515,29 @@ template <size_t _Width>
     static constexpr size_t _S_full_size = sizeof(_BuiltinType) * __CHAR_BIT__;
 
     _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper<bool, _S_full_size>
-    __as_full_vector() const { return _M_data; }
+    __as_full_vector() const
+    { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper() = default;
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(_BuiltinType __k)
-      : _M_data(__k) {};
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapper() = default;
+
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapper(_BuiltinType __k) : _M_data(__k) {};
 
-    _GLIBCXX_SIMD_INTRINSIC operator const _BuiltinType&() const
+    _GLIBCXX_SIMD_INTRINSIC
+    operator const _BuiltinType&() const
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC operator _BuiltinType&()
+    _GLIBCXX_SIMD_INTRINSIC
+    operator _BuiltinType&()
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC _BuiltinType __intrin() const
+    _GLIBCXX_SIMD_INTRINSIC _BuiltinType
+    __intrin() const
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr value_type operator[](size_t __i) const
+    _GLIBCXX_SIMD_INTRINSIC constexpr value_type
+    operator[](size_t __i) const
     { return _M_data & (_BuiltinType(1) << __i); }
 
     template <size_t __i>
@@ -2506,7 +2545,8 @@ template <size_t _Width>
       operator[](_SizeConstant<__i>) const
       { return _M_data & (_BuiltinType(1) << __i); }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr void _M_set(size_t __i, value_type __x)
+    _GLIBCXX_SIMD_INTRINSIC constexpr void
+    _M_set(size_t __i, value_type __x)
     {
       if (__x)
 	_M_data |= (_BuiltinType(1) << __i);
@@ -2514,11 +2554,12 @@ template <size_t _Width>
 	_M_data &= ~(_BuiltinType(1) << __i);
     }
 
-    _GLIBCXX_SIMD_INTRINSIC
-    constexpr bool _M_is_constprop() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr bool
+    _M_is_constprop() const
     { return __builtin_constant_p(_M_data); }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr bool _M_is_constprop_none_of() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr bool
+    _M_is_constprop_none_of() const
     {
       if (__builtin_constant_p(_M_data))
 	{
@@ -2530,7 +2571,8 @@ template <size_t _Width>
       return false;
     }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr bool _M_is_constprop_all_of() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr bool
+    _M_is_constprop_all_of() const
     {
       if (__builtin_constant_p(_M_data))
 	{
@@ -2552,10 +2594,11 @@ template <bool _MustZeroInitPadding, typename _BuiltinType>
 template <typename _BuiltinType>
   struct _SimdWrapperBase<false, _BuiltinType> // no padding or no SNaNs
   {
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapperBase() = default;
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapperBase(_BuiltinType __init)
-      : _M_data(__init)
-    {}
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapperBase() = default;
+
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapperBase(_BuiltinType __init) : _M_data(__init) {}
 
     _BuiltinType _M_data;
   };
@@ -2564,10 +2607,11 @@ template <typename _BuiltinType>
   struct _SimdWrapperBase<true, _BuiltinType> // with padding that needs to
 					      // never become SNaN
   {
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapperBase() : _M_data() {}
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapperBase(_BuiltinType __init)
-      : _M_data(__init)
-    {}
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapperBase() : _M_data() {}
+
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapperBase(_BuiltinType __init) : _M_data(__init) {}
 
     _BuiltinType _M_data;
   };
@@ -2606,24 +2650,33 @@ template <typename _Tp, size_t _Width>
     __as_full_vector() const
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(initializer_list<_Tp> __init)
-      : _Base(__generate_from_n_evaluations<_Width, _BuiltinType>(
-	[&](auto __i) { return __init.begin()[__i.value]; })) {}
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapper(initializer_list<_Tp> __init)
+    : _Base(__generate_from_n_evaluations<_Width, _BuiltinType>(
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		return __init.begin()[__i.value];
+	      })) {}
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper() = default;
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(const _SimdWrapper&)
-      = default;
-    _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(_SimdWrapper&&) = default;
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapper() = default;
+
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapper(const _SimdWrapper&) = default;
+
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    _SimdWrapper(_SimdWrapper&&) = default;
 
     _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper&
     operator=(const _SimdWrapper&) = default;
+
     _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper&
     operator=(_SimdWrapper&&) = default;
 
     template <typename _V, typename = enable_if_t<disjunction_v<
 			     is_same<_V, __vector_type_t<_Tp, _Width>>,
 			     is_same<_V, __intrinsic_type_t<_Tp, _Width>>>>>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper(_V __x)
+      _GLIBCXX_SIMD_INTRINSIC constexpr
+      _SimdWrapper(_V __x)
       // __vector_bitcast can convert e.g. __m128 to __vector(2) float
       : _Base(__vector_bitcast<_Tp, _Width>(__x)) {}
 
@@ -2633,33 +2686,46 @@ template <typename _Tp, size_t _Width>
       _GLIBCXX_SIMD_INTRINSIC constexpr
       operator _SimdTuple<_Tp, _As...>() const
       {
-	const auto& dd = _M_data; // workaround for GCC7 ICE
-	return __generate_from_n_evaluations<sizeof...(_As),
-					     _SimdTuple<_Tp, _As...>>([&](
-	  auto __i) constexpr { return dd[int(__i)]; });
+	return __generate_from_n_evaluations<sizeof...(_As), _SimdTuple<_Tp, _As...>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+		 { return _M_data[int(__i)]; });
       }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr operator const _BuiltinType&() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    operator const _BuiltinType&() const
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr operator _BuiltinType&()
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    operator _BuiltinType&()
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr _Tp operator[](size_t __i) const
+    _GLIBCXX_SIMD_INTRINSIC constexpr _Tp
+    operator[](size_t __i) const
     { return _M_data[__i]; }
 
     template <size_t __i>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _Tp operator[](_SizeConstant<__i>) const
+      _GLIBCXX_SIMD_INTRINSIC constexpr _Tp
+      operator[](_SizeConstant<__i>) const
       { return _M_data[__i]; }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr void _M_set(size_t __i, _Tp __x)
-    { _M_data[__i] = __x; }
+    _GLIBCXX_SIMD_INTRINSIC constexpr void
+    _M_set(size_t __i, _Tp __x)
+    {
+      if (__builtin_is_constant_evaluated())
+	_M_data = __generate_from_n_evaluations<_Width, _BuiltinType>([&](auto __j) {
+		    return __j == __i ? __x : _M_data[__j()];
+		  });
+      else
+	_M_data[__i] = __x;
+    }
 
     _GLIBCXX_SIMD_INTRINSIC
-    constexpr bool _M_is_constprop() const
+    constexpr bool
+    _M_is_constprop() const
     { return __builtin_constant_p(_M_data); }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr bool _M_is_constprop_none_of() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr bool
+    _M_is_constprop_none_of() const
     {
       if (__builtin_constant_p(_M_data))
 	{
@@ -2680,7 +2746,8 @@ template <typename _Tp, size_t _Width>
       return false;
     }
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr bool _M_is_constprop_all_of() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr bool
+    _M_is_constprop_all_of() const
     {
       if (__builtin_constant_p(_M_data))
 	{
@@ -2812,6 +2879,32 @@ template <typename _Tp>
 } // namespace simd_abi
 
 // traits {{{1
+template <typename _Tp>
+  struct is_simd_flag_type
+  : false_type
+  {};
+
+template <>
+  struct is_simd_flag_type<element_aligned_tag>
+  : true_type
+  {};
+
+template <>
+  struct is_simd_flag_type<vector_aligned_tag>
+  : true_type
+  {};
+
+template <size_t _Np>
+  struct is_simd_flag_type<overaligned_tag<_Np>>
+  : __bool_constant<(_Np > 0) and __has_single_bit(_Np)>
+  {};
+
+template <typename _Tp>
+  inline constexpr bool is_simd_flag_type_v = is_simd_flag_type<_Tp>::value;
+
+template <typename _Tp, typename = enable_if_t<is_simd_flag_type_v<_Tp>>>
+  using _IsSimdFlagType = _Tp;
+
 // is_abi_tag {{{2
 template <typename _Tp, typename = void_t<>>
   struct is_abi_tag : false_type {};
@@ -2878,22 +2971,14 @@ template <typename _Tp, typename _V, typename = void>
   struct rebind_simd;
 
 template <typename _Tp, typename _Up, typename _Abi>
-  struct rebind_simd<
-    _Tp, simd<_Up, _Abi>,
-    void_t<simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>>
-  {
-    using type
-      = simd<_Tp, simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>;
-  };
+  struct rebind_simd<_Tp, simd<_Up, _Abi>,
+		     void_t<simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>>
+  { using type = simd<_Tp, simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>; };
 
 template <typename _Tp, typename _Up, typename _Abi>
-  struct rebind_simd<
-    _Tp, simd_mask<_Up, _Abi>,
-    void_t<simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>>
-  {
-    using type
-      = simd_mask<_Tp, simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>;
-  };
+  struct rebind_simd<_Tp, simd_mask<_Up, _Abi>,
+		     void_t<simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>>
+  { using type = simd_mask<_Tp, simd_abi::deduce_t<_Tp, simd_size_v<_Up, _Abi>, _Abi>>; };
 
 template <typename _Tp, typename _V>
   using rebind_simd_t = typename rebind_simd<_Tp, _V>::type;
@@ -2903,13 +2988,11 @@ template <int _Np, typename _V, typename = void>
   struct resize_simd;
 
 template <int _Np, typename _Tp, typename _Abi>
-  struct resize_simd<_Np, simd<_Tp, _Abi>,
-		     void_t<simd_abi::deduce_t<_Tp, _Np, _Abi>>>
+  struct resize_simd<_Np, simd<_Tp, _Abi>, void_t<simd_abi::deduce_t<_Tp, _Np, _Abi>>>
   { using type = simd<_Tp, simd_abi::deduce_t<_Tp, _Np, _Abi>>; };
 
 template <int _Np, typename _Tp, typename _Abi>
-  struct resize_simd<_Np, simd_mask<_Tp, _Abi>,
-		     void_t<simd_abi::deduce_t<_Tp, _Np, _Abi>>>
+  struct resize_simd<_Np, simd_mask<_Tp, _Abi>, void_t<simd_abi::deduce_t<_Tp, _Np, _Abi>>>
   { using type = simd_mask<_Tp, simd_abi::deduce_t<_Tp, _Np, _Abi>>; };
 
 template <int _Np, typename _V>
@@ -2958,13 +3041,11 @@ template <typename _Tp, size_t _Np>
 
 // casts [simd.casts] {{{1
 // static_simd_cast {{{2
-template <typename _Tp, typename _Up, typename _Ap, bool = is_simd_v<_Tp>,
-	  typename = void>
+template <typename _Tp, typename _Up, typename _Ap, bool = is_simd_v<_Tp>, typename = void>
   struct __static_simd_cast_return_type;
 
 template <typename _Tp, typename _A0, typename _Up, typename _Ap>
-  struct __static_simd_cast_return_type<simd_mask<_Tp, _A0>, _Up, _Ap, false,
-					void>
+  struct __static_simd_cast_return_type<simd_mask<_Tp, _A0>, _Up, _Ap, false, void>
   : __static_simd_cast_return_type<simd<_Tp, _A0>, _Up, _Ap> {};
 
 template <typename _Tp, typename _Up, typename _Ap>
@@ -3147,6 +3228,10 @@ template <typename _Tp, typename _Up, typename _Ap>
   {
     if constexpr (is_same_v<typename _Tp::abi_type, _Ap>)
       return __x;
+    else if (__builtin_is_constant_evaluated())
+      return _Tp([&](auto __i) constexpr {
+	       return __i < simd_size_v<_Up, _Ap> ? __x[__i] : _Up();
+	     });
     else if constexpr (simd_size_v<_Up, _Ap> == 1)
       {
 	_Tp __r{};
@@ -3193,21 +3278,19 @@ template <typename _Tp, int _Np>
   { return __x; }
 
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC auto
+  _GLIBCXX_SIMD_INTRINSIC fixed_size_simd<_Tp, simd_size_v<_Tp, _Ap>>
   to_fixed_size(const simd<_Tp, _Ap>& __x)
   {
-    return simd<_Tp, simd_abi::fixed_size<simd_size_v<_Tp, _Ap>>>([&__x](
-      auto __i) constexpr { return __x[__i]; });
+    using _Rp = fixed_size_simd<_Tp, simd_size_v<_Tp, _Ap>>;
+    return _Rp([&__x](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; });
   }
 
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC auto
+  _GLIBCXX_SIMD_INTRINSIC fixed_size_simd_mask<_Tp, simd_size_v<_Tp, _Ap>>
   to_fixed_size(const simd_mask<_Tp, _Ap>& __x)
   {
-    constexpr int _Np = simd_mask<_Tp, _Ap>::size();
-    fixed_size_simd_mask<_Tp, _Np> __r;
-    __execute_n_times<_Np>([&](auto __i) constexpr { __r[__i] = __x[__i]; });
-    return __r;
+    return {__private_init,
+	    [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; }};
   }
 
 // to_native {{{2
@@ -3221,16 +3304,18 @@ template <typename _Tp, int _Np>
     return {__mem, vector_aligned};
   }
 
-template <typename _Tp, size_t _Np>
+template <typename _Tp, int _Np>
   _GLIBCXX_SIMD_INTRINSIC
   enable_if_t<(_Np == native_simd_mask<_Tp>::size()), native_simd_mask<_Tp>>
   to_native(const fixed_size_simd_mask<_Tp, _Np>& __x)
   {
-    return native_simd_mask<_Tp>([&](auto __i) constexpr { return __x[__i]; });
+    return native_simd_mask<_Tp>(
+	     __private_init,
+	     [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; });
   }
 
 // to_compatible {{{2
-template <typename _Tp, size_t _Np>
+template <typename _Tp, int _Np>
   _GLIBCXX_SIMD_INTRINSIC enable_if_t<(_Np == simd<_Tp>::size()), simd<_Tp>>
   to_compatible(const simd<_Tp, simd_abi::fixed_size<_Np>>& __x)
   {
@@ -3239,11 +3324,15 @@ template <typename _Tp, size_t _Np>
     return {__mem, vector_aligned};
   }
 
-template <typename _Tp, size_t _Np>
+template <typename _Tp, int _Np>
   _GLIBCXX_SIMD_INTRINSIC
   enable_if_t<(_Np == simd_mask<_Tp>::size()), simd_mask<_Tp>>
   to_compatible(const simd_mask<_Tp, simd_abi::fixed_size<_Np>>& __x)
-  { return simd_mask<_Tp>([&](auto __i) constexpr { return __x[__i]; }); }
+  {
+    return simd_mask<_Tp>(
+	     __private_init,
+	     [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; });
+  }
 
 // masked assignment [simd_mask.where] {{{1
 
@@ -3276,12 +3365,14 @@ template <typename _M, typename _Tp>
 
   public:
     const_where_expression(const const_where_expression&) = delete;
+
     const_where_expression& operator=(const const_where_expression&) = delete;
 
-    _GLIBCXX_SIMD_INTRINSIC const_where_expression(const _M& __kk, const _Tp& dd)
-      : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {}
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    const_where_expression(const _M& __kk, const _Tp& dd)
+    : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {}
 
-    _GLIBCXX_SIMD_INTRINSIC _V
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V
     operator-() const&&
     {
       return {__private_init,
@@ -3290,8 +3381,8 @@ template <typename _M, typename _Tp>
     }
 
     template <typename _Up, typename _Flags>
-      [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _V
-      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _Flags) const&&
+      [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V
+      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&&
       {
 	return {__private_init,
 		_Impl::_S_masked_load(__data(_M_value), __data(_M_k),
@@ -3299,8 +3390,8 @@ template <typename _M, typename _Tp>
       }
 
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_INTRINSIC void
-      copy_to(_LoadStorePtr<_Up, value_type>* __mem, _Flags) const&&
+      _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+      copy_to(_LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&&
       {
 	_Impl::_S_masked_store(__data(_M_value),
 			       _Flags::template _S_apply<_V>(__mem),
@@ -3320,8 +3411,8 @@ template <typename _Tp>
     struct _Wrapper { using value_type = _V; };
 
   protected:
-    using value_type =
-      typename conditional_t<is_arithmetic_v<_V>, _Wrapper, _V>::value_type;
+    using value_type
+      = typename conditional_t<is_arithmetic_v<_V>, _Wrapper, _V>::value_type;
 
     _GLIBCXX_SIMD_INTRINSIC friend const _M&
     __get_mask(const const_where_expression& __x)
@@ -3338,20 +3429,22 @@ template <typename _Tp>
     const_where_expression(const const_where_expression&) = delete;
     const_where_expression& operator=(const const_where_expression&) = delete;
 
-    _GLIBCXX_SIMD_INTRINSIC const_where_expression(const bool __kk, const _Tp& dd)
-      : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {}
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    const_where_expression(const bool __kk, const _Tp& dd)
+    : _M_k(__kk), _M_value(const_cast<_Tp&>(dd)) {}
 
-    _GLIBCXX_SIMD_INTRINSIC _V operator-() const&&
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V
+    operator-() const&&
     { return _M_k ? -_M_value : _M_value; }
 
     template <typename _Up, typename _Flags>
-      [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _V
-      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _Flags) const&&
+      [[nodiscard]] _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _V
+      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&&
       { return _M_k ? static_cast<_V>(__mem[0]) : _M_value; }
 
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_INTRINSIC void
-      copy_to(_LoadStorePtr<_Up, value_type>* __mem, _Flags) const&&
+      _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+      copy_to(_LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) const&&
       {
 	if (_M_k)
 	  __mem[0] = _M_value;
@@ -3376,18 +3469,21 @@ template <typename _M, typename _Tp>
       is_same<typename _M::abi_type, typename _Tp::abi_type>::value, "");
     static_assert(_M::size() == _Tp::size(), "");
 
-    _GLIBCXX_SIMD_INTRINSIC friend _Tp& __get_lvalue(where_expression& __x)
+    _GLIBCXX_SIMD_INTRINSIC friend constexpr _Tp&
+    __get_lvalue(where_expression& __x)
     { return __x._M_value; }
 
   public:
     where_expression(const where_expression&) = delete;
     where_expression& operator=(const where_expression&) = delete;
 
-    _GLIBCXX_SIMD_INTRINSIC where_expression(const _M& __kk, _Tp& dd)
-      : const_where_expression<_M, _Tp>(__kk, dd) {}
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
+    where_expression(const _M& __kk, _Tp& dd)
+    : const_where_expression<_M, _Tp>(__kk, dd) {}
 
     template <typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC void operator=(_Up&& __x) &&
+      _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+      operator=(_Up&& __x) &&
       {
 	_Impl::_S_masked_assign(__data(_M_k), __data(_M_value),
 				__to_value_type_or_member_type<_Tp>(
@@ -3396,14 +3492,15 @@ template <typename _M, typename _Tp>
 
 #define _GLIBCXX_SIMD_OP_(__op, __name)                                        \
   template <typename _Up>                                                      \
-    _GLIBCXX_SIMD_INTRINSIC void operator __op##=(_Up&& __x)&&                 \
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void                       \
+    operator __op##=(_Up&& __x)&&                                              \
     {                                                                          \
       _Impl::template _S_masked_cassign(                                       \
 	__data(_M_k), __data(_M_value),                                        \
 	__to_value_type_or_member_type<_Tp>(static_cast<_Up&&>(__x)),          \
-	[](auto __impl, auto __lhs, auto __rhs) constexpr {                    \
-	return __impl.__name(__lhs, __rhs);                                    \
-	});                                                                    \
+	[](auto __impl, auto __lhs, auto __rhs)                                \
+	  constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA                         \
+	{ return __impl.__name(__lhs, __rhs); });                              \
     }                                                                          \
   static_assert(true)
     _GLIBCXX_SIMD_OP_(+, _S_plus);
@@ -3418,48 +3515,48 @@ template <typename _M, typename _Tp>
     _GLIBCXX_SIMD_OP_(>>, _S_shift_right);
 #undef _GLIBCXX_SIMD_OP_
 
-    _GLIBCXX_SIMD_INTRINSIC void operator++() &&
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+    operator++() &&
     {
       __data(_M_value)
-	= _Impl::template _S_masked_unary<__increment>(__data(_M_k),
-						       __data(_M_value));
+	= _Impl::template _S_masked_unary<__increment>(__data(_M_k), __data(_M_value));
     }
 
-    _GLIBCXX_SIMD_INTRINSIC void operator++(int) &&
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+    operator++(int) &&
     {
       __data(_M_value)
-	= _Impl::template _S_masked_unary<__increment>(__data(_M_k),
-						       __data(_M_value));
+	= _Impl::template _S_masked_unary<__increment>(__data(_M_k), __data(_M_value));
     }
 
-    _GLIBCXX_SIMD_INTRINSIC void operator--() &&
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+    operator--() &&
     {
       __data(_M_value)
-	= _Impl::template _S_masked_unary<__decrement>(__data(_M_k),
-						       __data(_M_value));
+	= _Impl::template _S_masked_unary<__decrement>(__data(_M_k), __data(_M_value));
     }
 
-    _GLIBCXX_SIMD_INTRINSIC void operator--(int) &&
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+    operator--(int) &&
     {
       __data(_M_value)
-	= _Impl::template _S_masked_unary<__decrement>(__data(_M_k),
-						       __data(_M_value));
+	= _Impl::template _S_masked_unary<__decrement>(__data(_M_k), __data(_M_value));
     }
 
     // intentionally hides const_where_expression::copy_from
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_INTRINSIC void
-      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _Flags) &&
+      _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) &&
       {
-	__data(_M_value)
-	  = _Impl::_S_masked_load(__data(_M_value), __data(_M_k),
-				  _Flags::template _S_apply<_Tp>(__mem));
+	__data(_M_value) = _Impl::_S_masked_load(__data(_M_value), __data(_M_k),
+						 _Flags::template _S_apply<_Tp>(__mem));
       }
   };
 
 // where_expression<bool, T> {{{2
 template <typename _Tp>
-  class where_expression<bool, _Tp> : public const_where_expression<bool, _Tp>
+  class where_expression<bool, _Tp>
+  : public const_where_expression<bool, _Tp>
   {
     using _M = bool;
     using typename const_where_expression<_M, _Tp>::value_type;
@@ -3470,12 +3567,14 @@ template <typename _Tp>
     where_expression(const where_expression&) = delete;
     where_expression& operator=(const where_expression&) = delete;
 
-    _GLIBCXX_SIMD_INTRINSIC where_expression(const _M& __kk, _Tp& dd)
-      : const_where_expression<_M, _Tp>(__kk, dd) {}
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
+    where_expression(const _M& __kk, _Tp& dd)
+    : const_where_expression<_M, _Tp>(__kk, dd) {}
 
 #define _GLIBCXX_SIMD_OP_(__op)                                                \
     template <typename _Up>                                                    \
-      _GLIBCXX_SIMD_INTRINSIC void operator __op(_Up&& __x)&&                  \
+      _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void                     \
+      operator __op(_Up&& __x)&&                                               \
       { if (_M_k) _M_value __op static_cast<_Up&&>(__x); }
 
     _GLIBCXX_SIMD_OP_(=)
@@ -3491,67 +3590,71 @@ template <typename _Tp>
     _GLIBCXX_SIMD_OP_(>>=)
   #undef _GLIBCXX_SIMD_OP_
 
-    _GLIBCXX_SIMD_INTRINSIC void operator++() &&
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+    operator++() &&
     { if (_M_k) ++_M_value; }
 
-    _GLIBCXX_SIMD_INTRINSIC void operator++(int) &&
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+    operator++(int) &&
     { if (_M_k) ++_M_value; }
 
-    _GLIBCXX_SIMD_INTRINSIC void operator--() &&
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+    operator--() &&
     { if (_M_k) --_M_value; }
 
-    _GLIBCXX_SIMD_INTRINSIC void operator--(int) &&
+    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+    operator--(int) &&
     { if (_M_k) --_M_value; }
 
     // intentionally hides const_where_expression::copy_from
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_INTRINSIC void
-      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _Flags) &&
+      _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR void
+      copy_from(const _LoadStorePtr<_Up, value_type>* __mem, _IsSimdFlagType<_Flags>) &&
       { if (_M_k) _M_value = __mem[0]; }
   };
 
 // where {{{1
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC where_expression<simd_mask<_Tp, _Ap>, simd<_Tp, _Ap>>
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
+  where_expression<simd_mask<_Tp, _Ap>, simd<_Tp, _Ap>>
   where(const typename simd<_Tp, _Ap>::mask_type& __k, simd<_Tp, _Ap>& __value)
   { return {__k, __value}; }
 
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC
-    const_where_expression<simd_mask<_Tp, _Ap>, simd<_Tp, _Ap>>
-    where(const typename simd<_Tp, _Ap>::mask_type& __k,
-	  const simd<_Tp, _Ap>& __value)
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
+  const_where_expression<simd_mask<_Tp, _Ap>, simd<_Tp, _Ap>>
+  where(const typename simd<_Tp, _Ap>::mask_type& __k, const simd<_Tp, _Ap>& __value)
   { return {__k, __value}; }
 
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC
-    where_expression<simd_mask<_Tp, _Ap>, simd_mask<_Tp, _Ap>>
-    where(const remove_const_t<simd_mask<_Tp, _Ap>>& __k,
-	  simd_mask<_Tp, _Ap>& __value)
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
+  where_expression<simd_mask<_Tp, _Ap>, simd_mask<_Tp, _Ap>>
+  where(const remove_const_t<simd_mask<_Tp, _Ap>>& __k, simd_mask<_Tp, _Ap>& __value)
   { return {__k, __value}; }
 
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC
-    const_where_expression<simd_mask<_Tp, _Ap>, simd_mask<_Tp, _Ap>>
-    where(const remove_const_t<simd_mask<_Tp, _Ap>>& __k,
-	  const simd_mask<_Tp, _Ap>& __value)
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
+  const_where_expression<simd_mask<_Tp, _Ap>, simd_mask<_Tp, _Ap>>
+  where(const remove_const_t<simd_mask<_Tp, _Ap>>& __k, const simd_mask<_Tp, _Ap>& __value)
   { return {__k, __value}; }
 
 template <typename _Tp>
-  _GLIBCXX_SIMD_INTRINSIC where_expression<bool, _Tp>
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR where_expression<bool, _Tp>
   where(_ExactBool __k, _Tp& __value)
   { return {__k, __value}; }
 
 template <typename _Tp>
-  _GLIBCXX_SIMD_INTRINSIC const_where_expression<bool, _Tp>
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR const_where_expression<bool, _Tp>
   where(_ExactBool __k, const _Tp& __value)
   { return {__k, __value}; }
 
-  template <typename _Tp, typename _Ap>
-    void where(bool __k, simd<_Tp, _Ap>& __value) = delete;
+template <typename _Tp, typename _Ap>
+  _GLIBCXX_SIMD_CONSTEXPR void
+  where(bool __k, simd<_Tp, _Ap>& __value) = delete;
 
-  template <typename _Tp, typename _Ap>
-    void where(bool __k, const simd<_Tp, _Ap>& __value) = delete;
+template <typename _Tp, typename _Ap>
+  _GLIBCXX_SIMD_CONSTEXPR void
+  where(bool __k, const simd<_Tp, _Ap>& __value) = delete;
 
 // proposed mask iterations {{{1
 namespace __proposed {
@@ -3568,10 +3671,12 @@ template <size_t _Np>
       size_t __mask;
       size_t __bit;
 
-      _GLIBCXX_SIMD_INTRINSIC void __next_bit()
+      _GLIBCXX_SIMD_INTRINSIC void
+      __next_bit()
       { __bit = __builtin_ctzl(__mask); }
 
-      _GLIBCXX_SIMD_INTRINSIC void __reset_lsb()
+      _GLIBCXX_SIMD_INTRINSIC void
+      __reset_lsb()
       {
 	// 01100100 - 1 = 01100011
 	__mask &= (__mask - 1);
@@ -3583,20 +3688,24 @@ template <size_t _Np>
       iterator(const iterator&) = default;
       iterator(iterator&&) = default;
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE size_t operator->() const
+      _GLIBCXX_SIMD_ALWAYS_INLINE size_t
+      operator->() const
       { return __bit; }
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE size_t operator*() const
+      _GLIBCXX_SIMD_ALWAYS_INLINE size_t
+      operator*() const
       { return __bit; }
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE iterator& operator++()
+      _GLIBCXX_SIMD_ALWAYS_INLINE iterator&
+      operator++()
       {
 	__reset_lsb();
 	__next_bit();
 	return *this;
       }
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE iterator operator++(int)
+      _GLIBCXX_SIMD_ALWAYS_INLINE iterator
+      operator++(int)
       {
 	iterator __tmp = *this;
 	__reset_lsb();
@@ -3604,17 +3713,21 @@ template <size_t _Np>
 	return __tmp;
       }
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE bool operator==(const iterator& __rhs) const
+      _GLIBCXX_SIMD_ALWAYS_INLINE bool
+      operator==(const iterator& __rhs) const
       { return __mask == __rhs.__mask; }
 
-      _GLIBCXX_SIMD_ALWAYS_INLINE bool operator!=(const iterator& __rhs) const
+      _GLIBCXX_SIMD_ALWAYS_INLINE bool
+      operator!=(const iterator& __rhs) const
       { return __mask != __rhs.__mask; }
     };
 
-    iterator begin() const
+    iterator
+    begin() const
     { return __bits.to_ullong(); }
 
-    iterator end() const
+    iterator
+    end() const
     { return 0; }
   };
 
@@ -3629,15 +3742,13 @@ template <typename _Tp, typename _Ap>
 // reductions [simd.reductions] {{{1
 template <typename _Tp, typename _Abi, typename _BinaryOperation = plus<>>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _Tp
-  reduce(const simd<_Tp, _Abi>& __v,
-	 _BinaryOperation __binary_op = _BinaryOperation())
+  reduce(const simd<_Tp, _Abi>& __v, _BinaryOperation __binary_op = _BinaryOperation())
   { return _Abi::_SimdImpl::_S_reduce(__v, __binary_op); }
 
 template <typename _M, typename _V, typename _BinaryOperation = plus<>>
   _GLIBCXX_SIMD_INTRINSIC typename _V::value_type
   reduce(const const_where_expression<_M, _V>& __x,
-	 typename _V::value_type __identity_element,
-	 _BinaryOperation __binary_op)
+	 typename _V::value_type __identity_element, _BinaryOperation __binary_op)
   {
     if (__builtin_expect(none_of(__get_mask(__x)), false))
       return __identity_element;
@@ -3676,16 +3787,12 @@ template <typename _M, typename _V>
 template <typename _Tp, typename _Abi>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _Tp
   hmin(const simd<_Tp, _Abi>& __v) noexcept
-  {
-    return _Abi::_SimdImpl::_S_reduce(__v, __detail::_Minimum());
-  }
+  { return _Abi::_SimdImpl::_S_reduce(__v, __detail::_Minimum()); }
 
 template <typename _Tp, typename _Abi>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR _Tp
   hmax(const simd<_Tp, _Abi>& __v) noexcept
-  {
-    return _Abi::_SimdImpl::_S_reduce(__v, __detail::_Maximum());
-  }
+  { return _Abi::_SimdImpl::_S_reduce(__v, __detail::_Maximum()); }
 
 template <typename _M, typename _V>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
@@ -3753,8 +3860,7 @@ template <typename _Tp, typename _Ap>
 
 template <typename _Tp, typename _Ap>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR simd<_Tp, _Ap>
-  clamp(const simd<_Tp, _Ap>& __v, const simd<_Tp, _Ap>& __lo,
-	const simd<_Tp, _Ap>& __hi)
+  clamp(const simd<_Tp, _Ap>& __v, const simd<_Tp, _Ap>& __lo, const simd<_Tp, _Ap>& __hi)
   {
     using _Impl = typename _Ap::_SimdImpl;
     return {__private_init,
@@ -3771,13 +3877,12 @@ template <size_t... _Sizes, typename _Tp, typename _Ap,
 
 // __extract_part {{{
 template <int _Index, int _Total, int _Combine = 1, typename _Tp, size_t _Np>
-  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST constexpr
   _SimdWrapper<_Tp, _Np / _Total * _Combine>
   __extract_part(const _SimdWrapper<_Tp, _Np> __x);
 
-template <int _Index, int _Parts, int _Combine = 1, typename _Tp, typename _A0,
-	  typename... _As>
-  _GLIBCXX_SIMD_INTRINSIC auto
+template <int _Index, int _Parts, int _Combine = 1, typename _Tp, typename _A0, typename... _As>
+  _GLIBCXX_SIMD_INTRINSIC constexpr auto
   __extract_part(const _SimdTuple<_Tp, _A0, _As...>& __x);
 
 // }}}
@@ -3786,7 +3891,8 @@ template <size_t _V0, size_t... _Values>
   struct _SizeList
   {
     template <size_t _I>
-      static constexpr size_t _S_at(_SizeConstant<_I> = {})
+      static constexpr size_t
+      _S_at(_SizeConstant<_I> = {})
       {
 	if constexpr (_I == 0)
 	  return _V0;
@@ -3795,7 +3901,8 @@ template <size_t _V0, size_t... _Values>
       }
 
     template <size_t _I>
-      static constexpr auto _S_before(_SizeConstant<_I> = {})
+      static constexpr auto
+      _S_before(_SizeConstant<_I> = {})
       {
 	if constexpr (_I == 0)
 	  return _SizeConstant<0>();
@@ -3805,7 +3912,8 @@ template <size_t _V0, size_t... _Values>
       }
 
     template <size_t _Np>
-      static constexpr auto _S_pop_front(_SizeConstant<_Np> = {})
+      static constexpr auto
+      _S_pop_front(_SizeConstant<_Np> = {})
       {
 	if constexpr (_Np == 0)
 	  return _SizeList();
@@ -3900,12 +4008,11 @@ template <typename _V, typename _Ap,
       }
     else if (__x._M_is_constprop())
       {
-	return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	  auto __i) constexpr {
-	  return _V([&](auto __j) constexpr {
-	    return __x[__i * _V::size() + __j];
-	  });
-	});
+	return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return _V([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+			     { return __x[__i * _V::size() + __j]; });
+		 });
       }
     else if constexpr (
       __is_fixed_size_abi_v<_Ap>
@@ -3918,49 +4025,47 @@ template <typename _V, typename _Ap,
 #ifdef _GLIBCXX_SIMD_USE_ALIASING_LOADS
       const __may_alias<_Tp>* const __element_ptr
 	= reinterpret_cast<const __may_alias<_Tp>*>(&__data(__x));
-      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	auto __i) constexpr {
-	return _V(__element_ptr + __i * _V::size(), vector_aligned);
-      });
+      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+	       { return _V(__element_ptr + __i * _V::size(), vector_aligned); });
 #else
       const auto& __xx = __data(__x);
-      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	auto __i) constexpr {
-	[[maybe_unused]] constexpr size_t __offset
-	  = decltype(__i)::value * _V::size();
-	return _V([&](auto __j) constexpr {
-	  constexpr _SizeConstant<__j + __offset> __k;
-	  return __xx[__k];
-	});
-      });
+      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		 [[maybe_unused]] constexpr size_t __offset
+		   = decltype(__i)::value * _V::size();
+		 return _V([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			  constexpr _SizeConstant<__j + __offset> __k;
+			  return __xx[__k];
+			});
+	       });
 #endif
     }
   else if constexpr (is_same_v<typename _V::abi_type, simd_abi::scalar>)
     {
       // normally memcpy should work here as well
-      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	auto __i) constexpr { return __x[__i]; });
+      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; });
     }
   else
     {
-      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	auto __i) constexpr {
-	if constexpr (__is_fixed_size_abi_v<typename _V::abi_type>)
-	  return _V([&](auto __j) constexpr {
-	    return __x[__i * _V::size() + __j];
-	  });
-	else
-	  return _V(__private_init,
-		    __extract_part<decltype(__i)::value, _Parts>(__data(__x)));
-      });
+      return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		 if constexpr (__is_fixed_size_abi_v<typename _V::abi_type>)
+		   return _V([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			    return __x[__i * _V::size() + __j];
+			  });
+		 else
+		   return _V(__private_init,
+			     __extract_part<decltype(__i)::value, _Parts>(__data(__x)));
+	       });
     }
   }
 
 // }}}
 // split<simd_mask>(simd_mask) {{{
 template <typename _V, typename _Ap,
-	  size_t _Parts
-	  = simd_size_v<typename _V::simd_type::value_type, _Ap> / _V::size()>
+	  size_t _Parts = simd_size_v<typename _V::simd_type::value_type, _Ap> / _V::size()>
   enable_if_t<is_simd_mask_v<_V> && simd_size_v<typename
     _V::simd_type::value_type, _Ap> == _Parts * _V::size(), array<_V, _Parts>>
   split(const simd_mask<typename _V::simd_type::value_type, _Ap>& __x)
@@ -3976,22 +4081,22 @@ template <typename _V, typename _Ap,
     else if constexpr (_V::size() <= __CHAR_BIT__ * sizeof(_ULLong))
       {
 	const bitset __bits = __x.__to_bitset();
-	return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	  auto __i) constexpr {
-	  constexpr size_t __offset = __i * _V::size();
-	  return _V(__bitset_init, (__bits >> __offset).to_ullong());
-	});
+	return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   constexpr size_t __offset = __i * _V::size();
+		   return _V(__bitset_init, (__bits >> __offset).to_ullong());
+		 });
       }
     else
       {
-	return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>([&](
-	  auto __i) constexpr {
-	  constexpr size_t __offset = __i * _V::size();
-	  return _V(
-	    __private_init, [&](auto __j) constexpr {
-	      return __x[__j + __offset];
-	    });
-	});
+	return __generate_from_n_evaluations<_Parts, array<_V, _Parts>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   constexpr size_t __offset = __i * _V::size();
+		   return _V(__private_init,
+			     [&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			       return __x[__j + __offset];
+			     });
+		 });
       }
   }
 
@@ -4009,12 +4114,14 @@ template <size_t... _Sizes, typename _Tp, typename _Ap, typename>
     using _V = __deduced_simd<_Tp, _N0>;
 
     if (__x._M_is_constprop())
-      return __generate_from_n_evaluations<sizeof...(_Sizes), _Tuple>([&](
-	auto __i) constexpr {
-	using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>;
-	constexpr size_t __offset = _SL::_S_before(__i);
-	return _Vi([&](auto __j) constexpr { return __x[__offset + __j]; });
-      });
+      return __generate_from_n_evaluations<sizeof...(_Sizes), _Tuple>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		 using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>;
+		 constexpr size_t __offset = _SL::_S_before(__i);
+		 return _Vi([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			  return __x[__offset + __j];
+			});
+	       });
     else if constexpr (_Np == _N0)
       {
 	static_assert(sizeof...(_Sizes) == 1);
@@ -4081,28 +4188,28 @@ template <size_t... _Sizes, typename _Tp, typename _Ap, typename>
 #ifdef _GLIBCXX_SIMD_USE_ALIASING_LOADS
     const __may_alias<_Tp>* const __element_ptr
       = reinterpret_cast<const __may_alias<_Tp>*>(&__x);
-    return __generate_from_n_evaluations<sizeof...(_Sizes), _Tuple>([&](
-      auto __i) constexpr {
-      using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>;
-      constexpr size_t __offset = _SL::_S_before(__i);
-      constexpr size_t __base_align = alignof(simd<_Tp, _Ap>);
-      constexpr size_t __a
-	= __base_align - ((__offset * sizeof(_Tp)) % __base_align);
-      constexpr size_t __b = ((__a - 1) & __a) ^ __a;
-      constexpr size_t __alignment = __b == 0 ? __a : __b;
-      return _Vi(__element_ptr + __offset, overaligned<__alignment>);
-    });
+    return __generate_from_n_evaluations<sizeof...(_Sizes), _Tuple>(
+	     [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	       using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>;
+	       constexpr size_t __offset = _SL::_S_before(__i);
+	       constexpr size_t __base_align = alignof(simd<_Tp, _Ap>);
+	       constexpr size_t __a
+		 = __base_align - ((__offset * sizeof(_Tp)) % __base_align);
+	       constexpr size_t __b = ((__a - 1) & __a) ^ __a;
+	       constexpr size_t __alignment = __b == 0 ? __a : __b;
+	       return _Vi(__element_ptr + __offset, overaligned<__alignment>);
+	     });
 #else
-    return __generate_from_n_evaluations<sizeof...(_Sizes), _Tuple>([&](
-      auto __i) constexpr {
-      using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>;
-      const auto& __xx = __data(__x);
-      using _Offset = decltype(_SL::_S_before(__i));
-      return _Vi([&](auto __j) constexpr {
-	constexpr _SizeConstant<_Offset::value + __j> __k;
-	return __xx[__k];
-      });
-    });
+    return __generate_from_n_evaluations<sizeof...(_Sizes), _Tuple>(
+	     [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	       using _Vi = __deduced_simd<_Tp, _SL::_S_at(__i)>;
+	       const auto& __xx = __data(__x);
+	       using _Offset = decltype(_SL::_S_before(__i));
+	       return _Vi([&](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			constexpr _SizeConstant<_Offset::value + __j> __k;
+			return __xx[__k];
+		      });
+	     });
 #endif
   }
 
@@ -4123,8 +4230,7 @@ template <size_t _I, typename _Tp, typename _Ap, typename... _As>
 // __store_pack_of_simd {{{
 template <typename _Tp, typename _A0, typename... _As>
   _GLIBCXX_SIMD_INTRINSIC void
-  __store_pack_of_simd(char* __mem, const simd<_Tp, _A0>& __x0,
-		       const simd<_Tp, _As>&... __xs)
+  __store_pack_of_simd(char* __mem, const simd<_Tp, _A0>& __x0, const simd<_Tp, _As>&... __xs)
   {
     constexpr size_t __n_bytes = sizeof(_Tp) * simd_size_v<_Tp, _A0>;
     __builtin_memcpy(__mem, &__data(__x0), __n_bytes);
@@ -4144,8 +4250,9 @@ template <typename _Tp, typename... _As, typename = __detail::__odr_helper>
       return simd_cast<_Rp>(__xs...);
     else if ((... && __xs._M_is_constprop()))
       return simd<_Tp,
-		  simd_abi::deduce_t<_Tp, (simd_size_v<_Tp, _As> + ...)>>([&](
-	auto __i) constexpr { return __subscript_in_pack<__i>(__xs...); });
+		  simd_abi::deduce_t<_Tp, (simd_size_v<_Tp, _As> + ...)>>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+	       { return __subscript_in_pack<__i>(__xs...); });
     else
       {
 	_Rp __r{};
@@ -4161,9 +4268,10 @@ template <typename _Tp, typename _Abi, size_t _Np>
   _GLIBCXX_SIMD_CONSTEXPR __deduced_simd<_Tp, simd_size_v<_Tp, _Abi> * _Np>
   concat(const array<simd<_Tp, _Abi>, _Np>& __x)
   {
-    return __call_with_subscripts<_Np>(__x, [](const auto&... __xs) {
-      return concat(__xs...);
-    });
+    return __call_with_subscripts<_Np>(
+	     __x, [](const auto&... __xs) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	       return concat(__xs...);
+	     });
   }
 
 // }}}
@@ -4178,7 +4286,8 @@ template <typename _Up, typename _Accessor = _Up,
     int _M_index;
     _Up& _M_obj;
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr _ValueType _M_read() const noexcept
+    _GLIBCXX_SIMD_INTRINSIC constexpr _ValueType
+    _M_read() const noexcept
     {
       if constexpr (is_arithmetic_v<_Up>)
 	return _M_obj;
@@ -4187,7 +4296,8 @@ template <typename _Up, typename _Accessor = _Up,
     }
 
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC constexpr void _M_write(_Tp&& __x) const
+      _GLIBCXX_SIMD_INTRINSIC constexpr void
+      _M_write(_Tp&& __x) const
       { _Accessor::_S_set(_M_obj, _M_index, static_cast<_Tp&&>(__x)); }
 
   public:
@@ -4197,32 +4307,32 @@ template <typename _Up, typename _Accessor = _Up,
 
     using value_type = _ValueType;
 
-    _GLIBCXX_SIMD_INTRINSIC _SmartReference(const _SmartReference&) = delete;
+    _GLIBCXX_SIMD_INTRINSIC
+    _SmartReference(const _SmartReference&) = delete;
 
-    _GLIBCXX_SIMD_INTRINSIC constexpr operator value_type() const noexcept
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    operator value_type() const noexcept
     { return _M_read(); }
 
-    template <typename _Tp,
-	      typename
-	      = _ValuePreservingOrInt<__remove_cvref_t<_Tp>, value_type>>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference operator=(_Tp&& __x) &&
+    template <typename _Tp, typename = _ValuePreservingOrInt<__remove_cvref_t<_Tp>, value_type>>
+      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference
+      operator=(_Tp&& __x) &&
       {
 	_M_write(static_cast<_Tp&&>(__x));
 	return {_M_obj, _M_index};
       }
 
-#define _GLIBCXX_SIMD_OP_(__op)                                                \
-    template <typename _Tp,                                                    \
-	      typename _TT                                                     \
-	      = decltype(declval<value_type>() __op declval<_Tp>()),           \
-	      typename = _ValuePreservingOrInt<__remove_cvref_t<_Tp>, _TT>,    \
-	      typename = _ValuePreservingOrInt<_TT, value_type>>               \
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference                        \
-      operator __op##=(_Tp&& __x) &&                                           \
-      {                                                                        \
-	const value_type& __lhs = _M_read();                                   \
-	_M_write(__lhs __op __x);                                              \
-	return {_M_obj, _M_index};                                             \
+#define _GLIBCXX_SIMD_OP_(__op)                                                   \
+    template <typename _Tp,                                                       \
+	      typename _TT = decltype(declval<value_type>() __op declval<_Tp>()), \
+	      typename = _ValuePreservingOrInt<__remove_cvref_t<_Tp>, _TT>,       \
+	      typename = _ValuePreservingOrInt<_TT, value_type>>                  \
+      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference                           \
+      operator __op##=(_Tp&& __x) &&                                              \
+      {                                                                           \
+	const value_type& __lhs = _M_read();                                      \
+	_M_write(__lhs __op __x);                                                 \
+	return {_M_obj, _M_index};                                                \
       }
     _GLIBCXX_SIMD_ALL_ARITHMETICS(_GLIBCXX_SIMD_OP_);
     _GLIBCXX_SIMD_ALL_SHIFTS(_GLIBCXX_SIMD_OP_);
@@ -4230,9 +4340,9 @@ template <typename _Up, typename _Accessor = _Up,
 #undef _GLIBCXX_SIMD_OP_
 
     template <typename _Tp = void,
-	      typename
-	      = decltype(++declval<conditional_t<true, value_type, _Tp>&>())>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference operator++() &&
+	      typename = decltype(++declval<conditional_t<true, value_type, _Tp>&>())>
+      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference
+      operator++() &&
       {
 	value_type __x = _M_read();
 	_M_write(++__x);
@@ -4240,9 +4350,9 @@ template <typename _Up, typename _Accessor = _Up,
       }
 
     template <typename _Tp = void,
-	      typename
-	      = decltype(declval<conditional_t<true, value_type, _Tp>&>()++)>
-      _GLIBCXX_SIMD_INTRINSIC constexpr value_type operator++(int) &&
+	      typename = decltype(declval<conditional_t<true, value_type, _Tp>&>()++)>
+      _GLIBCXX_SIMD_INTRINSIC constexpr value_type
+      operator++(int) &&
       {
 	const value_type __r = _M_read();
 	value_type __x = __r;
@@ -4251,9 +4361,9 @@ template <typename _Up, typename _Accessor = _Up,
       }
 
     template <typename _Tp = void,
-	      typename
-	      = decltype(--declval<conditional_t<true, value_type, _Tp>&>())>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference operator--() &&
+	      typename = decltype(--declval<conditional_t<true, value_type, _Tp>&>())>
+      _GLIBCXX_SIMD_INTRINSIC constexpr _SmartReference
+      operator--() &&
       {
 	value_type __x = _M_read();
 	_M_write(--__x);
@@ -4261,9 +4371,9 @@ template <typename _Up, typename _Accessor = _Up,
       }
 
     template <typename _Tp = void,
-	      typename
-	      = decltype(declval<conditional_t<true, value_type, _Tp>&>()--)>
-      _GLIBCXX_SIMD_INTRINSIC constexpr value_type operator--(int) &&
+	      typename = decltype(declval<conditional_t<true, value_type, _Tp>&>()--)>
+      _GLIBCXX_SIMD_INTRINSIC constexpr value_type
+      operator--(int) &&
       {
 	const value_type __r = _M_read();
 	value_type __x = __r;
@@ -4339,7 +4449,8 @@ template <int _Bytes>
 template <template <int> class _Abi, int _Bytes, typename _Tp>
   struct __find_next_valid_abi
   {
-    static constexpr auto _S_choose()
+    static constexpr auto
+    _S_choose()
     {
       constexpr int _NextBytes = std::__bit_ceil(_Bytes) / 2;
       using _NextAbi = _Abi<_NextBytes>;
@@ -4383,7 +4494,8 @@ template <template <int> class _A0, template <int> class... _Rest>
 	typename _AbiList<_Rest...>::template _FirstValidAbi<_Tp, _Np>>;
 
     template <typename _Tp, int _Np>
-      static constexpr auto _S_determine_best_abi()
+      static constexpr auto
+      _S_determine_best_abi()
       {
 	static_assert(_Np >= 1);
 	constexpr int _Bytes = sizeof(_Tp) * _Np;
@@ -4496,7 +4608,7 @@ template <typename _Tp, typename _Abi>
 
     // }}}
     // access to internal representation (optional feature) {{{
-    _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR explicit
     simd_mask(typename _Traits::_MaskCastType __init)
     : _M_data{__init} {}
     // conversions to internal type is done in _MaskBase
@@ -4507,11 +4619,11 @@ template <typename _Tp, typename _Abi>
     // Conversion of simd_mask to and from bitset makes it much easier to
     // interface with other facilities. I suggest adding `static
     // simd_mask::from_bitset` and `simd_mask::to_bitset`.
-    _GLIBCXX_SIMD_ALWAYS_INLINE static simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR static simd_mask
     __from_bitset(bitset<size()> bs)
     { return {__bitset_init, bs}; }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE bitset<size()>
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR bitset<size()>
     __to_bitset() const
     { return _Impl::_S_to_bits(_M_data)._M_to_bitset(); }
 
@@ -4536,7 +4648,7 @@ template <typename _Tp, typename _Abi>
     template <typename _Up, typename = enable_if_t<conjunction<
 			      is_same<abi_type, simd_abi::fixed_size<size()>>,
 			      is_same<_Up, _Up>>::value>>
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR
       simd_mask(const simd_mask<_Up, simd_abi::fixed_size<size()>>& __x)
       : _M_data(_Impl::_S_from_bitmask(__data(__x), _S_type_tag)) {}
   #endif
@@ -4544,41 +4656,36 @@ template <typename _Tp, typename _Abi>
     // }}}
     // load constructor {{{
     template <typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      simd_mask(const value_type* __mem, _Flags)
-      : _M_data(_Impl::template _S_load<_Ip>(
-	_Flags::template _S_apply<simd_mask>(__mem))) {}
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR
+      simd_mask(const value_type* __mem, _IsSimdFlagType<_Flags>)
+      : _M_data(_Impl::template _S_load<_Ip>(_Flags::template _S_apply<simd_mask>(__mem))) {}
 
     template <typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      simd_mask(const value_type* __mem, simd_mask __k, _Flags)
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR
+      simd_mask(const value_type* __mem, simd_mask __k, _IsSimdFlagType<_Flags>)
       : _M_data{}
       {
-	_M_data
-	  = _Impl::_S_masked_load(_M_data, __k._M_data,
-				  _Flags::template _S_apply<simd_mask>(__mem));
+	_M_data = _Impl::_S_masked_load(_M_data, __k._M_data,
+					_Flags::template _S_apply<simd_mask>(__mem));
       }
 
     // }}}
     // loads [simd_mask.load] {{{
     template <typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE void
-      copy_from(const value_type* __mem, _Flags)
-      {
-	_M_data = _Impl::template _S_load<_Ip>(
-	  _Flags::template _S_apply<simd_mask>(__mem));
-      }
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR void
+      copy_from(const value_type* __mem, _IsSimdFlagType<_Flags>)
+      { _M_data = _Impl::template _S_load<_Ip>(_Flags::template _S_apply<simd_mask>(__mem)); }
 
     // }}}
     // stores [simd_mask.store] {{{
     template <typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE void
-      copy_to(value_type* __mem, _Flags) const
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR void
+      copy_to(value_type* __mem, _IsSimdFlagType<_Flags>) const
       { _Impl::_S_store(_M_data, _Flags::template _S_apply<simd_mask>(__mem)); }
 
     // }}}
     // scalar access {{{
-    _GLIBCXX_SIMD_ALWAYS_INLINE reference
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR reference
     operator[](size_t __i)
     {
       if (__i >= size())
@@ -4586,7 +4693,7 @@ template <typename _Tp, typename _Abi>
       return {_M_data, int(__i)};
     }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE value_type
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR value_type
     operator[](size_t __i) const
     {
       if (__i >= size())
@@ -4599,7 +4706,7 @@ template <typename _Tp, typename _Abi>
 
     // }}}
     // negation {{{
-    _GLIBCXX_SIMD_ALWAYS_INLINE simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR simd_mask
     operator!() const
     { return {__private_init, _Impl::_S_bit_not(_M_data)}; }
 
@@ -4608,9 +4715,8 @@ template <typename _Tp, typename _Abi>
   #ifdef _GLIBCXX_SIMD_ENABLE_IMPLICIT_MASK_CAST
     // simd_mask<int> && simd_mask<uint> needs disambiguation
     template <typename _Up, typename _A2,
-	      typename
-	      = enable_if_t<is_convertible_v<simd_mask<_Up, _A2>, simd_mask>>>
-      _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+	      typename = enable_if_t<is_convertible_v<simd_mask<_Up, _A2>, simd_mask>>>
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
       operator&&(const simd_mask& __x, const simd_mask<_Up, _A2>& __y)
       {
 	return {__private_init,
@@ -4618,9 +4724,8 @@ template <typename _Tp, typename _Abi>
       }
 
     template <typename _Up, typename _A2,
-	      typename
-	      = enable_if_t<is_convertible_v<simd_mask<_Up, _A2>, simd_mask>>>
-      _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+	      typename = enable_if_t<is_convertible_v<simd_mask<_Up, _A2>, simd_mask>>>
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
       operator||(const simd_mask& __x, const simd_mask<_Up, _A2>& __y)
       {
 	return {__private_init,
@@ -4628,45 +4733,41 @@ template <typename _Tp, typename _Abi>
       }
   #endif // _GLIBCXX_SIMD_ENABLE_IMPLICIT_MASK_CAST
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
     operator&&(const simd_mask& __x, const simd_mask& __y)
-    {
-      return {__private_init, _Impl::_S_logical_and(__x._M_data, __y._M_data)};
-    }
+    { return {__private_init, _Impl::_S_logical_and(__x._M_data, __y._M_data)}; }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
     operator||(const simd_mask& __x, const simd_mask& __y)
-    {
-      return {__private_init, _Impl::_S_logical_or(__x._M_data, __y._M_data)};
-    }
+    { return {__private_init, _Impl::_S_logical_or(__x._M_data, __y._M_data)}; }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
     operator&(const simd_mask& __x, const simd_mask& __y)
     { return {__private_init, _Impl::_S_bit_and(__x._M_data, __y._M_data)}; }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
     operator|(const simd_mask& __x, const simd_mask& __y)
     { return {__private_init, _Impl::_S_bit_or(__x._M_data, __y._M_data)}; }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask
     operator^(const simd_mask& __x, const simd_mask& __y)
     { return {__private_init, _Impl::_S_bit_xor(__x._M_data, __y._M_data)}; }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask&
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask&
     operator&=(simd_mask& __x, const simd_mask& __y)
     {
       __x._M_data = _Impl::_S_bit_and(__x._M_data, __y._M_data);
       return __x;
     }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask&
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask&
     operator|=(simd_mask& __x, const simd_mask& __y)
     {
       __x._M_data = _Impl::_S_bit_or(__x._M_data, __y._M_data);
       return __x;
     }
 
-    _GLIBCXX_SIMD_ALWAYS_INLINE friend simd_mask&
+    _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR friend simd_mask&
     operator^=(simd_mask& __x, const simd_mask& __y)
     {
       __x._M_data = _Impl::_S_bit_xor(__x._M_data, __y._M_data);
@@ -4696,16 +4797,16 @@ template <typename _Tp, typename _Abi>
       simd_mask(_PrivateInit, _Fp&& __gen)
       : _M_data()
       {
-	__execute_n_times<size()>([&](auto __i) constexpr {
+	__execute_n_times<size()>([&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  _Impl::_S_set(_M_data, __i, __gen(__i));
 	});
       }
 
     // }}}
     // bitset_init ctor {{{
-    _GLIBCXX_SIMD_INTRINSIC simd_mask(_BitsetInit, bitset<size()> __init)
-    : _M_data(
-	_Impl::_S_from_bitmask(_SanitizedBitMask<size()>(__init), _S_type_tag))
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    simd_mask(_BitsetInit, bitset<size()> __init)
+    : _M_data(_Impl::_S_from_bitmask(_SanitizedBitMask<size()>(__init), _S_type_tag))
     {}
 
     // }}}
@@ -4717,8 +4818,7 @@ template <typename _Tp, typename _Abi>
     struct _CvtProxy
     {
       template <typename _Up, typename _A2,
-		typename
-		= enable_if_t<simd_size_v<_Up, _A2> == simd_size_v<_Tp, _Abi>>>
+		typename = enable_if_t<simd_size_v<_Up, _A2> == simd_size_v<_Tp, _Abi>>>
 	_GLIBCXX_SIMD_ALWAYS_INLINE
 	operator simd_mask<_Up, _A2>() &&
 	{
@@ -4882,7 +4982,9 @@ template <typename _Tp, typename _Abi>
     if (__builtin_is_constant_evaluated() || __k._M_is_constprop())
       {
 	const int __r = __call_with_subscripts<simd_size_v<_Tp, _Abi>>(
-	  __k, [](auto... __elements) { return ((__elements != 0) + ...); });
+			  __k, [](auto... __elements) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			    return ((__elements != 0) + ...);
+			  });
 	if (__builtin_is_constant_evaluated() || __builtin_constant_p(__r))
 	  return __r;
       }
@@ -4897,8 +4999,11 @@ template <typename _Tp, typename _Abi>
       {
 	constexpr size_t _Np = simd_size_v<_Tp, _Abi>;
 	const size_t _Idx = __call_with_n_evaluations<_Np>(
-	  [](auto... __indexes) { return std::min({__indexes...}); },
-	  [&](auto __i) { return __k[__i] ? +__i : _Np; });
+			      [](auto... __indexes) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				return std::min({__indexes...});
+			      }, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				return __k[__i] ? +__i : _Np;
+			      });
 	if (_Idx >= _Np)
 	  __invoke_ub("find_first_set(empty mask) is UB");
 	if (__builtin_constant_p(_Idx))
@@ -4915,8 +5020,11 @@ template <typename _Tp, typename _Abi>
       {
 	constexpr size_t _Np = simd_size_v<_Tp, _Abi>;
 	const int _Idx = __call_with_n_evaluations<_Np>(
-	  [](auto... __indexes) { return std::max({__indexes...}); },
-	  [&](auto __i) { return __k[__i] ? int(__i) : -1; });
+			   [](auto... __indexes) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			     return std::max({__indexes...});
+			   }, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			     return __k[__i] ? int(__i) : -1;
+			   });
 	if (_Idx < 0)
 	  __invoke_ub("find_first_set(empty mask) is UB");
 	if (__builtin_constant_p(_Idx))
@@ -4965,7 +5073,8 @@ template <typename _V, typename _Tp, typename _Abi>
   {
     using _Impl = typename _SimdTraits<_Tp, _Abi>::_SimdImpl;
 
-    _GLIBCXX_SIMD_INTRINSIC const _V& __derived() const
+    _GLIBCXX_SIMD_INTRINSIC constexpr const _V&
+    __derived() const
     { return *static_cast<const _V*>(this); }
 
     template <typename _Up>
@@ -5185,16 +5294,16 @@ template <typename _Tp, typename _Abi>
 
     // load constructor
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      simd(const _Up* __mem, _Flags)
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR
+      simd(const _Up* __mem, _IsSimdFlagType<_Flags>)
       : _M_data(
 	  _Impl::_S_load(_Flags::template _S_apply<simd>(__mem), _S_type_tag))
       {}
 
     // loads [simd.load]
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE void
-      copy_from(const _Vectorizable<_Up>* __mem, _Flags)
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR void
+      copy_from(const _Vectorizable<_Up>* __mem, _IsSimdFlagType<_Flags>)
       {
 	_M_data = static_cast<decltype(_M_data)>(
 	  _Impl::_S_load(_Flags::template _S_apply<simd>(__mem), _S_type_tag));
@@ -5202,8 +5311,8 @@ template <typename _Tp, typename _Abi>
 
     // stores [simd.store]
     template <typename _Up, typename _Flags>
-      _GLIBCXX_SIMD_ALWAYS_INLINE void
-      copy_to(_Vectorizable<_Up>* __mem, _Flags) const
+      _GLIBCXX_SIMD_ALWAYS_INLINE _GLIBCXX_SIMD_CONSTEXPR void
+      copy_to(_Vectorizable<_Up>* __mem, _IsSimdFlagType<_Flags>) const
       {
 	_Impl::_S_store(_M_data, _Flags::template _S_apply<simd>(__mem),
 			_S_type_tag);
@@ -5374,7 +5483,7 @@ template <typename _Tp, typename _Abi>
     }
 
   private:
-    _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR static mask_type
+    _GLIBCXX_SIMD_INTRINSIC static constexpr mask_type
     _S_make_mask(typename mask_type::_MemberType __k)
     { return {__private_init, __k}; }
 
@@ -5401,26 +5510,17 @@ namespace __float_bitwise_operators { //{{{
 template <typename _Tp, typename _Ap>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR simd<_Tp, _Ap>
   operator^(const simd<_Tp, _Ap>& __a, const simd<_Tp, _Ap>& __b)
-  {
-    return {__private_init,
-	    _Ap::_SimdImpl::_S_bit_xor(__data(__a), __data(__b))};
-  }
+  { return {__private_init, _Ap::_SimdImpl::_S_bit_xor(__data(__a), __data(__b))}; }
 
 template <typename _Tp, typename _Ap>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR simd<_Tp, _Ap>
   operator|(const simd<_Tp, _Ap>& __a, const simd<_Tp, _Ap>& __b)
-  {
-    return {__private_init,
-	    _Ap::_SimdImpl::_S_bit_or(__data(__a), __data(__b))};
-  }
+  { return {__private_init, _Ap::_SimdImpl::_S_bit_or(__data(__a), __data(__b))}; }
 
 template <typename _Tp, typename _Ap>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR simd<_Tp, _Ap>
   operator&(const simd<_Tp, _Ap>& __a, const simd<_Tp, _Ap>& __b)
-  {
-    return {__private_init,
-	    _Ap::_SimdImpl::_S_bit_and(__data(__a), __data(__b))};
-  }
+  { return {__private_init, _Ap::_SimdImpl::_S_bit_and(__data(__a), __data(__b))}; }
 
 template <typename _Tp, typename _Ap>
   _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_SIMD_CONSTEXPR
--- a/src/libstdc++-v3/include/experimental/bits/simd_builtin.h
+++ b/src/libstdc++-v3/include/experimental/bits/simd_builtin.h
@@ -52,7 +52,7 @@ template <typename _V, typename = _VectorTraits<_V>>
 // Index == -1 requests zeroing of the output element
 template <int... _Indices, typename _Tp, typename _TVT = _VectorTraits<_Tp>,
 	  typename = __detail::__odr_helper>
-  _Tp
+  constexpr _Tp
   __vector_permute(_Tp __x)
   {
     static_assert(sizeof...(_Indices) == _TVT::_S_full_size);
@@ -65,7 +65,7 @@ template <int... _Indices, typename _Tp, typename _TVT = _VectorTraits<_Tp>,
 // Index == -1 requests zeroing of the output element
 template <int... _Indices, typename _Tp, typename _TVT = _VectorTraits<_Tp>,
 	  typename = __detail::__odr_helper>
-  _Tp
+  constexpr _Tp
   __vector_shuffle(_Tp __x, _Tp __y)
   {
     return _Tp{(_Indices == -1 ? 0
@@ -194,15 +194,18 @@ template <unsigned __shift, typename _Tp, typename _TVT = _VectorTraits<_Tp>>
 	using _Up = decltype(__w);
 	return __intrin_bitcast<_Tp>(
 	  __call_with_n_evaluations<(sizeof(_Tp) - __shift) / __chunksize>(
-	    [](auto... __chunks) { return _Up{__chunks...}; },
-	    [&](auto __i) { return __w[__shift / __chunksize + __i]; }));
+	    [](auto... __chunks) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	      return _Up{__chunks...};
+	    }, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	      return __w[__shift / __chunksize + __i];
+	    }));
       }
   }
 
 // }}}
 // __extract_part(_SimdWrapper<_Tp, _Np>) {{{
 template <int _Index, int _Total, int _Combine, typename _Tp, size_t _Np>
-  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST
+  _GLIBCXX_SIMD_INTRINSIC _GLIBCXX_CONST constexpr
   _SimdWrapper<_Tp, _Np / _Total * _Combine>
   __extract_part(const _SimdWrapper<_Tp, _Np> __x)
   {
@@ -225,7 +228,9 @@ template <int _Index, int _Total, int _Combine, typename _Tp, size_t _Np>
 	// by _Total");
 	if (__x._M_is_constprop())
 	  return __generate_from_n_evaluations<__return_size, _R>(
-	    [&](auto __i) { return __x[__values_to_skip + __i]; });
+	    [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	      return __x[__values_to_skip + __i];
+	    });
 	if constexpr (_Index == 0 && _Total == 1)
 	  return __x;
 	else if constexpr (_Index == 0)
@@ -570,7 +575,9 @@ template <typename _To,
 	constexpr auto _Np
 	  = _NParts == 0 ? _FromVT::_S_partial_width - _Offset : _NParts;
 	return __generate_from_n_evaluations<_Np, array<_To, _Np>>(
-	  [&](auto __i) { return static_cast<_To>(__v[__i + _Offset]); });
+		 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return static_cast<_To>(__v[__i + _Offset]);
+		 });
       }
     else
       {
@@ -611,13 +618,14 @@ template <typename _To,
 	      return __vector_bitcast<_FromT, decltype(__n)::value>(__vv);
 	    };
 	    [[maybe_unused]] const auto __vi = __to_intrin(__v);
-	    auto&& __make_array = [](auto __x0, [[maybe_unused]] auto __x1) {
-	      if constexpr (_Np == 1)
-		return _R{__intrin_bitcast<_To>(__x0)};
-	      else
-		return _R{__intrin_bitcast<_To>(__x0),
-			  __intrin_bitcast<_To>(__x1)};
-	    };
+	    auto&& __make_array
+		= [](auto __x0, [[maybe_unused]] auto __x1) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		  if constexpr (_Np == 1)
+		    return _R{__intrin_bitcast<_To>(__x0)};
+		  else
+		    return _R{__intrin_bitcast<_To>(__x0),
+			      __intrin_bitcast<_To>(__x1)};
+		};
 
 	    if constexpr (_Np == 0)
 	      return _R{};
@@ -642,7 +650,7 @@ template <typename _To,
 		      = __convert_all<__vector_type16_t<int>, _Np>(
 			__adjust(_SizeConstant<_Np * 4>(), __v));
 		    return __generate_from_n_evaluations<_Np, _R>(
-		      [&](auto __i) {
+		      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 			return __vector_convert<_To>(__as_wrapper(__ints[__i]));
 		      });
 		  }
@@ -687,36 +695,40 @@ template <typename _To,
 		  __vector_bitcast<int>(_mm_unpacklo_epi16(__vv[1], __vv[1])),
 		  __vector_bitcast<int>(_mm_unpackhi_epi16(__vv[1], __vv[1]))};
 		if constexpr (sizeof(_ToT) == 4)
-		  return __generate_from_n_evaluations<_Np, _R>([&](auto __i) {
-		    return __vector_convert<_To>(
-		      _SimdWrapper<int, 4>(__vvvv[__i] >> 24));
-		  });
+		  return __generate_from_n_evaluations<_Np, _R>(
+			   [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			     return __vector_convert<_To>(
+				      _SimdWrapper<int, 4>(__vvvv[__i] >> 24));
+			   });
 		else if constexpr (is_integral_v<_ToT>)
-		  return __generate_from_n_evaluations<_Np, _R>([&](auto __i) {
-		    const auto __signbits = __to_intrin(__vvvv[__i / 2] >> 31);
-		    const auto __sx32 = __to_intrin(__vvvv[__i / 2] >> 24);
-		    return __vector_bitcast<_ToT>(
-		      __i % 2 == 0 ? _mm_unpacklo_epi32(__sx32, __signbits)
-				   : _mm_unpackhi_epi32(__sx32, __signbits));
-		  });
+		  return __generate_from_n_evaluations<_Np, _R>(
+			   [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			     const auto __signbits = __to_intrin(__vvvv[__i / 2] >> 31);
+			     const auto __sx32 = __to_intrin(__vvvv[__i / 2] >> 24);
+			     return __vector_bitcast<_ToT>(
+				      __i % 2 == 0 ? _mm_unpacklo_epi32(__sx32, __signbits)
+						   : _mm_unpackhi_epi32(__sx32, __signbits));
+			   });
 		else
-		  return __generate_from_n_evaluations<_Np, _R>([&](auto __i) {
-		    const _SimdWrapper<int, 4> __int4 = __vvvv[__i / 2] >> 24;
-		    return __vector_convert<_To>(
-		      __i % 2 == 0 ? __int4
-				   : _SimdWrapper<int, 4>(
-				     _mm_unpackhi_epi64(__to_intrin(__int4),
-							__to_intrin(__int4))));
-		  });
+		  return __generate_from_n_evaluations<_Np, _R>(
+			   [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			     const _SimdWrapper<int, 4> __int4 = __vvvv[__i / 2] >> 24;
+			     return __vector_convert<_To>(
+				      __i % 2 == 0 ? __int4
+						   : _SimdWrapper<int, 4>(
+						       _mm_unpackhi_epi64(__to_intrin(__int4),
+									  __to_intrin(__int4))));
+			   });
 	      }
 	    else if constexpr (sizeof(_FromT) == 1 && sizeof(_ToT) == 4)
 	      {
 		const auto __shorts = __convert_all<__vector_type16_t<
 		  conditional_t<is_signed_v<_FromT>, short, unsigned short>>>(
 		  __adjust(_SizeConstant<(_Np + 1) / 2 * 8>(), __v));
-		return __generate_from_n_evaluations<_Np, _R>([&](auto __i) {
-		  return __convert_all<_To>(__shorts[__i / 2])[__i % 2];
-		});
+		return __generate_from_n_evaluations<_Np, _R>(
+			 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			   return __convert_all<_To>(__shorts[__i / 2])[__i % 2];
+			 });
 	      }
 	    else if constexpr (sizeof(_FromT) == 2 && sizeof(_ToT) == 8
 			       && is_signed_v<_FromT> && is_integral_v<_ToT>)
@@ -736,9 +748,10 @@ template <typename _To,
 		     __vector_bitcast<int>(
 		       _mm_unpackhi_epi32(_mm_srai_epi32(__vv[1], 16),
 					  _mm_srai_epi32(__vv[1], 31)))};
-		return __generate_from_n_evaluations<_Np, _R>([&](auto __i) {
-		  return __vector_bitcast<_ToT>(__vvvv[__i]);
-		});
+		return __generate_from_n_evaluations<_Np, _R>(
+			 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			   return __vector_bitcast<_ToT>(__vvvv[__i]);
+			 });
 	      }
 	    else if constexpr (sizeof(_FromT) <= 2 && sizeof(_ToT) == 8)
 	      {
@@ -747,9 +760,10 @@ template <typename _To,
 		    is_signed_v<_FromT> || is_floating_point_v<_ToT>, int,
 		    unsigned int>>>(
 		    __adjust(_SizeConstant<(_Np + 1) / 2 * 4>(), __v));
-		return __generate_from_n_evaluations<_Np, _R>([&](auto __i) {
-		  return __convert_all<_To>(__ints[__i / 2])[__i % 2];
-		});
+		return __generate_from_n_evaluations<_Np, _R>(
+			 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			   return __convert_all<_To>(__ints[__i / 2])[__i % 2];
+			 });
 	      }
 	    else
 	      __assert_unreachable<_To>();
@@ -779,14 +793,14 @@ template <typename _To,
 		__extract_part<_Offset, _FromVT::_S_partial_width,
 			       _ToVT::_S_full_size>(__v))};
 	    else
-	      return __generate_from_n_evaluations<_Np, _R>([&](
-		auto __i) constexpr {
-		auto __part
-		  = __extract_part<__i * _ToVT::_S_full_size + _Offset,
-				   _FromVT::_S_partial_width,
-				   _ToVT::_S_full_size>(__v);
-		return __vector_convert<_To>(__part);
-	      });
+	      return __generate_from_n_evaluations<_Np, _R>(
+		       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			 auto __part
+			   = __extract_part<__i * _ToVT::_S_full_size + _Offset,
+					    _FromVT::_S_partial_width,
+					    _ToVT::_S_full_size>(__v);
+			 return __vector_convert<_To>(__part);
+		       });
 	  }
 	else if constexpr (_Offset == 0)
 	  return array<_To, 1>{__vector_convert<_To>(__v)};
@@ -822,22 +836,19 @@ template <typename _Tp, typename _Mp, typename _Abi, size_t _Np>
     // _SimdBase / base class for simd, providing extra conversions {{{
     struct _SimdBase2
     {
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      explicit operator __intrinsic_type_t<_Tp, _Np>() const
-      {
-	return __to_intrin(static_cast<const simd<_Tp, _Abi>*>(this)->_M_data);
-      }
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      explicit operator __vector_type_t<_Tp, _Np>() const
-      {
-	return static_cast<const simd<_Tp, _Abi>*>(this)->_M_data.__builtin();
-      }
+      _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+      operator __intrinsic_type_t<_Tp, _Np>() const
+      { return __to_intrin(static_cast<const simd<_Tp, _Abi>*>(this)->_M_data); }
+
+      _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+      operator __vector_type_t<_Tp, _Np>() const
+      { return static_cast<const simd<_Tp, _Abi>*>(this)->_M_data.__builtin(); }
     };
 
     struct _SimdBase1
     {
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      explicit operator __intrinsic_type_t<_Tp, _Np>() const
+      _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+      operator __intrinsic_type_t<_Tp, _Np>() const
       { return __data(*static_cast<const simd<_Tp, _Abi>*>(this)); }
     };
 
@@ -849,23 +860,19 @@ template <typename _Tp, typename _Mp, typename _Abi, size_t _Np>
     // _MaskBase {{{
     struct _MaskBase2
     {
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      explicit operator __intrinsic_type_t<_Tp, _Np>() const
-      {
-	return static_cast<const simd_mask<_Tp, _Abi>*>(this)
-	  ->_M_data.__intrin();
-      }
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      explicit operator __vector_type_t<_Tp, _Np>() const
-      {
-	return static_cast<const simd_mask<_Tp, _Abi>*>(this)->_M_data._M_data;
-      }
+      _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+      operator __intrinsic_type_t<_Tp, _Np>() const
+      { return static_cast<const simd_mask<_Tp, _Abi>*>(this) ->_M_data.__intrin(); }
+
+      _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+      operator __vector_type_t<_Tp, _Np>() const
+      { return static_cast<const simd_mask<_Tp, _Abi>*>(this)->_M_data._M_data; }
     };
 
     struct _MaskBase1
     {
-      _GLIBCXX_SIMD_ALWAYS_INLINE
-      explicit operator __intrinsic_type_t<_Tp, _Np>() const
+      _GLIBCXX_SIMD_ALWAYS_INLINE explicit
+      operator __intrinsic_type_t<_Tp, _Np>() const
       { return __data(*static_cast<const simd_mask<_Tp, _Abi>*>(this)); }
     };
 
@@ -884,6 +891,7 @@ template <typename _Tp, typename _Mp, typename _Abi, size_t _Np>
     public:
       _GLIBCXX_SIMD_ALWAYS_INLINE
       _MaskCastType(_Up __x) : _M_data(__x) {}
+
       _GLIBCXX_SIMD_ALWAYS_INLINE
       operator _MaskMember() const { return _M_data; }
     };
@@ -897,9 +905,10 @@ template <typename _Tp, typename _Mp, typename _Abi, size_t _Np>
       _SimdMember _M_data;
 
     public:
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+      _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
       _SimdCastType1(_Ap __a) : _M_data(__vector_bitcast<_Tp>(__a)) {}
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+
+      _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
       operator _SimdMember() const { return _M_data; }
     };
 
@@ -910,11 +919,13 @@ template <typename _Tp, typename _Mp, typename _Abi, size_t _Np>
       _SimdMember _M_data;
 
     public:
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+      _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
       _SimdCastType2(_Ap __a) : _M_data(__vector_bitcast<_Tp>(__a)) {}
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+
+      _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
       _SimdCastType2(_Bp __b) : _M_data(__b) {}
-      _GLIBCXX_SIMD_ALWAYS_INLINE
+
+      _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
       operator _SimdMember() const { return _M_data; }
     };
 
@@ -1017,23 +1028,21 @@ template <int _UsedBytes>
 	else
 	  {
 	    constexpr auto __size = _S_size<_Tp>;
-	    _GLIBCXX_SIMD_USE_CONSTEXPR auto __r = __generate_vector<_UV>(
-	      [](auto __i) constexpr { return __i < __size ? -1 : 0; });
+	    _GLIBCXX_SIMD_USE_CONSTEXPR auto __r
+	      = __generate_vector<_UV>([](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+				       { return __i < __size ? -1 : 0; });
 	    return __r;
 	  }
       }
 
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static constexpr __intrinsic_type_t<_Tp,
-								  _S_size<_Tp>>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr __intrinsic_type_t<_Tp, _S_size<_Tp>>
       _S_implicit_mask_intrin()
-      {
-	return __to_intrin(
-	  __vector_bitcast<_Tp>(_S_implicit_mask<_Tp>()._M_data));
-      }
+      { return __to_intrin(__vector_bitcast<_Tp>(_S_implicit_mask<_Tp>()._M_data)); }
 
     template <typename _TW, typename _TVT = _VectorTraits<_TW>>
-      _GLIBCXX_SIMD_INTRINSIC static constexpr _TW _S_masked(_TW __x)
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _TW
+      _S_masked(_TW __x)
       {
 	using _Tp = typename _TVT::value_type;
 	if constexpr (!_MaskMember<_Tp>::_S_is_partial)
@@ -1155,8 +1164,7 @@ template <int _UsedBytes>
       { return __implicit_mask_n<_S_size<_Tp>>(); }
 
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static constexpr __bool_storage_member_type_t<
-	_S_size<_Tp>>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr __bool_storage_member_type_t<_S_size<_Tp>>
       _S_implicit_mask_intrin()
       { return __implicit_mask_n<_S_size<_Tp>>(); }
 
@@ -1208,7 +1216,7 @@ template <int _UsedBytes>
 	    if constexpr (is_integral_v<typename _TVT::value_type>)
 	      return __x
 		     | __generate_vector<_Tp, _S_full_size<_Tp>>(
-		       [](auto __i) -> _Tp {
+		       [](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA -> _Tp {
 			 if (__i < _Np)
 			   return 0;
 			 else
@@ -1288,7 +1296,8 @@ struct _CommonImplBuiltin
   // }}}
   // _S_store {{{
   template <size_t _ReqBytes = 0, typename _TV>
-    _GLIBCXX_SIMD_INTRINSIC static void _S_store(_TV __x, void* __addr)
+    _GLIBCXX_SIMD_INTRINSIC static void
+    _S_store(_TV __x, void* __addr)
     {
       constexpr size_t _Bytes = _ReqBytes == 0 ? sizeof(__x) : _ReqBytes;
       static_assert(sizeof(__x) >= _Bytes);
@@ -1324,8 +1333,8 @@ struct _CommonImplBuiltin
     }
 
   template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static void _S_store(_SimdWrapper<_Tp, _Np> __x,
-						 void* __addr)
+    _GLIBCXX_SIMD_INTRINSIC static void
+    _S_store(_SimdWrapper<_Tp, _Np> __x, void* __addr)
     { _S_store<_Np * sizeof(_Tp)>(__x._M_data, __addr); }
 
   // }}}
@@ -1336,6 +1345,11 @@ struct _CommonImplBuiltin
     {
       if constexpr (_Np == 1)
 	__mem[0] = __x[0];
+      else if (__builtin_is_constant_evaluated())
+	{
+	  for (size_t __i = 0; __i < _Np; ++__i)
+	    __mem[__i] = __x[__i];
+	}
       else if constexpr (_Np == 2)
 	{
 	  short __bool2 = (__x._M_to_bits() * 0x81) & 0x0101;
@@ -1348,26 +1362,27 @@ struct _CommonImplBuiltin
 	}
       else
 	{
-	  __execute_n_times<__div_roundup(_Np, 4)>([&](auto __i) {
-	    constexpr int __offset = __i * 4;
-	    constexpr int __remaining = _Np - __offset;
-	    if constexpr (__remaining > 4 && __remaining <= 7)
-	      {
-		const _ULLong __bool7
-		  = (__x.template _M_extract<__offset>()._M_to_bits()
-		     * 0x40810204081ULL)
-		    & 0x0101010101010101ULL;
-		_S_store<__remaining>(__bool7, __mem + __offset);
-	      }
-	    else if constexpr (__remaining >= 4)
-	      {
-		int __bits = __x.template _M_extract<__offset>()._M_to_bits();
-		if constexpr (__remaining > 7)
-		  __bits &= 0xf;
-		const int __bool4 = (__bits * 0x204081) & 0x01010101;
-		_S_store<4>(__bool4, __mem + __offset);
-	      }
-	  });
+	  __execute_n_times<__div_roundup(_Np, 4)>(
+	    [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	      constexpr int __offset = __i * 4;
+	      constexpr int __remaining = _Np - __offset;
+	      if constexpr (__remaining > 4 && __remaining <= 7)
+		{
+		  const _ULLong __bool7
+		    = (__x.template _M_extract<__offset>()._M_to_bits()
+			 * 0x40810204081ULL)
+			& 0x0101010101010101ULL;
+		  _S_store<__remaining>(__bool7, __mem + __offset);
+		}
+	      else if constexpr (__remaining >= 4)
+		{
+		  int __bits = __x.template _M_extract<__offset>()._M_to_bits();
+		  if constexpr (__remaining > 7)
+		    __bits &= 0xf;
+		  const int __bool4 = (__bits * 0x204081) & 0x01010101;
+		  _S_store<4>(__bool4, __mem + __offset);
+		}
+	    });
 	}
     }
 
@@ -1414,12 +1429,12 @@ template <typename _Abi, typename>
 
     // _M_make_simd(_SimdWrapper/__intrinsic_type_t) {{{2
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static simd<_Tp, _Abi>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr simd<_Tp, _Abi>
       _M_make_simd(_SimdWrapper<_Tp, _Np> __x)
       { return {__private_init, __x}; }
 
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static simd<_Tp, _Abi>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr simd<_Tp, _Abi>
       _M_make_simd(__intrinsic_type_t<_Tp, _Np> __x)
       { return {__private_init, __vector_bitcast<_Tp>(__x)}; }
 
@@ -1431,21 +1446,21 @@ template <typename _Abi, typename>
 
     // _S_generator {{{2
     template <typename _Fp, typename _Tp>
-      inline static constexpr _SimdMember<_Tp> _S_generator(_Fp&& __gen,
-							    _TypeTag<_Tp>)
+      inline static constexpr _SimdMember<_Tp>
+      _S_generator(_Fp&& __gen, _TypeTag<_Tp>)
       {
-	return __generate_vector<_Tp, _S_full_size<_Tp>>([&](
-	  auto __i) constexpr {
-	  if constexpr (__i < _S_size<_Tp>)
-	    return __gen(__i);
-	  else
-	    return 0;
-	});
+	return __generate_vector<_Tp, _S_full_size<_Tp>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   if constexpr (__i < _S_size<_Tp>)
+		     return __gen(__i);
+		   else
+		     return 0;
+		 });
       }
 
     // _S_load {{{2
     template <typename _Tp, typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC static _SimdMember<_Tp>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdMember<_Tp>
       _S_load(const _Up* __mem, _TypeTag<_Tp>) noexcept
       {
 	constexpr size_t _Np = _S_size<_Tp>;
@@ -1454,11 +1469,16 @@ template <typename _Abi, typename>
 	    : (is_floating_point_v<_Up> && __have_avx) || __have_avx2 ? 32
 								      : 16;
 	constexpr size_t __bytes_to_load = sizeof(_Up) * _Np;
-	if constexpr (sizeof(_Up) > 8)
-	  return __generate_vector<_Tp, _SimdMember<_Tp>::_S_full_size>([&](
-	    auto __i) constexpr {
-	    return static_cast<_Tp>(__i < _Np ? __mem[__i] : 0);
-	  });
+	if (__builtin_is_constant_evaluated())
+	  return __generate_vector<_Tp, _S_full_size<_Tp>>(
+		   [&](auto __i) constexpr {
+		     return static_cast<_Tp>(__i < _Np ? __mem[__i] : 0);
+		   });
+	else if constexpr (sizeof(_Up) > 8)
+	  return __generate_vector<_Tp, _SimdMember<_Tp>::_S_full_size>(
+		   [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		     return static_cast<_Tp>(__i < _Np ? __mem[__i] : 0);
+		   });
 	else if constexpr (is_same_v<_Up, _Tp>)
 	  return _CommonImpl::template _S_load<_Tp, _S_full_size<_Tp>,
 					       _Np * sizeof(_Tp)>(__mem);
@@ -1470,13 +1490,12 @@ template <typename _Abi, typename>
 	    constexpr size_t __n_loads = __bytes_to_load / __max_load_size;
 	    constexpr size_t __elements_per_load = _Np / __n_loads;
 	    return __call_with_n_evaluations<__n_loads>(
-	      [](auto... __uncvted) {
-		return __convert<_SimdMember<_Tp>>(__uncvted...);
-	      },
-	      [&](auto __i) {
-		return _CommonImpl::template _S_load<_Up, __elements_per_load>(
-		  __mem + __i * __elements_per_load);
-	      });
+		     [](auto... __uncvted) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		       return __convert<_SimdMember<_Tp>>(__uncvted...);
+		     }, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		       return _CommonImpl::template _S_load<_Up, __elements_per_load>(
+						      __mem + __i * __elements_per_load);
+		     });
 	  }
 	else if constexpr (__bytes_to_load % (__max_load_size / 2) == 0
 			   && __max_load_size > 16)
@@ -1485,45 +1504,50 @@ template <typename _Abi, typename>
 	      = __bytes_to_load / (__max_load_size / 2);
 	    constexpr size_t __elements_per_load = _Np / __n_loads;
 	    return __call_with_n_evaluations<__n_loads>(
-	      [](auto... __uncvted) {
-		return __convert<_SimdMember<_Tp>>(__uncvted...);
-	      },
-	      [&](auto __i) {
-		return _CommonImpl::template _S_load<_Up, __elements_per_load>(
-		  __mem + __i * __elements_per_load);
-	      });
+		     [](auto... __uncvted) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		       return __convert<_SimdMember<_Tp>>(__uncvted...);
+		     }, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		       return _CommonImpl::template _S_load<_Up, __elements_per_load>(
+						      __mem + __i * __elements_per_load);
+		     });
 	  }
 	else // e.g. int[] -> <char, 9>
 	  return __call_with_subscripts(
-	    __mem, make_index_sequence<_Np>(), [](auto... __args) {
-	      return __vector_type_t<_Tp, _S_full_size<_Tp>>{
-		static_cast<_Tp>(__args)...};
-	    });
+	    __mem, make_index_sequence<_Np>(),
+		   [](auto... __args) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		     return __vector_type_t<_Tp, _S_full_size<_Tp>>{static_cast<_Tp>(__args)...};
+		   });
       }
 
     // _S_masked_load {{{2
     template <typename _Tp, size_t _Np, typename _Up>
-      static inline _SimdWrapper<_Tp, _Np>
+      static constexpr inline _SimdWrapper<_Tp, _Np>
       _S_masked_load(_SimdWrapper<_Tp, _Np> __merge, _MaskMember<_Tp> __k,
 		     const _Up* __mem) noexcept
       {
-	_BitOps::_S_bit_iteration(_MaskImpl::_S_to_bits(__k), [&](auto __i) {
-	  __merge._M_set(__i, static_cast<_Tp>(__mem[__i]));
-	});
+	_BitOps::_S_bit_iteration(_MaskImpl::_S_to_bits(__k),
+				  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				    __merge._M_set(__i, static_cast<_Tp>(__mem[__i]));
+				  });
 	return __merge;
       }
 
     // _S_store {{{2
     template <typename _Tp, typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_store(_SimdMember<_Tp> __v, _Up* __mem, _TypeTag<_Tp>) noexcept
       {
 	// TODO: converting int -> "smaller int" can be optimized with AVX512
 	constexpr size_t _Np = _S_size<_Tp>;
 	constexpr size_t __max_store_size
 	  = _SuperImpl::template _S_max_store_size<_Up>;
-	if constexpr (sizeof(_Up) > 8)
-	  __execute_n_times<_Np>([&](auto __i) constexpr {
+	if (__builtin_is_constant_evaluated())
+	  {
+	    for (size_t __i = 0; __i < _Np; ++__i)
+	      __mem[__i] = __v[__i];
+	  }
+	else if constexpr (sizeof(_Up) > 8)
+	  __execute_n_times<_Np>([&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __mem[__i] = __v[__i];
 	  });
 	else if constexpr (is_same_v<_Up, _Tp>)
@@ -1540,9 +1564,10 @@ template <typename _Abi, typename>
 	    using _V = __vector_type_t<_Up, __vsize>;
 	    const array<_V, __stores> __converted
 	      = __convert_all<_V, __stores>(__v);
-	    __execute_n_times<__full_stores>([&](auto __i) constexpr {
-	      _CommonImpl::_S_store(__converted[__i], __mem + __i * __vsize);
-	    });
+	    __execute_n_times<__full_stores>(
+	      [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		_CommonImpl::_S_store(__converted[__i], __mem + __i * __vsize);
+	      });
 	    if constexpr (__full_stores < __stores)
 	      _CommonImpl::template _S_store<(_Np - __full_stores * __vsize)
 					     * sizeof(_Up)>(
@@ -1552,12 +1577,12 @@ template <typename _Abi, typename>
 
     // _S_masked_store_nocvt {{{2
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
-      _S_masked_store_nocvt(_SimdWrapper<_Tp, _Np> __v, _Tp* __mem,
-			    _MaskMember<_Tp> __k)
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
+      _S_masked_store_nocvt(_SimdWrapper<_Tp, _Np> __v, _Tp* __mem, _MaskMember<_Tp> __k)
       {
 	_BitOps::_S_bit_iteration(
-	  _MaskImpl::_S_to_bits(__k), [&](auto __i) constexpr {
+	  _MaskImpl::_S_to_bits(__k),
+	  [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __mem[__i] = __v[__i];
 	  });
       }
@@ -1565,9 +1590,8 @@ template <typename _Abi, typename>
     // _S_masked_store {{{2
     template <typename _TW, typename _TVT = _VectorTraits<_TW>,
 	      typename _Tp = typename _TVT::value_type, typename _Up>
-      static inline void
-      _S_masked_store(const _TW __v, _Up* __mem, const _MaskMember<_Tp> __k)
-	noexcept
+      static constexpr inline void
+      _S_masked_store(const _TW __v, _Up* __mem, const _MaskMember<_Tp> __k) noexcept
       {
 	constexpr size_t _TV_size = _S_size<_Tp>;
 	[[maybe_unused]] const auto __vi = __to_intrin(__v);
@@ -1579,7 +1603,7 @@ template <typename _Abi, typename>
 	    _Up> || (is_integral_v<_Tp> && is_integral_v<_Up> && sizeof(_Tp) == sizeof(_Up)))
 	  {
 	    // bitwise or no conversion, reinterpret:
-	    const _MaskMember<_Up> __kk = [&]() {
+	    const _MaskMember<_Up> __kk = [&]() _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	      if constexpr (__is_bitmask_v<decltype(__k)>)
 		return _MaskMember<_Up>(__k._M_data);
 	      else
@@ -1618,7 +1642,7 @@ template <typename _Abi, typename>
 		constexpr size_t _NParts = _S_full_size<_Tp> / _UW_size;
 		const array<_UV, _NAllStores> __converted
 		  = __convert_all<_UV, _NAllStores>(__v);
-		__execute_n_times<_NFullStores>([&](auto __i) {
+		__execute_n_times<_NFullStores>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  _SuperImpl::_S_masked_store_nocvt(
 		    _UW(__converted[__i]), __mem + __i * _UW_size,
 		    _UAbi::_MaskImpl::template _S_convert<
@@ -1637,10 +1661,10 @@ template <typename _Abi, typename>
 	      }
 	  }
 	else
-	  _BitOps::_S_bit_iteration(
-	    _MaskImpl::_S_to_bits(__k), [&](auto __i) constexpr {
-	      __mem[__i] = static_cast<_Up>(__v[__i]);
-	    });
+	  _BitOps::_S_bit_iteration(_MaskImpl::_S_to_bits(__k),
+				    [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				      __mem[__i] = static_cast<_Up>(__v[__i]);
+				    });
       }
 
     // _S_complement {{{2
@@ -1794,7 +1818,7 @@ template <typename _Abi, typename>
     // reductions {{{2
     template <size_t _Np, size_t... _Is, size_t... _Zeros, typename _Tp,
 	      typename _BinaryOperation>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
       _S_reduce_partial(index_sequence<_Is...>, index_sequence<_Zeros...>,
 			simd<_Tp, _Abi> __x, _BinaryOperation&& __binary_op)
       {
@@ -1824,6 +1848,13 @@ template <typename _Abi, typename>
 	else if constexpr (_Np == 2)
 	  return __binary_op(simd<_Tp, simd_abi::scalar>(__x[0]),
 			     simd<_Tp, simd_abi::scalar>(__x[1]))[0];
+	else if (__builtin_is_constant_evaluated())
+	  {
+	    simd<_Tp, simd_abi::scalar> __acc = __x[0];
+	    for (size_t __i = 1; __i < _Np; ++__i)
+	      __acc = __binary_op(__acc, simd<_Tp, simd_abi::scalar>(__x[__i]));
+	    return __acc[0];
+	  }
 	else if constexpr (_Abi::template _S_is_partial<_Tp>) //{{{
 	  {
 	    [[maybe_unused]] constexpr auto __full_size
@@ -1929,35 +1960,41 @@ template <typename _Abi, typename>
     // frexp, modf and copysign implemented in simd_math.h
 #define _GLIBCXX_SIMD_MATH_FALLBACK(__name)                                    \
     template <typename _Tp, typename... _More>                                 \
-      static _Tp _S_##__name(const _Tp& __x, const _More&... __more)           \
+      static _Tp                                                               \
+      _S_##__name(const _Tp& __x, const _More&... __more)                      \
       {                                                                        \
 	return __generate_vector<_Tp>(                                         \
-	  [&](auto __i) { return __name(__x[__i], __more[__i]...); });         \
+		 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {            \
+		   return __name(__x[__i], __more[__i]...);                    \
+		 });                                                           \
       }
 
 #define _GLIBCXX_SIMD_MATH_FALLBACK_MASKRET(__name)                            \
     template <typename _Tp, typename... _More>                                 \
-      static typename _Tp::mask_type _S_##__name(const _Tp& __x,               \
-						 const _More&... __more)       \
+      static typename _Tp::mask_type                                           \
+      _S_##__name(const _Tp& __x, const _More&... __more)                      \
       {                                                                        \
 	return __generate_vector<_Tp>(                                         \
-	  [&](auto __i) { return __name(__x[__i], __more[__i]...); });         \
-      }
-
-#define _GLIBCXX_SIMD_MATH_FALLBACK_FIXEDRET(_RetTp, __name)                   \
-    template <typename _Tp, typename... _More>                                 \
-      static auto _S_##__name(const _Tp& __x, const _More&... __more)          \
-      {                                                                        \
-	return __fixed_size_storage_t<_RetTp,                                  \
-				      _VectorTraits<_Tp>::_S_partial_width>::  \
-	  _S_generate([&](auto __meta) constexpr {                             \
-	    return __meta._S_generator(                                        \
-	      [&](auto __i) {                                                  \
-		return __name(__x[__meta._S_offset + __i],                     \
-			      __more[__meta._S_offset + __i]...);              \
-	      },                                                               \
-	      static_cast<_RetTp*>(nullptr));                                  \
-	  });                                                                  \
+		 [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {            \
+		   return __name(__x[__i], __more[__i]...);                    \
+		 });                                                           \
+      }
+
+#define _GLIBCXX_SIMD_MATH_FALLBACK_FIXEDRET(_RetTp, __name)                          \
+    template <typename _Tp, typename... _More>                                        \
+      static auto                                                                     \
+      _S_##__name(const _Tp& __x, const _More&... __more)                             \
+      {                                                                               \
+	return __fixed_size_storage_t<_RetTp,                                         \
+				      _VectorTraits<_Tp>::_S_partial_width>::         \
+	  _S_generate([&](auto __meta) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { \
+	    return __meta._S_generator(                                               \
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {                      \
+		return __name(__x[__meta._S_offset + __i],                            \
+			      __more[__meta._S_offset + __i]...);                     \
+	      },                                                                      \
+	      static_cast<_RetTp*>(nullptr));                                         \
+	  });                                                                         \
       }
 
     _GLIBCXX_SIMD_MATH_FALLBACK(acos)
@@ -2010,7 +2047,7 @@ template <typename _Abi, typename>
       _S_remquo(const _Tp __x, const _Tp __y,
 		__fixed_size_storage_t<int, _TVT::_S_partial_width>* __z)
       {
-	return __generate_vector<_Tp>([&](auto __i) {
+	return __generate_vector<_Tp>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  int __tmp;
 	  auto __r = remquo(__x[__i], __y[__i], &__tmp);
 	  __z->_M_set(__i, __tmp);
@@ -2094,22 +2131,22 @@ template <typename _Abi, typename>
 #undef _GLIBCXX_SIMD_MATH_FALLBACK_FIXEDRET
     // _S_abs {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
-    _S_abs(_SimdWrapper<_Tp, _Np> __x) noexcept
-    {
-      // if (__builtin_is_constant_evaluated())
-      //  {
-      //    return __x._M_data < 0 ? -__x._M_data : __x._M_data;
-      //  }
-      if constexpr (is_floating_point_v<_Tp>)
-	// `v < 0 ? -v : v` cannot compile to the efficient implementation of
-	// masking the signbit off because it must consider v == -0
-
-	// ~(-0.) & v would be easy, but breaks with fno-signed-zeros
-	return __and(_S_absmask<__vector_type_t<_Tp, _Np>>, __x._M_data);
-      else
-	return __x._M_data < 0 ? -__x._M_data : __x._M_data;
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _S_abs(_SimdWrapper<_Tp, _Np> __x) noexcept
+      {
+	// if (__builtin_is_constant_evaluated())
+	//  {
+	//    return __x._M_data < 0 ? -__x._M_data : __x._M_data;
+	//  }
+	if constexpr (is_floating_point_v<_Tp>)
+	  // `v < 0 ? -v : v` cannot compile to the efficient implementation of
+	  // masking the signbit off because it must consider v == -0
+
+	  // ~(-0.) & v would be easy, but breaks with fno-signed-zeros
+	  return __and(_S_absmask<__vector_type_t<_Tp, _Np>>, __x._M_data);
+	else
+	  return __x._M_data < 0 ? -__x._M_data : __x._M_data;
+      }
 
     // }}}3
     // _S_plus_minus {{{
@@ -2117,339 +2154,337 @@ template <typename _Abi, typename>
     // - _TV must be __vector_type_t<floating-point type, N>.
     // - _UV must be _TV or floating-point type.
     template <typename _TV, typename _UV>
-    _GLIBCXX_SIMD_INTRINSIC static constexpr _TV _S_plus_minus(_TV __x,
-							       _UV __y) noexcept
-    {
-  #if defined __i386__ && !defined __SSE_MATH__
-      if constexpr (sizeof(__x) == 8)
-	{ // operations on __x would use the FPU
-	  static_assert(is_same_v<_TV, __vector_type_t<float, 2>>);
-	  const auto __x4 = __vector_bitcast<float, 4>(__x);
-	  if constexpr (is_same_v<_TV, _UV>)
-	    return __vector_bitcast<float, 2>(
-	      _S_plus_minus(__x4, __vector_bitcast<float, 4>(__y)));
-	  else
-	    return __vector_bitcast<float, 2>(_S_plus_minus(__x4, __y));
-	}
-  #endif
-  #if !defined __clang__ && __GCC_IEC_559 == 0
-      if (__builtin_is_constant_evaluated()
-	  || (__builtin_constant_p(__x) && __builtin_constant_p(__y)))
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _TV
+      _S_plus_minus(_TV __x, _UV __y) noexcept
+      {
+#if defined __i386__ && !defined __SSE_MATH__
+	if constexpr (sizeof(__x) == 8)
+	  { // operations on __x would use the FPU
+	    static_assert(is_same_v<_TV, __vector_type_t<float, 2>>);
+	    const auto __x4 = __vector_bitcast<float, 4>(__x);
+	    if constexpr (is_same_v<_TV, _UV>)
+	      return __vector_bitcast<float, 2>(
+		       _S_plus_minus(__x4, __vector_bitcast<float, 4>(__y)));
+	    else
+	      return __vector_bitcast<float, 2>(_S_plus_minus(__x4, __y));
+	  }
+#endif
+#if !defined __clang__ && __GCC_IEC_559 == 0
+	if (__builtin_is_constant_evaluated()
+	      || (__builtin_constant_p(__x) && __builtin_constant_p(__y)))
+	  return (__x + __y) - __y;
+	else
+	  return [&] {
+	    __x += __y;
+	    if constexpr(__have_sse)
+	      {
+		if constexpr (sizeof(__x) >= 16)
+		  asm("" : "+x"(__x));
+		else if constexpr (is_same_v<__vector_type_t<float, 2>, _TV>)
+		  asm("" : "+x"(__x[0]), "+x"(__x[1]));
+		else
+		  __assert_unreachable<_TV>();
+	      }
+	    else if constexpr(__have_neon)
+	      asm("" : "+w"(__x));
+	    else if constexpr (__have_power_vmx)
+	      {
+		if constexpr (is_same_v<__vector_type_t<float, 2>, _TV>)
+		  asm("" : "+fgr"(__x[0]), "+fgr"(__x[1]));
+		else
+		  asm("" : "+v"(__x));
+	      }
+	    else
+	      asm("" : "+g"(__x));
+	    return __x - __y;
+	  }();
+#else
 	return (__x + __y) - __y;
-      else
-	return [&] {
-	  __x += __y;
-	  if constexpr(__have_sse)
-	    {
-	      if constexpr (sizeof(__x) >= 16)
-		asm("" : "+x"(__x));
-	      else if constexpr (is_same_v<__vector_type_t<float, 2>, _TV>)
-		asm("" : "+x"(__x[0]), "+x"(__x[1]));
-	      else
-		__assert_unreachable<_TV>();
-	    }
-	  else if constexpr(__have_neon)
-	    asm("" : "+w"(__x));
-	  else if constexpr (__have_power_vmx)
-	    {
-	      if constexpr (is_same_v<__vector_type_t<float, 2>, _TV>)
-		asm("" : "+fgr"(__x[0]), "+fgr"(__x[1]));
-	      else
-		asm("" : "+v"(__x));
-	    }
-	  else
-	    asm("" : "+g"(__x));
-	  return __x - __y;
-	}();
-  #else
-      return (__x + __y) - __y;
-  #endif
-    }
+#endif
+      }
 
     // }}}
     // _S_nearbyint {{{3
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_nearbyint(_Tp __x_) noexcept
-    {
-      using value_type = typename _TVT::value_type;
-      using _V = typename _TVT::type;
-      const _V __x = __x_;
-      const _V __absx = __and(__x, _S_absmask<_V>);
-      static_assert(__CHAR_BIT__ * sizeof(1ull) >= __digits_v<value_type>);
-      _GLIBCXX_SIMD_USE_CONSTEXPR _V __shifter_abs
-	= _V() + (1ull << (__digits_v<value_type> - 1));
-      const _V __shifter = __or(__and(_S_signmask<_V>, __x), __shifter_abs);
-      const _V __shifted = _S_plus_minus(__x, __shifter);
-      return __absx < __shifter_abs ? __shifted : __x;
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_nearbyint(_Tp __x_) noexcept
+      {
+	using value_type = typename _TVT::value_type;
+	using _V = typename _TVT::type;
+	const _V __x = __x_;
+	const _V __absx = __and(__x, _S_absmask<_V>);
+	static_assert(__CHAR_BIT__ * sizeof(1ull) >= __digits_v<value_type>);
+	_GLIBCXX_SIMD_USE_CONSTEXPR _V __shifter_abs
+	  = _V() + (1ull << (__digits_v<value_type> - 1));
+	const _V __shifter = __or(__and(_S_signmask<_V>, __x), __shifter_abs);
+	const _V __shifted = _S_plus_minus(__x, __shifter);
+	return __absx < __shifter_abs ? __shifted : __x;
+      }
 
     // _S_rint {{{3
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_rint(_Tp __x) noexcept
-    {
-      return _SuperImpl::_S_nearbyint(__x);
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_rint(_Tp __x) noexcept
+      { return _SuperImpl::_S_nearbyint(__x); }
 
     // _S_trunc {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
-    _S_trunc(_SimdWrapper<_Tp, _Np> __x)
-    {
-      using _V = __vector_type_t<_Tp, _Np>;
-      const _V __absx = __and(__x._M_data, _S_absmask<_V>);
-      static_assert(__CHAR_BIT__ * sizeof(1ull) >= __digits_v<_Tp>);
-      constexpr _Tp __shifter = 1ull << (__digits_v<_Tp> - 1);
-      _V __truncated = _S_plus_minus(__absx, __shifter);
-      __truncated -= __truncated > __absx ? _V() + 1 : _V();
-      return __absx < __shifter ? __or(__xor(__absx, __x._M_data), __truncated)
-				: __x._M_data;
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _S_trunc(_SimdWrapper<_Tp, _Np> __x)
+      {
+	using _V = __vector_type_t<_Tp, _Np>;
+	const _V __absx = __and(__x._M_data, _S_absmask<_V>);
+	static_assert(__CHAR_BIT__ * sizeof(1ull) >= __digits_v<_Tp>);
+	constexpr _Tp __shifter = 1ull << (__digits_v<_Tp> - 1);
+	_V __truncated = _S_plus_minus(__absx, __shifter);
+	__truncated -= __truncated > __absx ? _V() + 1 : _V();
+	return __absx < __shifter ? __or(__xor(__absx, __x._M_data), __truncated)
+				  : __x._M_data;
+      }
 
     // _S_round {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
-    _S_round(_SimdWrapper<_Tp, _Np> __x)
-    {
-      const auto __abs_x = _SuperImpl::_S_abs(__x);
-      const auto __t_abs = _SuperImpl::_S_trunc(__abs_x)._M_data;
-      const auto __r_abs // round(abs(x)) =
-	= __t_abs + (__abs_x._M_data - __t_abs >= _Tp(.5) ? _Tp(1) : 0);
-      return __or(__xor(__abs_x._M_data, __x._M_data), __r_abs);
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _S_round(_SimdWrapper<_Tp, _Np> __x)
+      {
+	const auto __abs_x = _SuperImpl::_S_abs(__x);
+	const auto __t_abs = _SuperImpl::_S_trunc(__abs_x)._M_data;
+	const auto __r_abs // round(abs(x)) =
+	  = __t_abs + (__abs_x._M_data - __t_abs >= _Tp(.5) ? _Tp(1) : 0);
+	return __or(__xor(__abs_x._M_data, __x._M_data), __r_abs);
+      }
 
     // _S_floor {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
-    _S_floor(_SimdWrapper<_Tp, _Np> __x)
-    {
-      const auto __y = _SuperImpl::_S_trunc(__x)._M_data;
-      const auto __negative_input
-	= __vector_bitcast<_Tp>(__x._M_data < __vector_broadcast<_Np, _Tp>(0));
-      const auto __mask
-	= __andnot(__vector_bitcast<_Tp>(__y == __x._M_data), __negative_input);
-      return __or(__andnot(__mask, __y),
-		  __and(__mask, __y - __vector_broadcast<_Np, _Tp>(1)));
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _S_floor(_SimdWrapper<_Tp, _Np> __x)
+      {
+	const auto __y = _SuperImpl::_S_trunc(__x)._M_data;
+	const auto __negative_input
+	  = __vector_bitcast<_Tp>(__x._M_data < __vector_broadcast<_Np, _Tp>(0));
+	const auto __mask
+	  = __andnot(__vector_bitcast<_Tp>(__y == __x._M_data), __negative_input);
+	return __or(__andnot(__mask, __y),
+		    __and(__mask, __y - __vector_broadcast<_Np, _Tp>(1)));
+      }
 
     // _S_ceil {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
-    _S_ceil(_SimdWrapper<_Tp, _Np> __x)
-    {
-      const auto __y = _SuperImpl::_S_trunc(__x)._M_data;
-      const auto __negative_input
-	= __vector_bitcast<_Tp>(__x._M_data < __vector_broadcast<_Np, _Tp>(0));
-      const auto __inv_mask
-	= __or(__vector_bitcast<_Tp>(__y == __x._M_data), __negative_input);
-      return __or(__and(__inv_mask, __y),
-		  __andnot(__inv_mask, __y + __vector_broadcast<_Np, _Tp>(1)));
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _S_ceil(_SimdWrapper<_Tp, _Np> __x)
+      {
+	const auto __y = _SuperImpl::_S_trunc(__x)._M_data;
+	const auto __negative_input
+	  = __vector_bitcast<_Tp>(__x._M_data < __vector_broadcast<_Np, _Tp>(0));
+	const auto __inv_mask
+	  = __or(__vector_bitcast<_Tp>(__y == __x._M_data), __negative_input);
+	return __or(__and(__inv_mask, __y),
+		    __andnot(__inv_mask, __y + __vector_broadcast<_Np, _Tp>(1)));
+      }
 
     // _S_isnan {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
-    _S_isnan([[maybe_unused]] _SimdWrapper<_Tp, _Np> __x)
-    {
-  #if __FINITE_MATH_ONLY__
-      return {}; // false
-  #elif !defined __SUPPORT_SNAN__
-      return ~(__x._M_data == __x._M_data);
-  #elif defined __STDC_IEC_559__
-      using _Ip = __int_for_sizeof_t<_Tp>;
-      const auto __absn = __vector_bitcast<_Ip>(_SuperImpl::_S_abs(__x));
-      const auto __infn
-	= __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__infinity_v<_Tp>));
-      return __infn < __absn;
-  #else
-  #error "Not implemented: how to support SNaN but non-IEC559 floating-point?"
-  #endif
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
+      _S_isnan([[maybe_unused]] _SimdWrapper<_Tp, _Np> __x)
+      {
+#if __FINITE_MATH_ONLY__
+	return {}; // false
+#elif !defined __SUPPORT_SNAN__
+	return ~(__x._M_data == __x._M_data);
+#elif defined __STDC_IEC_559__
+	using _Ip = __int_for_sizeof_t<_Tp>;
+	const auto __absn = __vector_bitcast<_Ip>(_SuperImpl::_S_abs(__x));
+	const auto __infn
+	  = __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__infinity_v<_Tp>));
+	return __infn < __absn;
+#else
+#error "Not implemented: how to support SNaN but non-IEC559 floating-point?"
+#endif
+      }
 
     // _S_isfinite {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
-    _S_isfinite([[maybe_unused]] _SimdWrapper<_Tp, _Np> __x)
-    {
-  #if __FINITE_MATH_ONLY__
-      using _UV = typename _MaskMember<_Tp>::_BuiltinType;
-      _GLIBCXX_SIMD_USE_CONSTEXPR _UV __alltrue = ~_UV();
-      return __alltrue;
-  #else
-      // if all exponent bits are set, __x is either inf or NaN
-      using _Ip = __int_for_sizeof_t<_Tp>;
-      const auto __absn = __vector_bitcast<_Ip>(_SuperImpl::_S_abs(__x));
-      const auto __maxn
-	= __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__finite_max_v<_Tp>));
-      return __absn <= __maxn;
-  #endif
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
+      _S_isfinite([[maybe_unused]] _SimdWrapper<_Tp, _Np> __x)
+      {
+#if __FINITE_MATH_ONLY__
+	using _UV = typename _MaskMember<_Tp>::_BuiltinType;
+	_GLIBCXX_SIMD_USE_CONSTEXPR _UV __alltrue = ~_UV();
+	return __alltrue;
+#else
+	// if all exponent bits are set, __x is either inf or NaN
+	using _Ip = __int_for_sizeof_t<_Tp>;
+	const auto __absn = __vector_bitcast<_Ip>(_SuperImpl::_S_abs(__x));
+	const auto __maxn
+	  = __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__finite_max_v<_Tp>));
+	return __absn <= __maxn;
+#endif
+      }
 
     // _S_isunordered {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
-    _S_isunordered(_SimdWrapper<_Tp, _Np> __x, _SimdWrapper<_Tp, _Np> __y)
-    {
-      return __or(_S_isnan(__x), _S_isnan(__y));
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
+      _S_isunordered(_SimdWrapper<_Tp, _Np> __x, _SimdWrapper<_Tp, _Np> __y)
+      { return __or(_S_isnan(__x), _S_isnan(__y)); }
 
     // _S_signbit {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
-    _S_signbit(_SimdWrapper<_Tp, _Np> __x)
-    {
-      using _Ip = __int_for_sizeof_t<_Tp>;
-      return __vector_bitcast<_Ip>(__x) < 0;
-      // Arithmetic right shift (SRA) would also work (instead of compare), but
-      // 64-bit SRA isn't available on x86 before AVX512. And in general,
-      // compares are more likely to be efficient than SRA.
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
+      _S_signbit(_SimdWrapper<_Tp, _Np> __x)
+      {
+	using _Ip = __int_for_sizeof_t<_Tp>;
+	return __vector_bitcast<_Ip>(__x) < 0;
+	// Arithmetic right shift (SRA) would also work (instead of compare), but
+	// 64-bit SRA isn't available on x86 before AVX512. And in general,
+	// compares are more likely to be efficient than SRA.
+      }
 
     // _S_isinf {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
-    _S_isinf([[maybe_unused]] _SimdWrapper<_Tp, _Np> __x)
-    {
-  #if __FINITE_MATH_ONLY__
-      return {}; // false
-  #else
-      return _SuperImpl::template _S_equal_to<_Tp, _Np>(_SuperImpl::_S_abs(__x),
-							__vector_broadcast<_Np>(
-							  __infinity_v<_Tp>));
-      // alternative:
-      // compare to inf using the corresponding integer type
-      /*
-	 return
-	 __vector_bitcast<_Tp>(__vector_bitcast<__int_for_sizeof_t<_Tp>>(
-			       _S_abs(__x)._M_data)
-	 ==
-	 __vector_bitcast<__int_for_sizeof_t<_Tp>>(__vector_broadcast<_Np>(
-	 __infinity_v<_Tp>)));
-	 */
-  #endif
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
+      _S_isinf([[maybe_unused]] _SimdWrapper<_Tp, _Np> __x)
+      {
+#if __FINITE_MATH_ONLY__
+	return {}; // false
+#else
+	return _SuperImpl::template _S_equal_to<_Tp, _Np>(_SuperImpl::_S_abs(__x),
+							  __vector_broadcast<_Np>(
+							    __infinity_v<_Tp>));
+	// alternative:
+	// compare to inf using the corresponding integer type
+	/*
+	   return
+	   __vector_bitcast<_Tp>(__vector_bitcast<__int_for_sizeof_t<_Tp>>(
+				 _S_abs(__x)._M_data)
+	   ==
+	   __vector_bitcast<__int_for_sizeof_t<_Tp>>(__vector_broadcast<_Np>(
+	   __infinity_v<_Tp>)));
+	   */
+#endif
+      }
 
     // _S_isnormal {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
-    _S_isnormal(_SimdWrapper<_Tp, _Np> __x)
-    {
-      using _Ip = __int_for_sizeof_t<_Tp>;
-      const auto __absn = __vector_bitcast<_Ip>(_SuperImpl::_S_abs(__x));
-      const auto __minn
-	= __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__norm_min_v<_Tp>));
-  #if __FINITE_MATH_ONLY__
-      return __absn >= __minn;
-  #else
-      const auto __maxn
-	= __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__finite_max_v<_Tp>));
-      return __minn <= __absn && __absn <= __maxn;
-  #endif
-    }
+      _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
+      _S_isnormal(_SimdWrapper<_Tp, _Np> __x)
+      {
+	using _Ip = __int_for_sizeof_t<_Tp>;
+	const auto __absn = __vector_bitcast<_Ip>(_SuperImpl::_S_abs(__x));
+	const auto __minn
+	  = __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__norm_min_v<_Tp>));
+#if __FINITE_MATH_ONLY__
+	return __absn >= __minn;
+#else
+	const auto __maxn
+	  = __vector_bitcast<_Ip>(__vector_broadcast<_Np>(__finite_max_v<_Tp>));
+	return __minn <= __absn && __absn <= __maxn;
+#endif
+      }
 
     // _S_fpclassify {{{3
     template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static __fixed_size_storage_t<int, _Np>
-    _S_fpclassify(_SimdWrapper<_Tp, _Np> __x)
-    {
-      using _I = __int_for_sizeof_t<_Tp>;
-      const auto __xn
-	= __vector_bitcast<_I>(__to_intrin(_SuperImpl::_S_abs(__x)));
-      constexpr size_t _NI = sizeof(__xn) / sizeof(_I);
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __minn
-	= __vector_bitcast<_I>(__vector_broadcast<_NI>(__norm_min_v<_Tp>));
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __infn
-	= __vector_bitcast<_I>(__vector_broadcast<_NI>(__infinity_v<_Tp>));
-
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_normal
-	= __vector_broadcast<_NI, _I>(FP_NORMAL);
-  #if !__FINITE_MATH_ONLY__
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_nan
-	= __vector_broadcast<_NI, _I>(FP_NAN);
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_infinite
-	= __vector_broadcast<_NI, _I>(FP_INFINITE);
-  #endif
-  #ifndef __FAST_MATH__
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_subnormal
-	= __vector_broadcast<_NI, _I>(FP_SUBNORMAL);
-  #endif
-      _GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_zero
-	= __vector_broadcast<_NI, _I>(FP_ZERO);
+      _GLIBCXX_SIMD_INTRINSIC static __fixed_size_storage_t<int, _Np>
+      _S_fpclassify(_SimdWrapper<_Tp, _Np> __x)
+      {
+	using _I = __int_for_sizeof_t<_Tp>;
+	const auto __xn
+	  = __vector_bitcast<_I>(__to_intrin(_SuperImpl::_S_abs(__x)));
+	constexpr size_t _NI = sizeof(__xn) / sizeof(_I);
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __minn
+	  = __vector_bitcast<_I>(__vector_broadcast<_NI>(__norm_min_v<_Tp>));
+
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_normal
+	  = __vector_broadcast<_NI, _I>(FP_NORMAL);
+#if !__FINITE_MATH_ONLY__
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __infn
+	  = __vector_bitcast<_I>(__vector_broadcast<_NI>(__infinity_v<_Tp>));
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_nan
+	  = __vector_broadcast<_NI, _I>(FP_NAN);
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_infinite
+	  = __vector_broadcast<_NI, _I>(FP_INFINITE);
+#endif
+#ifndef __FAST_MATH__
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_subnormal
+	  = __vector_broadcast<_NI, _I>(FP_SUBNORMAL);
+#endif
+	_GLIBCXX_SIMD_USE_CONSTEXPR auto __fp_zero
+	  = __vector_broadcast<_NI, _I>(FP_ZERO);
 
-      __vector_type_t<_I, _NI>
-	__tmp = __xn < __minn
+	__vector_type_t<_I, _NI>
+	  __tmp = __xn < __minn
   #ifdef __FAST_MATH__
-		  ? __fp_zero
+		    ? __fp_zero
   #else
-		  ? (__xn == 0 ? __fp_zero : __fp_subnormal)
+		    ? (__xn == 0 ? __fp_zero : __fp_subnormal)
   #endif
   #if __FINITE_MATH_ONLY__
-		  : __fp_normal;
+		    : __fp_normal;
   #else
-		  : (__xn < __infn ? __fp_normal
-				   : (__xn == __infn ? __fp_infinite : __fp_nan));
+		    : (__xn < __infn ? __fp_normal
+				     : (__xn == __infn ? __fp_infinite : __fp_nan));
   #endif
 
-      if constexpr (sizeof(_I) == sizeof(int))
-	{
-	  using _FixedInt = __fixed_size_storage_t<int, _Np>;
-	  const auto __as_int = __vector_bitcast<int, _Np>(__tmp);
-	  if constexpr (_FixedInt::_S_tuple_size == 1)
-	    return {__as_int};
-	  else if constexpr (_FixedInt::_S_tuple_size == 2
-			     && is_same_v<
-			       typename _FixedInt::_SecondType::_FirstAbi,
-			       simd_abi::scalar>)
-	    return {__extract<0, 2>(__as_int), __as_int[_Np - 1]};
-	  else if constexpr (_FixedInt::_S_tuple_size == 2)
-	    return {__extract<0, 2>(__as_int),
-		    __auto_bitcast(__extract<1, 2>(__as_int))};
-	  else
-	    __assert_unreachable<_Tp>();
-	}
-      else if constexpr (_Np == 2 && sizeof(_I) == 8
-			 && __fixed_size_storage_t<int, _Np>::_S_tuple_size == 2)
-	{
-	  const auto __aslong = __vector_bitcast<_LLong>(__tmp);
-	  return {int(__aslong[0]), {int(__aslong[1])}};
-	}
-  #if _GLIBCXX_SIMD_X86INTRIN
-      else if constexpr (sizeof(_Tp) == 8 && sizeof(__tmp) == 32
-			 && __fixed_size_storage_t<int, _Np>::_S_tuple_size == 1)
-	return {_mm_packs_epi32(__to_intrin(__lo128(__tmp)),
-				__to_intrin(__hi128(__tmp)))};
-      else if constexpr (sizeof(_Tp) == 8 && sizeof(__tmp) == 64
-			 && __fixed_size_storage_t<int, _Np>::_S_tuple_size == 1)
-	return {_mm512_cvtepi64_epi32(__to_intrin(__tmp))};
-  #endif // _GLIBCXX_SIMD_X86INTRIN
-      else if constexpr (__fixed_size_storage_t<int, _Np>::_S_tuple_size == 1)
-	return {__call_with_subscripts<_Np>(__vector_bitcast<_LLong>(__tmp),
-					    [](auto... __l) {
-					      return __make_wrapper<int>(__l...);
-					    })};
-      else
-	__assert_unreachable<_Tp>();
-    }
+	if constexpr (sizeof(_I) == sizeof(int))
+	  {
+	    using _FixedInt = __fixed_size_storage_t<int, _Np>;
+	    const auto __as_int = __vector_bitcast<int, _Np>(__tmp);
+	    if constexpr (_FixedInt::_S_tuple_size == 1)
+	      return {__as_int};
+	    else if constexpr (_FixedInt::_S_tuple_size == 2
+				 && is_same_v<
+				      typename _FixedInt::_SecondType::_FirstAbi,
+				      simd_abi::scalar>)
+	      return {__extract<0, 2>(__as_int), __as_int[_Np - 1]};
+	    else if constexpr (_FixedInt::_S_tuple_size == 2)
+	      return {__extract<0, 2>(__as_int),
+		      __auto_bitcast(__extract<1, 2>(__as_int))};
+	    else
+	      __assert_unreachable<_Tp>();
+	  }
+	else if constexpr (_Np == 2 && sizeof(_I) == 8
+			     && __fixed_size_storage_t<int, _Np>::_S_tuple_size == 2)
+	  {
+	    const auto __aslong = __vector_bitcast<_LLong>(__tmp);
+	    return {int(__aslong[0]), {int(__aslong[1])}};
+	  }
+#if _GLIBCXX_SIMD_X86INTRIN
+	else if constexpr (sizeof(_Tp) == 8 && sizeof(__tmp) == 32
+			     && __fixed_size_storage_t<int, _Np>::_S_tuple_size == 1)
+	  return {_mm_packs_epi32(__to_intrin(__lo128(__tmp)),
+				  __to_intrin(__hi128(__tmp)))};
+	else if constexpr (sizeof(_Tp) == 8 && sizeof(__tmp) == 64
+			     && __fixed_size_storage_t<int, _Np>::_S_tuple_size == 1)
+	  return {_mm512_cvtepi64_epi32(__to_intrin(__tmp))};
+#endif // _GLIBCXX_SIMD_X86INTRIN
+	else if constexpr (__fixed_size_storage_t<int, _Np>::_S_tuple_size == 1)
+	  return {__call_with_subscripts<_Np>(__vector_bitcast<_LLong>(__tmp),
+					      [](auto... __l) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+						return __make_wrapper<int>(__l...);
+					      })};
+	else
+	  __assert_unreachable<_Tp>();
+      }
 
     // _S_increment & _S_decrement{{{2
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_increment(_SimdWrapper<_Tp, _Np>& __x)
       { __x = __x._M_data + 1; }
 
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_decrement(_SimdWrapper<_Tp, _Np>& __x)
       { __x = __x._M_data - 1; }
 
     // smart_reference access {{{2
     template <typename _Tp, size_t _Np, typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC constexpr static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_set(_SimdWrapper<_Tp, _Np>& __v, int __i, _Up&& __x) noexcept
       { __v._M_set(__i, static_cast<_Up&&>(__x)); }
 
     // _S_masked_assign{{{2
     template <typename _Tp, typename _K, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_masked_assign(_SimdWrapper<_K, _Np> __k, _SimdWrapper<_Tp, _Np>& __lhs,
 		       __type_identity_t<_SimdWrapper<_Tp, _Np>> __rhs)
       {
@@ -2462,7 +2497,7 @@ template <typename _Abi, typename>
       }
 
     template <typename _Tp, typename _K, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_masked_assign(_SimdWrapper<_K, _Np> __k, _SimdWrapper<_Tp, _Np>& __lhs,
 		       __type_identity_t<_Tp> __rhs)
       {
@@ -2490,7 +2525,7 @@ template <typename _Abi, typename>
 
     // _S_masked_cassign {{{2
     template <typename _Op, typename _Tp, typename _K, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_masked_cassign(const _SimdWrapper<_K, _Np> __k,
 			_SimdWrapper<_Tp, _Np>& __lhs,
 			const __type_identity_t<_SimdWrapper<_Tp, _Np>> __rhs,
@@ -2506,7 +2541,7 @@ template <typename _Abi, typename>
       }
 
     template <typename _Op, typename _Tp, typename _K, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_masked_cassign(const _SimdWrapper<_K, _Np> __k,
 			_SimdWrapper<_Tp, _Np>& __lhs,
 			const __type_identity_t<_Tp> __rhs, _Op __op)
@@ -2515,7 +2550,7 @@ template <typename _Abi, typename>
     // _S_masked_unary {{{2
     template <template <typename> class _Op, typename _Tp, typename _K,
 	      size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
       _S_masked_unary(const _SimdWrapper<_K, _Np> __k,
 		      const _SimdWrapper<_Tp, _Np> __v)
       {
@@ -2525,8 +2560,31 @@ template <typename _Abi, typename>
 	_Op<decltype(__vv)> __op;
 	if (__k._M_is_constprop_all_of())
 	  return __data(__op(__vv));
-	else
-	  return _CommonImpl::_S_blend(__k, __v, __data(__op(__vv)));
+	else if constexpr (is_same_v<_Op<void>, __increment<void>>)
+	  {
+	    static_assert(not std::is_same_v<_K, bool>);
+	    if constexpr (is_integral_v<_Tp>)
+	      // Take a shortcut knowing that __k is an integer vector with values -1 or 0.
+	      return __v._M_data - __vector_bitcast<_Tp>(__k._M_data);
+	    else if constexpr (not __have_avx2)
+	      return __v._M_data
+		       + __vector_bitcast<_Tp>(__k._M_data & __builtin_bit_cast(
+							       _K, _Tp(1)));
+	    // starting with AVX2 it is more efficient to blend after add
+	  }
+	else if constexpr (is_same_v<_Op<void>, __decrement<void>>)
+	  {
+	    static_assert(not std::is_same_v<_K, bool>);
+	    if constexpr (is_integral_v<_Tp>)
+	      // Take a shortcut knowing that __k is an integer vector with values -1 or 0.
+	      return __v._M_data + __vector_bitcast<_Tp>(__k._M_data);
+	    else if constexpr (not __have_avx2)
+	      return __v._M_data
+		       - __vector_bitcast<_Tp>(__k._M_data & __builtin_bit_cast(
+							       _K, _Tp(1)));
+	    // starting with AVX2 it is more efficient to blend after sub
+	  }
+	return _CommonImpl::_S_blend(__k, __v, __data(__op(__vv)));
       }
 
     //}}}2
@@ -2554,13 +2612,13 @@ struct _MaskImplBuiltinMixin
     _S_to_maskvector(_BitMask<_Np, _Sanitized> __x)
     {
       static_assert(is_same_v<_Up, __int_for_sizeof_t<_Up>>);
-      return __generate_vector<__vector_type_t<_Up, _ToN>>([&](
-	auto __i) constexpr {
-	if constexpr (__i < _Np)
-	  return __x[__i] ? ~_Up() : _Up();
-	else
-	  return _Up();
-      });
+      return __generate_vector<__vector_type_t<_Up, _ToN>>(
+	       [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		 if constexpr (__i < _Np)
+		   return __x[__i] ? ~_Up() : _Up();
+		 else
+		   return _Up();
+	       });
     }
 
   template <typename _Up, size_t _UpN = 0, typename _Tp, size_t _Np,
@@ -2601,13 +2659,13 @@ struct _MaskImplBuiltinMixin
 	  -1, -1, -1, -1, -1>(__y); else
 	  */
 	  {
-	    return __generate_vector<__vector_type_t<_Up, _ToN>>([&](
-	      auto __i) constexpr {
-	      if constexpr (__i < _Np)
-		return _Up(__x[__i.value]);
-	      else
-		return _Up();
-	    });
+	    return __generate_vector<__vector_type_t<_Up, _ToN>>(
+		     [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		       if constexpr (__i < _Np)
+			 return _Up(__x[__i.value]);
+		       else
+			 return _Up();
+		     });
 	  }
 	}
     }
@@ -2625,7 +2683,9 @@ struct _MaskImplBuiltinMixin
 	= __vector_bitcast<_Up>(__x) >> (sizeof(_Up) * __CHAR_BIT__ - 1);
       _ULLong __r = 0;
       __execute_n_times<_Np>(
-	[&](auto __i) { __r |= _ULLong(__bools[__i.value]) << __i; });
+	[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	  __r |= _ULLong(__bools[__i.value]) << __i;
+	});
       return __r;
     }
 
@@ -2657,10 +2717,7 @@ template <typename _Abi, typename>
     template <typename _Tp>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember<_Tp>
       _S_broadcast(bool __x)
-      {
-	return __x ? _Abi::template _S_implicit_mask<_Tp>()
-		   : _MaskMember<_Tp>();
-      }
+      { return __x ? _Abi::template _S_implicit_mask<_Tp>() : _MaskMember<_Tp>(); }
 
     // }}}
     // _S_load {{{
@@ -2669,17 +2726,18 @@ template <typename _Abi, typename>
       _S_load(const bool* __mem)
       {
 	using _I = __int_for_sizeof_t<_Tp>;
-	if constexpr (sizeof(_Tp) == sizeof(bool))
-	  {
-	    const auto __bools
-	      = _CommonImpl::template _S_load<_I, _S_size<_Tp>>(__mem);
-	    // bool is {0, 1}, everything else is UB
-	    return __bools > 0;
-	  }
-	else
-	  return __generate_vector<_I, _S_size<_Tp>>([&](auto __i) constexpr {
-	    return __mem[__i] ? ~_I() : _I();
-	  });
+	if (not __builtin_is_constant_evaluated())
+	  if constexpr (sizeof(_Tp) == sizeof(bool))
+	    {
+	      const auto __bools
+		= _CommonImpl::template _S_load<_I, _S_size<_Tp>>(__mem);
+	      // bool is {0, 1}, everything else is UB
+	      return __bools > 0;
+	    }
+	return __generate_vector<_I, _S_size<_Tp>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __mem[__i] ? ~_I() : _I();
+		 });
       }
 
     // }}}
@@ -2752,7 +2810,7 @@ template <typename _Abi, typename>
 	// AVX(2) has 32/64 bit maskload, but nothing at 8 bit granularity
 	auto __tmp = __wrapper_bitcast<__int_for_sizeof_t<_Tp>>(__merge);
 	_BitOps::_S_bit_iteration(_SuperImpl::_S_to_bits(__mask),
-				  [&](auto __i) {
+				  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 				    __tmp._M_set(__i, -__mem[__i]);
 				  });
 	__merge = __wrapper_bitcast<_Tp>(__tmp);
@@ -2761,10 +2819,10 @@ template <typename _Abi, typename>
 
     // _S_store {{{2
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void _S_store(_SimdWrapper<_Tp, _Np> __v,
-						   bool* __mem) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
+      _S_store(_SimdWrapper<_Tp, _Np> __v, bool* __mem) noexcept
       {
-	__execute_n_times<_Np>([&](auto __i) constexpr {
+	__execute_n_times<_Np>([&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  __mem[__i] = __v[__i];
 	});
       }
@@ -2775,31 +2833,27 @@ template <typename _Abi, typename>
       _S_masked_store(const _SimdWrapper<_Tp, _Np> __v, bool* __mem,
 		      const _SimdWrapper<_Tp, _Np> __k) noexcept
       {
-	_BitOps::_S_bit_iteration(
-	  _SuperImpl::_S_to_bits(__k), [&](auto __i) constexpr {
-	    __mem[__i] = __v[__i];
-	  });
+	_BitOps::_S_bit_iteration(_SuperImpl::_S_to_bits(__k),
+				  [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				    __mem[__i] = __v[__i];
+				  });
       }
 
     // _S_from_bitmask{{{2
     template <size_t _Np, typename _Tp>
       _GLIBCXX_SIMD_INTRINSIC static _MaskMember<_Tp>
       _S_from_bitmask(_SanitizedBitMask<_Np> __bits, _TypeTag<_Tp>)
-      {
-	return _SuperImpl::template _S_to_maskvector<_Tp, _S_size<_Tp>>(__bits);
-      }
+      { return _SuperImpl::template _S_to_maskvector<_Tp, _S_size<_Tp>>(__bits); }
 
     // logical and bitwise operators {{{2
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_logical_and(const _SimdWrapper<_Tp, _Np>& __x,
-		     const _SimdWrapper<_Tp, _Np>& __y)
+      _S_logical_and(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       { return __and(__x._M_data, __y._M_data); }
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_logical_or(const _SimdWrapper<_Tp, _Np>& __x,
-		    const _SimdWrapper<_Tp, _Np>& __y)
+      _S_logical_or(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       { return __or(__x._M_data, __y._M_data); }
 
     template <typename _Tp, size_t _Np>
@@ -2815,26 +2869,23 @@ template <typename _Abi, typename>
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_bit_and(const _SimdWrapper<_Tp, _Np>& __x,
-		 const _SimdWrapper<_Tp, _Np>& __y)
+      _S_bit_and(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       { return __and(__x._M_data, __y._M_data); }
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_bit_or(const _SimdWrapper<_Tp, _Np>& __x,
-		const _SimdWrapper<_Tp, _Np>& __y)
+      _S_bit_or(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       { return __or(__x._M_data, __y._M_data); }
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_bit_xor(const _SimdWrapper<_Tp, _Np>& __x,
-		 const _SimdWrapper<_Tp, _Np>& __y)
+      _S_bit_xor(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       { return __xor(__x._M_data, __y._M_data); }
 
     // smart_reference access {{{2
     template <typename _Tp, size_t _Np>
-      static constexpr void _S_set(_SimdWrapper<_Tp, _Np>& __k, int __i,
-				   bool __x) noexcept
+      static constexpr void
+      _S_set(_SimdWrapper<_Tp, _Np>& __k, int __i, bool __x) noexcept
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  __k._M_set(__i, __x);
@@ -2845,7 +2896,7 @@ template <typename _Abi, typename>
 	      {
 		__k = __generate_from_n_evaluations<_Np,
 						    __vector_type_t<_Tp, _Np>>(
-		  [&](auto __j) {
+		  [&](auto __j) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		    if (__i == static_cast<int>(__j))
 		      return _Tp(-__x);
 		    else
@@ -2860,15 +2911,13 @@ template <typename _Abi, typename>
     // _S_masked_assign{{{2
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static void
-      _S_masked_assign(_SimdWrapper<_Tp, _Np> __k,
-		       _SimdWrapper<_Tp, _Np>& __lhs,
+      _S_masked_assign(_SimdWrapper<_Tp, _Np> __k, _SimdWrapper<_Tp, _Np>& __lhs,
 		       __type_identity_t<_SimdWrapper<_Tp, _Np>> __rhs)
       { __lhs = _CommonImpl::_S_blend(__k, __lhs, __rhs); }
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static void
-      _S_masked_assign(_SimdWrapper<_Tp, _Np> __k,
-		       _SimdWrapper<_Tp, _Np>& __lhs, bool __rhs)
+      _S_masked_assign(_SimdWrapper<_Tp, _Np> __k, _SimdWrapper<_Tp, _Np>& __lhs, bool __rhs)
       {
 	if (__builtin_constant_p(__rhs))
 	  {
@@ -2890,7 +2939,8 @@ template <typename _Abi, typename>
       {
 	return __call_with_subscripts(
 	  __data(__k), make_index_sequence<_S_size<_Tp>>(),
-	  [](const auto... __ent) constexpr { return (... && !(__ent == 0)); });
+	  [](const auto... __ent) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+	  { return (... && !(__ent == 0)); });
       }
 
     // }}}
@@ -2901,7 +2951,8 @@ template <typename _Abi, typename>
       {
 	return __call_with_subscripts(
 	  __data(__k), make_index_sequence<_S_size<_Tp>>(),
-	  [](const auto... __ent) constexpr { return (... || !(__ent == 0)); });
+	  [](const auto... __ent) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+	  { return (... || !(__ent == 0)); });
       }
 
     // }}}
@@ -2912,7 +2963,8 @@ template <typename _Abi, typename>
       {
 	return __call_with_subscripts(
 	  __data(__k), make_index_sequence<_S_size<_Tp>>(),
-	  [](const auto... __ent) constexpr { return (... && (__ent == 0)); });
+	  [](const auto... __ent) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+	  { return (... && (__ent == 0)); });
       }
 
     // }}}
@@ -2945,20 +2997,14 @@ template <typename _Abi, typename>
     template <typename _Tp>
       _GLIBCXX_SIMD_INTRINSIC static int
       _S_find_first_set(simd_mask<_Tp, _Abi> __k)
-      {
-	return std::__countr_zero(
-	  _SuperImpl::_S_to_bits(__data(__k))._M_to_bits());
-      }
+      { return std::__countr_zero(_SuperImpl::_S_to_bits(__data(__k))._M_to_bits()); }
 
     // }}}
     // _S_find_last_set {{{
     template <typename _Tp>
       _GLIBCXX_SIMD_INTRINSIC static int
       _S_find_last_set(simd_mask<_Tp, _Abi> __k)
-      {
-	return std::__bit_width(
-	  _SuperImpl::_S_to_bits(__data(__k))._M_to_bits()) - 1;
-      }
+      { return std::__bit_width(_SuperImpl::_S_to_bits(__data(__k))._M_to_bits()) - 1; }
 
     // }}}
   };
--- a/src/libstdc++-v3/include/experimental/bits/simd_converter.h
+++ b/src/libstdc++-v3/include/experimental/bits/simd_converter.h
@@ -121,7 +121,7 @@ template <typename _From, typename _To, int _Np>
 	{
 	  return __call_with_subscripts(
 	    __x, make_index_sequence<_Np>(),
-	    [](auto... __values) constexpr->_Ret {
+	    [](auto... __values) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA -> _Ret {
 	      return __make_simd_tuple<_To, decltype((void) __values,
 						     simd_abi::scalar())...>(
 		static_cast<_To>(__values)...);
@@ -233,7 +233,9 @@ template <typename _From, typename _To, int _Np>
 	  static_assert(_Ret::_FirstAbi::template _S_is_partial<_To>);
 	  return _Ret{__generate_from_n_evaluations<
 	    _Np, typename _VectorTraits<typename _Ret::_FirstType>::type>(
-	    [&](auto __i) { return static_cast<_To>(__x[__i]); })};
+	    [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	      return static_cast<_To>(__x[__i]);
+	    })};
 	}
       else
 	{
@@ -241,7 +243,7 @@ template <typename _From, typename _To, int _Np>
 	  constexpr auto __n
 	    = __div_roundup(_Ret::_S_first_size, _Arg::_S_first_size);
 	  return __call_with_n_evaluations<__n>(
-	    [&__x](auto... __uncvted) {
+	    [&__x](auto... __uncvted) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	      // assuming _Arg Abi tags for all __i are _Arg::_FirstAbi
 	      _SimdConverter<_From, typename _Arg::_FirstAbi, _To,
 			     typename _Ret::_FirstAbi>
@@ -255,8 +257,9 @@ template <typename _From, typename _To, int _Np>
 		    _From, simd_abi::fixed_size<_Np - _Ret::_S_first_size>, _To,
 		    simd_abi::fixed_size<_Np - _Ret::_S_first_size>>()(
 		    __simd_tuple_pop_front<_Ret::_S_first_size>(__x))};
-	    },
-	    [&__x](auto __i) { return __get_tuple_at<__i>(__x); });
+	    }, [&__x](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	      return __get_tuple_at<__i>(__x);
+	    });
 	}
     }
   };
@@ -322,13 +325,14 @@ template <typename _From, int _Np, typename _To, typename _Ap>
 	return __vector_convert<__vector_type_t<_To, _Np>>(__x.first);
       else if constexpr (_Arg::_S_is_homogeneous)
 	return __call_with_n_evaluations<_Arg::_S_tuple_size>(
-	  [](auto... __members) {
+	  [](auto... __members) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    if constexpr ((is_convertible_v<decltype(__members), _To> && ...))
 	      return __vector_type_t<_To, _Np>{static_cast<_To>(__members)...};
 	    else
 	      return __vector_convert<__vector_type_t<_To, _Np>>(__members...);
-	  },
-	  [&](auto __i) { return __get_tuple_at<__i>(__x); });
+	  }, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	    return __get_tuple_at<__i>(__x);
+	  });
       else if constexpr (__fixed_size_storage_t<_To, _Np>::_S_tuple_size == 1)
 	{
 	  _SimdConverter<_From, simd_abi::fixed_size<_Np>, _To,
@@ -340,7 +344,7 @@ template <typename _From, int _Np, typename _To, typename _Ap>
 	{
 	  const _SimdWrapper<_From, _Np> __xv
 	    = __generate_from_n_evaluations<_Np, __vector_type_t<_From, _Np>>(
-	      [&](auto __i) { return __x[__i]; });
+		[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; });
 	  return __vector_convert<__vector_type_t<_To, _Np>>(__xv);
 	}
     }
--- a/src/libstdc++-v3/include/experimental/bits/simd_detail.h
+++ b/src/libstdc++-v3/include/experimental/bits/simd_detail.h
@@ -254,9 +254,11 @@
 
 #ifdef __clang__
 #define _GLIBCXX_SIMD_NORMAL_MATH
+#define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
 #else
 #define _GLIBCXX_SIMD_NORMAL_MATH                                              \
   [[__gnu__::__optimize__("finite-math-only,no-signed-zeros")]]
+#define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA __attribute__((__always_inline__))
 #endif
 #define _GLIBCXX_SIMD_NEVER_INLINE [[__gnu__::__noinline__]]
 #define _GLIBCXX_SIMD_INTRINSIC                                                \
@@ -265,7 +267,7 @@
 #define _GLIBCXX_SIMD_IS_UNLIKELY(__x) __builtin_expect(__x, 0)
 #define _GLIBCXX_SIMD_IS_LIKELY(__x) __builtin_expect(__x, 1)
 
-#if defined __STRICT_ANSI__ && __STRICT_ANSI__
+#if __STRICT_ANSI__ || defined __clang__
 #define _GLIBCXX_SIMD_CONSTEXPR
 #define _GLIBCXX_SIMD_USE_CONSTEXPR_API const
 #else
@@ -294,6 +296,8 @@
 #ifdef _GLIBCXX_SIMD_NO_ALWAYS_INLINE
 #undef _GLIBCXX_SIMD_ALWAYS_INLINE
 #define _GLIBCXX_SIMD_ALWAYS_INLINE inline
+#undef _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+#define _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
 #undef _GLIBCXX_SIMD_INTRINSIC
 #define _GLIBCXX_SIMD_INTRINSIC inline
 #endif
--- a/src/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
+++ b/src/libstdc++-v3/include/experimental/bits/simd_fixed_size.h
@@ -55,10 +55,7 @@ template <typename _Tp, typename _A0, typename... _As>
 
 template <size_t _I, typename _Tp, typename _A0, typename... _As>
   struct __simd_tuple_element<_I, _SimdTuple<_Tp, _A0, _As...>>
-  {
-    using type =
-      typename __simd_tuple_element<_I - 1, _SimdTuple<_Tp, _As...>>::type;
-  };
+  { using type = typename __simd_tuple_element<_I - 1, _SimdTuple<_Tp, _As...>>::type; };
 
 template <size_t _I, typename _Tp>
   using __simd_tuple_element_t = typename __simd_tuple_element<_I, _Tp>::type;
@@ -80,10 +77,8 @@ template <typename _Tp, typename... _A0s, typename... _A1s>
   }
 
 template <typename _Tp, typename _A10, typename... _A1s>
-  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp, simd_abi::scalar, _A10,
-					       _A1s...>
-  __simd_tuple_concat(const _Tp& __left,
-		      const _SimdTuple<_Tp, _A10, _A1s...>& __right)
+  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp, simd_abi::scalar, _A10, _A1s...>
+  __simd_tuple_concat(const _Tp& __left, const _SimdTuple<_Tp, _A10, _A1s...>& __right)
   { return {__left, __right}; }
 
 // }}}
@@ -112,37 +107,29 @@ struct __as_simd_tuple {};
 
 template <typename _Tp, typename _A0, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr simd<_Tp, _A0>
-  __simd_tuple_get_impl(__as_simd, const _SimdTuple<_Tp, _A0, _Abis...>& __t,
-			_SizeConstant<0>)
+  __simd_tuple_get_impl(__as_simd, const _SimdTuple<_Tp, _A0, _Abis...>& __t, _SizeConstant<0>)
   { return {__private_init, __t.first}; }
 
 template <typename _Tp, typename _A0, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr const auto&
-  __simd_tuple_get_impl(__as_simd_tuple,
-			const _SimdTuple<_Tp, _A0, _Abis...>& __t,
+  __simd_tuple_get_impl(__as_simd_tuple, const _SimdTuple<_Tp, _A0, _Abis...>& __t,
 			_SizeConstant<0>)
   { return __t.first; }
 
 template <typename _Tp, typename _A0, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr auto&
-  __simd_tuple_get_impl(__as_simd_tuple, _SimdTuple<_Tp, _A0, _Abis...>& __t,
-			_SizeConstant<0>)
+  __simd_tuple_get_impl(__as_simd_tuple, _SimdTuple<_Tp, _A0, _Abis...>& __t, _SizeConstant<0>)
   { return __t.first; }
 
 template <typename _R, size_t _Np, typename _Tp, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr auto
-  __simd_tuple_get_impl(_R, const _SimdTuple<_Tp, _Abis...>& __t,
-			_SizeConstant<_Np>)
+  __simd_tuple_get_impl(_R, const _SimdTuple<_Tp, _Abis...>& __t, _SizeConstant<_Np>)
   { return __simd_tuple_get_impl(_R(), __t.second, _SizeConstant<_Np - 1>()); }
 
 template <size_t _Np, typename _Tp, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr auto&
-  __simd_tuple_get_impl(__as_simd_tuple, _SimdTuple<_Tp, _Abis...>& __t,
-			_SizeConstant<_Np>)
-  {
-    return __simd_tuple_get_impl(__as_simd_tuple(), __t.second,
-				 _SizeConstant<_Np - 1>());
-  }
+  __simd_tuple_get_impl(__as_simd_tuple, _SimdTuple<_Tp, _Abis...>& __t, _SizeConstant<_Np>)
+  { return __simd_tuple_get_impl(__as_simd_tuple(), __t.second, _SizeConstant<_Np - 1>()); }
 
 template <size_t _Np, typename _Tp, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr auto
@@ -154,16 +141,12 @@ template <size_t _Np, typename _Tp, typename... _Abis>
 template <size_t _Np, typename _Tp, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr auto
   __get_tuple_at(const _SimdTuple<_Tp, _Abis...>& __t)
-  {
-    return __simd_tuple_get_impl(__as_simd_tuple(), __t, _SizeConstant<_Np>());
-  }
+  { return __simd_tuple_get_impl(__as_simd_tuple(), __t, _SizeConstant<_Np>()); }
 
 template <size_t _Np, typename _Tp, typename... _Abis>
   _GLIBCXX_SIMD_INTRINSIC constexpr auto&
   __get_tuple_at(_SimdTuple<_Tp, _Abis...>& __t)
-  {
-    return __simd_tuple_get_impl(__as_simd_tuple(), __t, _SizeConstant<_Np>());
-  }
+  { return __simd_tuple_get_impl(__as_simd_tuple(), __t, _SizeConstant<_Np>()); }
 
 // __tuple_element_meta {{{1
 template <typename _Tp, typename _Abi, size_t _Offset>
@@ -183,25 +166,25 @@ template <typename _Tp, typename _Abi, size_t _Offset>
     static constexpr _MaskImpl _S_mask_impl = {};
 
     template <size_t _Np, bool _Sanitized>
-      _GLIBCXX_SIMD_INTRINSIC static auto
+      _GLIBCXX_SIMD_INTRINSIC static constexpr auto
       _S_submask(_BitMask<_Np, _Sanitized> __bits)
       { return __bits.template _M_extract<_Offset, _S_size()>(); }
 
     template <size_t _Np, bool _Sanitized>
-      _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
       _S_make_mask(_BitMask<_Np, _Sanitized> __bits)
       {
 	return _MaskImpl::template _S_convert<_Tp>(
 	  __bits.template _M_extract<_Offset, _S_size()>()._M_sanitized());
       }
 
-    _GLIBCXX_SIMD_INTRINSIC static _ULLong
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _ULLong
     _S_mask_to_shifted_ullong(_MaskMember __k)
     { return _MaskImpl::_S_to_bits(__k).to_ullong() << _Offset; }
   };
 
 template <size_t _Offset, typename _Tp, typename _Abi, typename... _As>
-  _GLIBCXX_SIMD_INTRINSIC
+  _GLIBCXX_SIMD_INTRINSIC constexpr
   __tuple_element_meta<_Tp, _Abi, _Offset>
   __make_meta(const _SimdTuple<_Tp, _Abi, _As...>&)
   { return {}; }
@@ -213,17 +196,13 @@ template <size_t _Offset, typename _Base>
   {
     static inline constexpr size_t _S_offset = _Offset;
 
-    _GLIBCXX_SIMD_INTRINSIC char* _M_as_charptr()
-    {
-      return reinterpret_cast<char*>(this)
-	     + _S_offset * sizeof(typename _Base::value_type);
-    }
+    _GLIBCXX_SIMD_INTRINSIC char*
+    _M_as_charptr()
+    { return reinterpret_cast<char*>(this) + _S_offset * sizeof(typename _Base::value_type); }
 
-    _GLIBCXX_SIMD_INTRINSIC const char* _M_as_charptr() const
-    {
-      return reinterpret_cast<const char*>(this)
-	     + _S_offset * sizeof(typename _Base::value_type);
-    }
+    _GLIBCXX_SIMD_INTRINSIC const char*
+    _M_as_charptr() const
+    { return reinterpret_cast<const char*>(this) + _S_offset * sizeof(typename _Base::value_type); }
   };
 
 // make _WithOffset<_WithOffset> ill-formed to use:
@@ -240,19 +219,13 @@ template <size_t _Offset, typename _Tp>
   _GLIBCXX_SIMD_INTRINSIC
   decltype(auto)
   __add_offset(const _Tp& __base)
-  {
-    return static_cast<const _WithOffset<_Offset, __remove_cvref_t<_Tp>>&>(
-      __base);
-  }
+  { return static_cast<const _WithOffset<_Offset, __remove_cvref_t<_Tp>>&>(__base); }
 
 template <size_t _Offset, size_t _ExistingOffset, typename _Tp>
   _GLIBCXX_SIMD_INTRINSIC
   decltype(auto)
   __add_offset(_WithOffset<_ExistingOffset, _Tp>& __base)
-  {
-    return static_cast<_WithOffset<_Offset + _ExistingOffset, _Tp>&>(
-      static_cast<_Tp&>(__base));
-  }
+  { return static_cast<_WithOffset<_Offset + _ExistingOffset, _Tp>&>(static_cast<_Tp&>(__base)); }
 
 template <size_t _Offset, size_t _ExistingOffset, typename _Tp>
   _GLIBCXX_SIMD_INTRINSIC
@@ -298,7 +271,8 @@ template <typename _FirstType, typename _SecondType>
     _SecondType second;
 
     _GLIBCXX_SIMD_INTRINSIC
-    constexpr bool _M_is_constprop() const
+    constexpr bool
+    _M_is_constprop() const
     {
       if constexpr (is_class_v<_FirstType>)
 	return first._M_is_constprop() && second._M_is_constprop();
@@ -314,7 +288,8 @@ template <typename _FirstType, typename _Tp>
     static constexpr _SimdTuple<_Tp> second = {};
 
     _GLIBCXX_SIMD_INTRINSIC
-    constexpr bool _M_is_constprop() const
+    constexpr bool
+    _M_is_constprop() const
     {
       if constexpr (is_class_v<_FirstType>)
 	return first._M_is_constprop();
@@ -353,25 +328,31 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
       = default;
 
     template <typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple(_Up&& __x)
+      _GLIBCXX_SIMD_INTRINSIC constexpr
+      _SimdTuple(_Up&& __x)
       : _Base{static_cast<_Up&&>(__x)} {}
 
     template <typename _Up, typename _Up2>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple(_Up&& __x, _Up2&& __y)
+      _GLIBCXX_SIMD_INTRINSIC constexpr
+      _SimdTuple(_Up&& __x, _Up2&& __y)
       : _Base{static_cast<_Up&&>(__x), static_cast<_Up2&&>(__y)} {}
 
     template <typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple(_Up&& __x, _SimdTuple<_Tp>)
+      _GLIBCXX_SIMD_INTRINSIC constexpr
+      _SimdTuple(_Up&& __x, _SimdTuple<_Tp>)
       : _Base{static_cast<_Up&&>(__x)} {}
 
-    _GLIBCXX_SIMD_INTRINSIC char* _M_as_charptr()
+    _GLIBCXX_SIMD_INTRINSIC char*
+    _M_as_charptr()
     { return reinterpret_cast<char*>(this); }
 
-    _GLIBCXX_SIMD_INTRINSIC const char* _M_as_charptr() const
+    _GLIBCXX_SIMD_INTRINSIC const char*
+    _M_as_charptr() const
     { return reinterpret_cast<const char*>(this); }
 
     template <size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC constexpr auto& _M_at()
+      _GLIBCXX_SIMD_INTRINSIC constexpr auto&
+      _M_at()
       {
 	if constexpr (_Np == 0)
 	  return first;
@@ -380,7 +361,8 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
       }
 
     template <size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC constexpr const auto& _M_at() const
+      _GLIBCXX_SIMD_INTRINSIC constexpr const auto&
+      _M_at() const
       {
 	if constexpr (_Np == 0)
 	  return first;
@@ -389,7 +371,8 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
       }
 
     template <size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC constexpr auto _M_simd_at() const
+      _GLIBCXX_SIMD_INTRINSIC constexpr auto
+      _M_simd_at() const
       {
 	if constexpr (_Np == 0)
 	  return simd<_Tp, _Abi0>(__private_init, first);
@@ -434,14 +417,15 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 	if constexpr (is_same_v<_SimdTuple, __remove_cvref_t<_Tup>>)
 	  return __tup.first;
 	else if (__builtin_is_constant_evaluated())
-	  return __fixed_size_storage_t<_TupT, _S_first_size>::_S_generate([&](
-	    auto __meta) constexpr {
-	    return __meta._S_generator(
-	      [&](auto __i) constexpr { return __tup[__i]; },
-	      static_cast<_TupT*>(nullptr));
+	  return __fixed_size_storage_t<_TupT, _S_first_size>::_S_generate(
+		   [&](auto __meta) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		     return __meta._S_generator(
+			      [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				return __tup[__i];
+			      }, static_cast<_TupT*>(nullptr));
 	  });
 	else
-	  return [&]() {
+	  return [&]() { // not always_inline; allow the compiler to decide
 	    __fixed_size_storage_t<_TupT, _S_first_size> __r;
 	    __builtin_memcpy(__r._M_as_charptr(), __tup._M_as_charptr(),
 			     sizeof(__r));
@@ -515,12 +499,11 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 			 negation<is_const<remove_reference_t<_More>>>>) )
 	  {
 	    // need to write back at least one of __more after calling __fun
-	    auto&& __first = [&](auto... __args) constexpr
-	    {
+	    auto&& __first = [&](auto... __args) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	      auto __r = __fun(__tuple_element_meta<_Tp, _Abi0, 0>(), first,
 			       __args...);
 	      [[maybe_unused]] auto&& __ignore_me = {(
-		[](auto&& __dst, const auto& __src) {
+		[](auto&& __dst, const auto& __src) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  if constexpr (is_assignable_v<decltype(__dst),
 						decltype(__dst)>)
 		    {
@@ -530,8 +513,7 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 		}(static_cast<_More&&>(__more), __args),
 		0)...};
 	      return __r;
-	    }
-	    (_M_extract_argument(__more)...);
+	    }(_M_extract_argument(__more)...);
 	    if constexpr (_S_tuple_size == 1)
 	      return {__first};
 	    else
@@ -553,8 +535,8 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
       }
 
     template <typename _R = _Tp, typename _Fp, typename... _More>
-      _GLIBCXX_SIMD_INTRINSIC auto _M_apply_r(_Fp&& __fun,
-					      const _More&... __more) const
+      _GLIBCXX_SIMD_INTRINSIC constexpr auto
+      _M_apply_r(_Fp&& __fun, const _More&... __more) const
       {
 	auto&& __first = __fun(__tuple_element_meta<_Tp, _Abi0, 0>(), first,
 			       __more.first...);
@@ -591,51 +573,44 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 	  return second[integral_constant<_Up, _I - simd_size_v<_Tp, _Abi0>>()];
       }
 
-    _GLIBCXX_SIMD_INTRINSIC
-    _Tp operator[](size_t __i) const noexcept
+    _GLIBCXX_SIMD_INTRINSIC constexpr _Tp
+    operator[](size_t __i) const noexcept
     {
       if constexpr (_S_tuple_size == 1)
 	return _M_subscript_read(__i);
-      else
-	{
 #ifdef _GLIBCXX_SIMD_USE_ALIASING_LOADS
-	  return reinterpret_cast<const __may_alias<_Tp>*>(this)[__i];
-#else
-	  if constexpr (__is_scalar_abi<_Abi0>())
-	    {
-	      const _Tp* ptr = &first;
-	      return ptr[__i];
-	    }
-	  else
-	    return __i < simd_size_v<_Tp, _Abi0>
-		     ? _M_subscript_read(__i)
-		     : second[__i - simd_size_v<_Tp, _Abi0>];
+      else if (not __builtin_is_constant_evaluated())
+	return reinterpret_cast<const __may_alias<_Tp>*>(this)[__i];
 #endif
+      else if constexpr (__is_scalar_abi<_Abi0>())
+	{
+	  const _Tp* ptr = &first;
+	  return ptr[__i];
 	}
+      else
+	return __i < simd_size_v<_Tp, _Abi0> ? _M_subscript_read(__i)
+					     : second[__i - simd_size_v<_Tp, _Abi0>];
     }
 
-    _GLIBCXX_SIMD_INTRINSIC
-    void _M_set(size_t __i, _Tp __val) noexcept
+    _GLIBCXX_SIMD_INTRINSIC constexpr void
+    _M_set(size_t __i, _Tp __val) noexcept
     {
       if constexpr (_S_tuple_size == 1)
 	return _M_subscript_write(__i, __val);
-      else
-	{
 #ifdef _GLIBCXX_SIMD_USE_ALIASING_LOADS
-	  reinterpret_cast<__may_alias<_Tp>*>(this)[__i] = __val;
-#else
-	  if (__i < simd_size_v<_Tp, _Abi0>)
-	    _M_subscript_write(__i, __val);
-	  else
-	    second._M_set(__i - simd_size_v<_Tp, _Abi0>, __val);
+      else if (not __builtin_is_constant_evaluated())
+	reinterpret_cast<__may_alias<_Tp>*>(this)[__i] = __val;
 #endif
-	}
+      else if (__i < simd_size_v<_Tp, _Abi0>)
+	_M_subscript_write(__i, __val);
+      else
+	second._M_set(__i - simd_size_v<_Tp, _Abi0>, __val);
     }
 
   private:
     // _M_subscript_read/_write {{{
-    _GLIBCXX_SIMD_INTRINSIC
-    _Tp _M_subscript_read([[maybe_unused]] size_t __i) const noexcept
+    _GLIBCXX_SIMD_INTRINSIC constexpr _Tp
+    _M_subscript_read([[maybe_unused]] size_t __i) const noexcept
     {
       if constexpr (__is_vectorizable_v<_FirstType>)
 	return first;
@@ -643,8 +618,8 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 	return first[__i];
     }
 
-    _GLIBCXX_SIMD_INTRINSIC
-    void _M_subscript_write([[maybe_unused]] size_t __i, _Tp __y) noexcept
+    _GLIBCXX_SIMD_INTRINSIC constexpr void
+    _M_subscript_write([[maybe_unused]] size_t __i, _Tp __y) noexcept
     {
       if constexpr (__is_vectorizable_v<_FirstType>)
 	first = __y;
@@ -657,22 +632,22 @@ template <typename _Tp, typename _Abi0, typename... _Abis>
 
 // __make_simd_tuple {{{1
 template <typename _Tp, typename _A0>
-  _GLIBCXX_SIMD_INTRINSIC _SimdTuple<_Tp, _A0>
+  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp, _A0>
   __make_simd_tuple(simd<_Tp, _A0> __x0)
   { return {__data(__x0)}; }
 
 template <typename _Tp, typename _A0, typename... _As>
-  _GLIBCXX_SIMD_INTRINSIC _SimdTuple<_Tp, _A0, _As...>
+  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp, _A0, _As...>
   __make_simd_tuple(const simd<_Tp, _A0>& __x0, const simd<_Tp, _As>&... __xs)
   { return {__data(__x0), __make_simd_tuple(__xs...)}; }
 
 template <typename _Tp, typename _A0>
-  _GLIBCXX_SIMD_INTRINSIC _SimdTuple<_Tp, _A0>
+  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp, _A0>
   __make_simd_tuple(const typename _SimdTraits<_Tp, _A0>::_SimdMember& __arg0)
   { return {__arg0}; }
 
 template <typename _Tp, typename _A0, typename _A1, typename... _Abis>
-  _GLIBCXX_SIMD_INTRINSIC _SimdTuple<_Tp, _A0, _A1, _Abis...>
+  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp, _A0, _A1, _Abis...>
   __make_simd_tuple(
     const typename _SimdTraits<_Tp, _A0>::_SimdMember& __arg0,
     const typename _SimdTraits<_Tp, _A1>::_SimdMember& __arg1,
@@ -688,8 +663,7 @@ template <typename _Tp, size_t _Np,
 	  size_t _Offset = 0, // skip this many elements in __from0
 	  typename _R = __fixed_size_storage_t<_Tp, _Np>, typename _V0,
 	  typename _V0VT = _VectorTraits<_V0>, typename... _VX>
-  _GLIBCXX_SIMD_INTRINSIC _R constexpr __to_simd_tuple(const _V0 __from0,
-						       const _VX... __fromX)
+  _GLIBCXX_SIMD_INTRINSIC _R constexpr __to_simd_tuple(const _V0 __from0, const _VX... __fromX)
   {
     static_assert(is_same_v<typename _V0VT::value_type, _Tp>);
     static_assert(_Offset < _V0VT::_S_full_size);
@@ -776,18 +750,18 @@ template <typename _Tp, size_t _Np, typename _V, size_t _NV, typename... _VX>
 	  sizeof...(_VX) == 0,
 	  "An array of scalars must be the last argument to __to_simd_tuple");
 	return __call_with_subscripts(
-	  __from,
-	  make_index_sequence<_NV>(), [&](const auto... __args) constexpr {
-	    return __simd_tuple_concat(
-	      _SimdTuple<_Tp, simd_abi::scalar>{__args}..., _SimdTuple<_Tp>());
-	  });
+		 __from, make_index_sequence<_NV>(),
+		 [&](const auto... __args) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __simd_tuple_concat(
+			    _SimdTuple<_Tp, simd_abi::scalar>{__args}..., _SimdTuple<_Tp>());
+		 });
       }
     else
       return __call_with_subscripts(
-	__from,
-	make_index_sequence<_NV>(), [&](const auto... __args) constexpr {
-	  return __to_simd_tuple<_Tp, _Np>(__args..., __fromX...);
-	});
+	       __from, make_index_sequence<_NV>(),
+	       [&](const auto... __args) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		 return __to_simd_tuple<_Tp, _Np>(__args..., __fromX...);
+	       });
   }
 
 template <size_t, typename _Tp>
@@ -816,19 +790,19 @@ template <typename _Tp, typename _A0, size_t _NOut, size_t _Np,
 
 // __optimize_simd_tuple {{{1
 template <typename _Tp>
-  _GLIBCXX_SIMD_INTRINSIC _SimdTuple<_Tp>
+  _GLIBCXX_SIMD_INTRINSIC constexpr _SimdTuple<_Tp>
   __optimize_simd_tuple(const _SimdTuple<_Tp>)
   { return {}; }
 
 template <typename _Tp, typename _Ap>
-  _GLIBCXX_SIMD_INTRINSIC const _SimdTuple<_Tp, _Ap>&
+  _GLIBCXX_SIMD_INTRINSIC constexpr const _SimdTuple<_Tp, _Ap>&
   __optimize_simd_tuple(const _SimdTuple<_Tp, _Ap>& __x)
   { return __x; }
 
 template <typename _Tp, typename _A0, typename _A1, typename... _Abis,
 	  typename _R = __fixed_size_storage_t<
 	    _Tp, _SimdTuple<_Tp, _A0, _A1, _Abis...>::_S_size()>>
-  _GLIBCXX_SIMD_INTRINSIC _R
+  _GLIBCXX_SIMD_INTRINSIC constexpr _R
   __optimize_simd_tuple(const _SimdTuple<_Tp, _A0, _A1, _Abis...>& __x)
   {
     using _Tup = _SimdTuple<_Tp, _A0, _A1, _Abis...>;
@@ -841,7 +815,7 @@ template <typename _Tp, typename _A0, typename _A1, typename... _Abis,
 		       || _A0::template _S_is_partial<_Tp>)
       return {__generate_from_n_evaluations<_R::_S_first_size,
 					    typename _R::_FirstType>(
-		[&](auto __i) { return __x[__i]; }),
+		[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { return __x[__i]; }),
 	      __optimize_simd_tuple(
 		__simd_tuple_pop_front<_R::_S_first_size>(__x))};
     else if constexpr (is_same_v<_A0, _A1>
@@ -901,11 +875,8 @@ template <size_t _Offset = 0, typename _Tp, typename _A0, typename _A1,
 // __for_each(_SimdTuple &, const _SimdTuple &, Fun) {{{1
 template <size_t _Offset = 0, typename _Tp, typename _A0, typename _Fp>
   _GLIBCXX_SIMD_INTRINSIC constexpr void
-  __for_each(_SimdTuple<_Tp, _A0>& __a, const _SimdTuple<_Tp, _A0>& __b,
-	     _Fp&& __fun)
-  {
-    static_cast<_Fp&&>(__fun)(__make_meta<_Offset>(__a), __a.first, __b.first);
-  }
+  __for_each(_SimdTuple<_Tp, _A0>& __a, const _SimdTuple<_Tp, _A0>& __b, _Fp&& __fun)
+  { static_cast<_Fp&&>(__fun)(__make_meta<_Offset>(__a), __a.first, __b.first); }
 
 template <size_t _Offset = 0, typename _Tp, typename _A0, typename _A1,
 	  typename... _As, typename _Fp>
@@ -921,11 +892,8 @@ template <size_t _Offset = 0, typename _Tp, typename _A0, typename _A1,
 // __for_each(const _SimdTuple &, const _SimdTuple &, Fun) {{{1
 template <size_t _Offset = 0, typename _Tp, typename _A0, typename _Fp>
   _GLIBCXX_SIMD_INTRINSIC constexpr void
-  __for_each(const _SimdTuple<_Tp, _A0>& __a, const _SimdTuple<_Tp, _A0>& __b,
-	     _Fp&& __fun)
-  {
-    static_cast<_Fp&&>(__fun)(__make_meta<_Offset>(__a), __a.first, __b.first);
-  }
+  __for_each(const _SimdTuple<_Tp, _A0>& __a, const _SimdTuple<_Tp, _A0>& __b, _Fp&& __fun)
+  { static_cast<_Fp&&>(__fun)(__make_meta<_Offset>(__a), __a.first, __b.first); }
 
 template <size_t _Offset = 0, typename _Tp, typename _A0, typename _A1,
 	  typename... _As, typename _Fp>
@@ -940,9 +908,8 @@ template <size_t _Offset = 0, typename _Tp, typename _A0, typename _A1,
 
 // }}}1
 // __extract_part(_SimdTuple) {{{
-template <int _Index, int _Total, int _Combine, typename _Tp, typename _A0,
-	  typename... _As>
-  _GLIBCXX_SIMD_INTRINSIC auto // __vector_type_t or _SimdTuple
+template <int _Index, int _Total, int _Combine, typename _Tp, typename _A0, typename... _As>
+  _GLIBCXX_SIMD_INTRINSIC constexpr auto // __vector_type_t or _SimdTuple
   __extract_part(const _SimdTuple<_Tp, _A0, _As...>& __x)
   {
     // worst cases:
@@ -994,10 +961,11 @@ template <int _Index, int _Total, int _Combine, typename _Tp, typename _A0,
 	return __as_vector(simd<_Tp, _RetAbi>(element_ptr, element_aligned));
 #else
 	[[maybe_unused]] constexpr size_t __offset = __values_to_skip;
-	return __as_vector(simd<_Tp, _RetAbi>([&](auto __i) constexpr {
-	  constexpr _SizeConstant<__i + __offset> __k;
-	  return __x[__k];
-	}));
+	return __as_vector(simd<_Tp, _RetAbi>(
+			     [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			       constexpr _SizeConstant<__i + __offset> __k;
+			       return __x[__k];
+			     }));
 #endif
       }
 
@@ -1042,11 +1010,11 @@ template <typename _Tp, bool = is_arithmetic_v<__remove_cvref_t<_Tp>>>
     _Tp _M_data;
     using _TT = __remove_cvref_t<_Tp>;
 
-    _GLIBCXX_SIMD_INTRINSIC
+    _GLIBCXX_SIMD_INTRINSIC constexpr
     operator _TT()
     { return _M_data; }
 
-    _GLIBCXX_SIMD_INTRINSIC
+    _GLIBCXX_SIMD_INTRINSIC constexpr
     operator _TT&()
     {
       static_assert(is_lvalue_reference<_Tp>::value, "");
@@ -1054,7 +1022,7 @@ template <typename _Tp, bool = is_arithmetic_v<__remove_cvref_t<_Tp>>>
       return _M_data;
     }
 
-    _GLIBCXX_SIMD_INTRINSIC
+    _GLIBCXX_SIMD_INTRINSIC constexpr
     operator _TT*()
     {
       static_assert(is_lvalue_reference<_Tp>::value, "");
@@ -1062,29 +1030,23 @@ template <typename _Tp, bool = is_arithmetic_v<__remove_cvref_t<_Tp>>>
       return &_M_data;
     }
 
-    _GLIBCXX_SIMD_INTRINSIC
-    constexpr __autocvt_to_simd(_Tp dd) : _M_data(dd) {}
+    _GLIBCXX_SIMD_INTRINSIC constexpr
+    __autocvt_to_simd(_Tp dd) : _M_data(dd) {}
 
     template <typename _Abi>
-      _GLIBCXX_SIMD_INTRINSIC
+      _GLIBCXX_SIMD_INTRINSIC constexpr
       operator simd<typename _TT::value_type, _Abi>()
       { return {__private_init, _M_data}; }
 
     template <typename _Abi>
-      _GLIBCXX_SIMD_INTRINSIC
+      _GLIBCXX_SIMD_INTRINSIC constexpr
       operator simd<typename _TT::value_type, _Abi>&()
-      {
-	return *reinterpret_cast<simd<typename _TT::value_type, _Abi>*>(
-	  &_M_data);
-      }
+      { return *reinterpret_cast<simd<typename _TT::value_type, _Abi>*>(&_M_data); }
 
     template <typename _Abi>
-      _GLIBCXX_SIMD_INTRINSIC
+      _GLIBCXX_SIMD_INTRINSIC constexpr
       operator simd<typename _TT::value_type, _Abi>*()
-      {
-	return reinterpret_cast<simd<typename _TT::value_type, _Abi>*>(
-	  &_M_data);
-      }
+      { return reinterpret_cast<simd<typename _TT::value_type, _Abi>*>(&_M_data); }
   };
 
 template <typename _Tp>
@@ -1104,11 +1066,11 @@ template <typename _Tp>
     ~__autocvt_to_simd()
     { _M_data = __data(_M_fd).first; }
 
-    _GLIBCXX_SIMD_INTRINSIC
+    _GLIBCXX_SIMD_INTRINSIC constexpr
     operator fixed_size_simd<_TT, 1>()
     { return _M_fd; }
 
-    _GLIBCXX_SIMD_INTRINSIC
+    _GLIBCXX_SIMD_INTRINSIC constexpr
     operator fixed_size_simd<_TT, 1> &()
     {
       static_assert(is_lvalue_reference<_Tp>::value, "");
@@ -1116,7 +1078,7 @@ template <typename _Tp>
       return _M_fd;
     }
 
-    _GLIBCXX_SIMD_INTRINSIC
+    _GLIBCXX_SIMD_INTRINSIC constexpr
     operator fixed_size_simd<_TT, 1> *()
     {
       static_assert(is_lvalue_reference<_Tp>::value, "");
@@ -1193,16 +1155,17 @@ template <int _Np>
 	{
 	  // The following ensures, function arguments are passed via the stack.
 	  // This is important for ABI compatibility across TU boundaries
-	  _GLIBCXX_SIMD_ALWAYS_INLINE
+	  _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
 	  _SimdBase(const _SimdBase&) {}
+
 	  _SimdBase() = default;
 
-	  _GLIBCXX_SIMD_ALWAYS_INLINE
-	  explicit operator const _SimdMember &() const
+	  _GLIBCXX_SIMD_ALWAYS_INLINE constexpr explicit
+	  operator const _SimdMember &() const
 	  { return static_cast<const simd<_Tp, _Fixed>*>(this)->_M_data; }
 
-	  _GLIBCXX_SIMD_ALWAYS_INLINE
-	  explicit operator array<_Tp, _Np>() const
+	  _GLIBCXX_SIMD_ALWAYS_INLINE constexpr explicit
+	  operator array<_Tp, _Np>() const
 	  {
 	    array<_Tp, _Np> __r;
 	    // _SimdMember can be larger because of higher alignment
@@ -1222,12 +1185,14 @@ template <int _Np>
 	// _SimdCastType {{{
 	struct _SimdCastType
 	{
-	  _GLIBCXX_SIMD_ALWAYS_INLINE
+	  _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
 	  _SimdCastType(const array<_Tp, _Np>&);
-	  _GLIBCXX_SIMD_ALWAYS_INLINE
+
+	  _GLIBCXX_SIMD_ALWAYS_INLINE constexpr
 	  _SimdCastType(const _SimdMember& dd) : _M_data(dd) {}
-	  _GLIBCXX_SIMD_ALWAYS_INLINE
-	  explicit operator const _SimdMember &() const { return _M_data; }
+
+	  _GLIBCXX_SIMD_ALWAYS_INLINE constexpr explicit
+	  operator const _SimdMember &() const { return _M_data; }
 
 	private:
 	  const _SimdMember& _M_data;
@@ -1284,52 +1249,56 @@ template <int _Np, typename>
 
     // broadcast {{{2
     template <typename _Tp>
-      static constexpr inline _SimdMember<_Tp> _S_broadcast(_Tp __x) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdMember<_Tp>
+      _S_broadcast(_Tp __x) noexcept
       {
-	return _SimdMember<_Tp>::_S_generate([&](auto __meta) constexpr {
-	  return __meta._S_broadcast(__x);
-	});
+	return _SimdMember<_Tp>::_S_generate(
+		 [&](auto __meta) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __meta._S_broadcast(__x);
+		 });
       }
 
     // _S_generator {{{2
     template <typename _Fp, typename _Tp>
-      static constexpr inline _SimdMember<_Tp> _S_generator(_Fp&& __gen,
-							    _TypeTag<_Tp>)
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdMember<_Tp>
+      _S_generator(_Fp&& __gen, _TypeTag<_Tp>)
       {
-	return _SimdMember<_Tp>::_S_generate([&__gen](auto __meta) constexpr {
-	  return __meta._S_generator(
-	    [&](auto __i) constexpr {
-	      return __i < _Np ? __gen(_SizeConstant<__meta._S_offset + __i>())
-			       : 0;
-	    },
-	    _TypeTag<_Tp>());
-	});
+	return _SimdMember<_Tp>::_S_generate(
+		 [&__gen](auto __meta) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __meta._S_generator(
+			    [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			      return __i < _Np ? __gen(_SizeConstant<__meta._S_offset + __i>())
+					       : 0;
+			    },
+			    _TypeTag<_Tp>());
+		 });
       }
 
     // _S_load {{{2
     template <typename _Tp, typename _Up>
-      static inline _SimdMember<_Tp> _S_load(const _Up* __mem,
-					     _TypeTag<_Tp>) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdMember<_Tp>
+      _S_load(const _Up* __mem, _TypeTag<_Tp>) noexcept
       {
-	return _SimdMember<_Tp>::_S_generate([&](auto __meta) {
-	  return __meta._S_load(&__mem[__meta._S_offset], _TypeTag<_Tp>());
-	});
+	return _SimdMember<_Tp>::_S_generate(
+		 [&](auto __meta) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __meta._S_load(&__mem[__meta._S_offset], _TypeTag<_Tp>());
+		 });
       }
 
     // _S_masked_load {{{2
     template <typename _Tp, typename... _As, typename _Up>
-      static inline _SimdTuple<_Tp, _As...>
+      _GLIBCXX_SIMD_INTRINSIC static _SimdTuple<_Tp, _As...>
       _S_masked_load(const _SimdTuple<_Tp, _As...>& __old,
 		     const _MaskMember __bits, const _Up* __mem) noexcept
       {
 	auto __merge = __old;
-	__for_each(__merge, [&](auto __meta, auto& __native) {
+	__for_each(__merge, [&](auto __meta, auto& __native) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  if (__meta._S_submask(__bits).any())
 #pragma GCC diagnostic push
-	  // __mem + __mem._S_offset could be UB ([expr.add]/4.3, but it punts
-	  // the responsibility for avoiding UB to the caller of the masked load
-	  // via the mask. Consequently, the compiler may assume this branch is
-	  // unreachable, if the pointer arithmetic is UB.
+	    // Dereferencing __mem + __meta._S_offset could be UB ([expr.add]/4.3).
+	    // It is the responsibility of the caller of the masked load (via the mask's value) to
+	    // avoid UB. Consequently, the compiler may assume this branch is unreachable, if the
+	    // pointer arithmetic is UB.
 #pragma GCC diagnostic ignored "-Warray-bounds"
 	    __native
 	      = __meta._S_masked_load(__native, __meta._S_make_mask(__bits),
@@ -1341,21 +1310,21 @@ template <int _Np, typename>
 
     // _S_store {{{2
     template <typename _Tp, typename _Up>
-      static inline void _S_store(const _SimdMember<_Tp>& __v, _Up* __mem,
-				  _TypeTag<_Tp>) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
+      _S_store(const _SimdMember<_Tp>& __v, _Up* __mem, _TypeTag<_Tp>) noexcept
       {
-	__for_each(__v, [&](auto __meta, auto __native) {
+	__for_each(__v, [&](auto __meta, auto __native) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  __meta._S_store(__native, &__mem[__meta._S_offset], _TypeTag<_Tp>());
 	});
       }
 
     // _S_masked_store {{{2
     template <typename _Tp, typename... _As, typename _Up>
-      static inline void _S_masked_store(const _SimdTuple<_Tp, _As...>& __v,
-					 _Up* __mem,
-					 const _MaskMember __bits) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static void
+      _S_masked_store(const _SimdTuple<_Tp, _As...>& __v, _Up* __mem,
+		      const _MaskMember __bits) noexcept
       {
-	__for_each(__v, [&](auto __meta, auto __native) {
+	__for_each(__v, [&](auto __meta, auto __native) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  if (__meta._S_submask(__bits).any())
 #pragma GCC diagnostic push
 	  // __mem + __mem._S_offset could be UB ([expr.add]/4.3, but it punts
@@ -1371,12 +1340,12 @@ template <int _Np, typename>
 
     // negation {{{2
     template <typename _Tp, typename... _As>
-      static inline _MaskMember
+      static constexpr inline _MaskMember
       _S_negate(const _SimdTuple<_Tp, _As...>& __x) noexcept
       {
 	_MaskMember __bits = 0;
 	__for_each(
-	  __x, [&__bits](auto __meta, auto __native) constexpr {
+	  __x, [&__bits](auto __meta, auto __native) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __bits
 	      |= __meta._S_mask_to_shifted_ullong(__meta._S_negate(__native));
 	  });
@@ -1414,7 +1383,7 @@ template <int _Np, typename>
 	  {
 	    const auto& __x2 = __call_with_n_evaluations<
 	      __div_roundup(_Tup::_S_tuple_size, 2)>(
-	      [](auto __first_simd, auto... __remaining) {
+	      [](auto __first_simd, auto... __remaining) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		if constexpr (sizeof...(__remaining) == 0)
 		  return __first_simd;
 		else
@@ -1428,7 +1397,7 @@ template <int _Np, typename>
 		      __make_simd_tuple(__first_simd, __remaining...));
 		  }
 	      },
-	      [&](auto __i) {
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		auto __left = __tup.template _M_simd_at<2 * __i>();
 		if constexpr (2 * __i + 1 == _Tup::_S_tuple_size)
 		  return __left;
@@ -1444,7 +1413,9 @@ template <int _Np, typename>
 			_GLIBCXX_SIMD_USE_CONSTEXPR_API
 			typename _LT::mask_type __k(
 			  __private_init,
-			  [](auto __j) constexpr { return __j < _RT::size(); });
+			  [](auto __j) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			    return __j < _RT::size();
+			  });
 			_LT __ext_right = __left;
 			where(__k, __ext_right)
 			  = __proposed::resizing_simd_cast<_LT>(__right);
@@ -1459,24 +1430,22 @@ template <int _Np, typename>
 
     // _S_min, _S_max {{{2
     template <typename _Tp, typename... _As>
-      static inline constexpr _SimdTuple<_Tp, _As...>
-      _S_min(const _SimdTuple<_Tp, _As...>& __a,
-	     const _SimdTuple<_Tp, _As...>& __b)
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
+      _S_min(const _SimdTuple<_Tp, _As...>& __a, const _SimdTuple<_Tp, _As...>& __b)
       {
 	return __a._M_apply_per_chunk(
-	  [](auto __impl, auto __aa, auto __bb) constexpr {
+	  [](auto __impl, auto __aa, auto __bb) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    return __impl._S_min(__aa, __bb);
 	  },
 	  __b);
       }
 
     template <typename _Tp, typename... _As>
-      static inline constexpr _SimdTuple<_Tp, _As...>
-      _S_max(const _SimdTuple<_Tp, _As...>& __a,
-	     const _SimdTuple<_Tp, _As...>& __b)
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
+      _S_max(const _SimdTuple<_Tp, _As...>& __a, const _SimdTuple<_Tp, _As...>& __b)
       {
 	return __a._M_apply_per_chunk(
-	  [](auto __impl, auto __aa, auto __bb) constexpr {
+	  [](auto __impl, auto __aa, auto __bb) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    return __impl._S_max(__aa, __bb);
 	  },
 	  __b);
@@ -1484,36 +1453,38 @@ template <int _Np, typename>
 
     // _S_complement {{{2
     template <typename _Tp, typename... _As>
-      static inline constexpr _SimdTuple<_Tp, _As...>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
       _S_complement(const _SimdTuple<_Tp, _As...>& __x) noexcept
       {
-	return __x._M_apply_per_chunk([](auto __impl, auto __xx) constexpr {
-	  return __impl._S_complement(__xx);
-	});
+	return __x._M_apply_per_chunk(
+		 [](auto __impl, auto __xx) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __impl._S_complement(__xx);
+		 });
       }
 
     // _S_unary_minus {{{2
     template <typename _Tp, typename... _As>
-      static inline constexpr _SimdTuple<_Tp, _As...>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
       _S_unary_minus(const _SimdTuple<_Tp, _As...>& __x) noexcept
       {
-	return __x._M_apply_per_chunk([](auto __impl, auto __xx) constexpr {
-	  return __impl._S_unary_minus(__xx);
-	});
+	return __x._M_apply_per_chunk(
+		 [](auto __impl, auto __xx) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __impl._S_unary_minus(__xx);
+		 });
       }
 
     // arithmetic operators {{{2
 
-#define _GLIBCXX_SIMD_FIXED_OP(name_, op_)                                     \
-    template <typename _Tp, typename... _As>                                   \
-      static inline constexpr _SimdTuple<_Tp, _As...> name_(                   \
-	const _SimdTuple<_Tp, _As...>& __x, const _SimdTuple<_Tp, _As...>& __y)\
-      {                                                                        \
-	return __x._M_apply_per_chunk(                                         \
-	  [](auto __impl, auto __xx, auto __yy) constexpr {                    \
-	    return __impl.name_(__xx, __yy);                                   \
-	  },                                                                   \
-	  __y);                                                                \
+#define _GLIBCXX_SIMD_FIXED_OP(name_, op_)                                                     \
+    template <typename _Tp, typename... _As>                                                   \
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...> name_(                  \
+	const _SimdTuple<_Tp, _As...>& __x, const _SimdTuple<_Tp, _As...>& __y)                \
+      {                                                                                        \
+	return __x._M_apply_per_chunk(                                                         \
+	  [](auto __impl, auto __xx, auto __yy) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { \
+	    return __impl.name_(__xx, __yy);                                                   \
+	  },                                                                                   \
+	  __y);                                                                                \
       }
 
     _GLIBCXX_SIMD_FIXED_OP(_S_plus, +)
@@ -1529,21 +1500,23 @@ template <int _Np, typename>
 #undef _GLIBCXX_SIMD_FIXED_OP
 
     template <typename _Tp, typename... _As>
-      static inline constexpr _SimdTuple<_Tp, _As...>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
       _S_bit_shift_left(const _SimdTuple<_Tp, _As...>& __x, int __y)
       {
-	return __x._M_apply_per_chunk([__y](auto __impl, auto __xx) constexpr {
-	  return __impl._S_bit_shift_left(__xx, __y);
-	});
+	return __x._M_apply_per_chunk(
+		 [__y](auto __impl, auto __xx) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __impl._S_bit_shift_left(__xx, __y);
+		 });
       }
 
     template <typename _Tp, typename... _As>
-      static inline constexpr _SimdTuple<_Tp, _As...>
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdTuple<_Tp, _As...>
       _S_bit_shift_right(const _SimdTuple<_Tp, _As...>& __x, int __y)
       {
-	return __x._M_apply_per_chunk([__y](auto __impl, auto __xx) constexpr {
-	  return __impl._S_bit_shift_right(__xx, __y);
-	});
+	return __x._M_apply_per_chunk(
+		 [__y](auto __impl, auto __xx) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __impl._S_bit_shift_right(__xx, __y);
+		 });
       }
 
   // math {{{2
@@ -1557,35 +1530,40 @@ template <int _Np, typename>
 	  {                                                                    \
 	    if constexpr (is_same_v<_Tp, _RetTp>)                              \
 	      return __x._M_apply_per_chunk(                                   \
-		[](auto __impl, auto __xx) constexpr {                         \
-		  using _V = typename decltype(__impl)::simd_type;             \
-		  return __data(__name(_V(__private_init, __xx)));             \
-		});                                                            \
+		       [](auto __impl, auto __xx)                              \
+			 constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA          \
+		       {                                                       \
+			 using _V = typename decltype(__impl)::simd_type;      \
+			 return __data(__name(_V(__private_init, __xx)));      \
+		       });                                                     \
 	    else                                                               \
 	      return __optimize_simd_tuple(                                    \
-		__x.template _M_apply_r<_RetTp>([](auto __impl, auto __xx) {   \
-		  return __impl._S_##__name(__xx);                             \
-		}));                                                           \
+		       __x.template _M_apply_r<_RetTp>(                        \
+			 [](auto __impl, auto __xx)                            \
+			   _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA                  \
+			 { return __impl._S_##__name(__xx); }));               \
 	  }                                                                    \
 	else if constexpr (                                                    \
 	  is_same_v<                                                           \
 	    _Tp,                                                               \
 	    _RetTp> && (... && is_same_v<_SimdTuple<_Tp, _As...>, _More>) )    \
 	  return __x._M_apply_per_chunk(                                       \
-	    [](auto __impl, auto __xx, auto... __pack) constexpr {             \
-	      using _V = typename decltype(__impl)::simd_type;                 \
-	      return __data(__name(_V(__private_init, __xx),                   \
-				   _V(__private_init, __pack)...));            \
-	    },                                                                 \
-	    __more...);                                                        \
+		   [](auto __impl, auto __xx, auto... __pack)                  \
+		     constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA              \
+		   {                                                           \
+		     using _V = typename decltype(__impl)::simd_type;          \
+		     return __data(__name(_V(__private_init, __xx),            \
+					  _V(__private_init, __pack)...));     \
+		   }, __more...);                                              \
 	else if constexpr (is_same_v<_Tp, _RetTp>)                             \
 	  return __x._M_apply_per_chunk(                                       \
-	    [](auto __impl, auto __xx, auto... __pack) constexpr {             \
-	      using _V = typename decltype(__impl)::simd_type;                 \
-	      return __data(__name(_V(__private_init, __xx),                   \
-				   __autocvt_to_simd(__pack)...));             \
-	    },                                                                 \
-	    __more...);                                                        \
+		   [](auto __impl, auto __xx, auto... __pack)                  \
+		     constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA              \
+		   {                                                           \
+		     using _V = typename decltype(__impl)::simd_type;          \
+		     return __data(__name(_V(__private_init, __xx),            \
+					  __autocvt_to_simd(__pack)...));      \
+		   }, __more...);                                              \
 	else                                                                   \
 	  __assert_unreachable<_Tp>();                                         \
       }
@@ -1651,16 +1629,15 @@ template <int _Np, typename>
 #undef _GLIBCXX_SIMD_APPLY_ON_TUPLE
 
     template <typename _Tp, typename... _Abis>
-      static _SimdTuple<_Tp, _Abis...> _S_remquo(
-	const _SimdTuple<_Tp, _Abis...>& __x,
-	const _SimdTuple<_Tp, _Abis...>& __y,
-	__fixed_size_storage_t<int, _SimdTuple<_Tp, _Abis...>::_S_size()>* __z)
+      static inline _SimdTuple<_Tp, _Abis...>
+      _S_remquo(const _SimdTuple<_Tp, _Abis...>& __x, const _SimdTuple<_Tp, _Abis...>& __y,
+		__fixed_size_storage_t<int, _SimdTuple<_Tp, _Abis...>::_S_size()>* __z)
       {
 	return __x._M_apply_per_chunk(
-	  [](auto __impl, const auto __xx, const auto __yy, auto& __zz) {
-	    return __impl._S_remquo(__xx, __yy, &__zz);
-	  },
-	  __y, *__z);
+		 [](auto __impl, const auto __xx, const auto __yy, auto& __zz)
+		   _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+		 { return __impl._S_remquo(__xx, __yy, &__zz); },
+		 __y, *__z);
       }
 
     template <typename _Tp, typename... _As>
@@ -1669,22 +1646,20 @@ template <int _Np, typename>
 	       __fixed_size_storage_t<int, _Np>& __exp) noexcept
       {
 	return __x._M_apply_per_chunk(
-	  [](auto __impl, const auto& __a, auto& __b) {
-	    return __data(
-	      frexp(typename decltype(__impl)::simd_type(__private_init, __a),
-		    __autocvt_to_simd(__b)));
-	  },
-	  __exp);
+		 [](auto __impl, const auto& __a, auto& __b) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __data(frexp(typename decltype(__impl)::simd_type(__private_init, __a),
+				       __autocvt_to_simd(__b)));
+		 }, __exp);
       }
 
-#define _GLIBCXX_SIMD_TEST_ON_TUPLE_(name_)                                    \
-    template <typename _Tp, typename... _As>                                   \
-      static inline _MaskMember                                                \
-	_S_##name_(const _SimdTuple<_Tp, _As...>& __x) noexcept                \
-      {                                                                        \
-	return _M_test([](auto __impl,                                         \
-			  auto __xx) { return __impl._S_##name_(__xx); },      \
-		       __x);                                                   \
+#define _GLIBCXX_SIMD_TEST_ON_TUPLE_(name_)                                              \
+    template <typename _Tp, typename... _As>                                             \
+      static inline _MaskMember                                                          \
+      _S_##name_(const _SimdTuple<_Tp, _As...>& __x) noexcept                            \
+      {                                                                                  \
+	return _M_test([] (auto __impl, auto __xx) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA  { \
+		 return __impl._S_##name_(__xx);                                         \
+	       }, __x);                                                                  \
       }
 
     _GLIBCXX_SIMD_TEST_ON_TUPLE_(isinf)
@@ -1700,7 +1675,7 @@ template <int _Np, typename>
       _S_increment(_SimdTuple<_Ts...>& __x)
       {
 	__for_each(
-	  __x, [](auto __meta, auto& native) constexpr {
+	  __x, [](auto __meta, auto& native) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __meta._S_increment(native);
 	  });
       }
@@ -1710,7 +1685,7 @@ template <int _Np, typename>
       _S_decrement(_SimdTuple<_Ts...>& __x)
       {
 	__for_each(
-	  __x, [](auto __meta, auto& native) constexpr {
+	  __x, [](auto __meta, auto& native) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __meta._S_decrement(native);
 	  });
       }
@@ -1718,15 +1693,14 @@ template <int _Np, typename>
     // compares {{{2
 #define _GLIBCXX_SIMD_CMP_OPERATIONS(__cmp)                                    \
     template <typename _Tp, typename... _As>                                   \
-      _GLIBCXX_SIMD_INTRINSIC constexpr static _MaskMember                     \
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember                     \
       __cmp(const _SimdTuple<_Tp, _As...>& __x,                                \
 	    const _SimdTuple<_Tp, _As...>& __y)                                \
       {                                                                        \
-	return _M_test(                                                        \
-	  [](auto __impl, auto __xx, auto __yy) constexpr {                    \
-	    return __impl.__cmp(__xx, __yy);                                   \
-	  },                                                                   \
-	  __x, __y);                                                           \
+	return _M_test([](auto __impl, auto __xx, auto __yy)                   \
+			 constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA          \
+		       { return __impl.__cmp(__xx, __yy); },                   \
+		       __x, __y);                                              \
       }
 
     _GLIBCXX_SIMD_CMP_OPERATIONS(_S_equal_to)
@@ -1743,33 +1717,34 @@ template <int _Np, typename>
 
     // smart_reference access {{{2
     template <typename _Tp, typename... _As, typename _Up>
-      _GLIBCXX_SIMD_INTRINSIC static void _S_set(_SimdTuple<_Tp, _As...>& __v,
-						 int __i, _Up&& __x) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
+      _S_set(_SimdTuple<_Tp, _As...>& __v, int __i, _Up&& __x) noexcept
       { __v._M_set(__i, static_cast<_Up&&>(__x)); }
 
     // _S_masked_assign {{{2
     template <typename _Tp, typename... _As>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_masked_assign(const _MaskMember __bits, _SimdTuple<_Tp, _As...>& __lhs,
 		       const __type_identity_t<_SimdTuple<_Tp, _As...>>& __rhs)
       {
-	__for_each(
-	  __lhs, __rhs,
-	  [&](auto __meta, auto& __native_lhs, auto __native_rhs) constexpr {
-	    __meta._S_masked_assign(__meta._S_make_mask(__bits), __native_lhs,
-				    __native_rhs);
-	  });
+	__for_each(__lhs, __rhs,
+		   [&](auto __meta, auto& __native_lhs, auto __native_rhs)
+		     constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+		   {
+		     __meta._S_masked_assign(__meta._S_make_mask(__bits), __native_lhs,
+					     __native_rhs);
+		   });
       }
 
     // Optimization for the case where the RHS is a scalar. No need to broadcast
     // the scalar to a simd first.
     template <typename _Tp, typename... _As>
-      _GLIBCXX_SIMD_INTRINSIC static void
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
       _S_masked_assign(const _MaskMember __bits, _SimdTuple<_Tp, _As...>& __lhs,
 		       const __type_identity_t<_Tp> __rhs)
       {
 	__for_each(
-	  __lhs, [&](auto __meta, auto& __native_lhs) constexpr {
+	  __lhs, [&](auto __meta, auto& __native_lhs) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __meta._S_masked_assign(__meta._S_make_mask(__bits), __native_lhs,
 				    __rhs);
 	  });
@@ -1777,28 +1752,28 @@ template <int _Np, typename>
 
     // _S_masked_cassign {{{2
     template <typename _Op, typename _Tp, typename... _As>
-      static inline void _S_masked_cassign(const _MaskMember __bits,
-					   _SimdTuple<_Tp, _As...>& __lhs,
-					   const _SimdTuple<_Tp, _As...>& __rhs,
-					   _Op __op)
+      static constexpr inline void
+      _S_masked_cassign(const _MaskMember __bits, _SimdTuple<_Tp, _As...>& __lhs,
+			const _SimdTuple<_Tp, _As...>& __rhs, _Op __op)
       {
-	__for_each(
-	  __lhs, __rhs,
-	  [&](auto __meta, auto& __native_lhs, auto __native_rhs) constexpr {
-	    __meta.template _S_masked_cassign(__meta._S_make_mask(__bits),
-					      __native_lhs, __native_rhs, __op);
-	  });
+	__for_each(__lhs, __rhs,
+		   [&](auto __meta, auto& __native_lhs, auto __native_rhs)
+		     constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+		   {
+		     __meta.template _S_masked_cassign(__meta._S_make_mask(__bits),
+						       __native_lhs, __native_rhs, __op);
+		   });
       }
 
     // Optimization for the case where the RHS is a scalar. No need to broadcast
     // the scalar to a simd first.
     template <typename _Op, typename _Tp, typename... _As>
-      static inline void _S_masked_cassign(const _MaskMember __bits,
-					   _SimdTuple<_Tp, _As...>& __lhs,
-					   const _Tp& __rhs, _Op __op)
+      static constexpr inline void
+      _S_masked_cassign(const _MaskMember __bits, _SimdTuple<_Tp, _As...>& __lhs,
+			const _Tp& __rhs, _Op __op)
       {
 	__for_each(
-	  __lhs, [&](auto __meta, auto& __native_lhs) constexpr {
+	  __lhs, [&](auto __meta, auto& __native_lhs) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	    __meta.template _S_masked_cassign(__meta._S_make_mask(__bits),
 					      __native_lhs, __rhs, __op);
 	  });
@@ -1806,7 +1781,7 @@ template <int _Np, typename>
 
     // _S_masked_unary {{{2
     template <template <typename> class _Op, typename _Tp, typename... _As>
-      static inline _SimdTuple<_Tp, _As...>
+      static constexpr inline _SimdTuple<_Tp, _As...>
       _S_masked_unary(const _MaskMember __bits, const _SimdTuple<_Tp, _As...>& __v)
       {
 	return __v._M_apply_wrapped([&__bits](auto __meta,
@@ -1853,6 +1828,13 @@ template <int _Np, typename>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
       _S_load(const bool* __mem)
       {
+	if (__builtin_is_constant_evaluated())
+	  {
+	    _MaskMember __r{};
+	    for (size_t __i = 0; __i < _Np; ++__i)
+	      __r.set(__i, __mem[__i]);
+	    return __r;
+	  }
 	using _Ip = __int_for_sizeof_t<bool>;
 	// the following load uses element_aligned and relies on __mem already
 	// carrying alignment information from when this load function was
@@ -1888,18 +1870,19 @@ template <int _Np, typename>
     // }}}
     // _S_from_bitmask {{{2
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
       _S_from_bitmask(_MaskMember __bits, _TypeTag<_Tp>) noexcept
       { return __bits; }
 
     // _S_load {{{2
-    static inline _MaskMember _S_load(const bool* __mem) noexcept
+    static constexpr inline _MaskMember
+    _S_load(const bool* __mem) noexcept
     {
       // TODO: _UChar is not necessarily the best type to use here. For smaller
       // _Np _UShort, _UInt, _ULLong, float, and double can be more efficient.
       _ULLong __r = 0;
       using _Vs = __fixed_size_storage_t<_UChar, _Np>;
-      __for_each(_Vs{}, [&](auto __meta, auto) {
+      __for_each(_Vs{}, [&](auto __meta, auto) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	__r |= __meta._S_mask_to_shifted_ullong(
 	  __meta._S_mask_impl._S_load(&__mem[__meta._S_offset],
 				      _SizeConstant<__meta._S_size()>()));
@@ -1908,19 +1891,19 @@ template <int _Np, typename>
     }
 
     // _S_masked_load {{{2
-    static inline _MaskMember _S_masked_load(_MaskMember __merge,
-					     _MaskMember __mask,
-					     const bool* __mem) noexcept
+    static constexpr inline _MaskMember
+    _S_masked_load(_MaskMember __merge, _MaskMember __mask, const bool* __mem) noexcept
     {
-      _BitOps::_S_bit_iteration(__mask.to_ullong(), [&](auto __i) {
-	__merge.set(__i, __mem[__i]);
-      });
+      _BitOps::_S_bit_iteration(__mask.to_ullong(),
+				[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+				  __merge.set(__i, __mem[__i]);
+				});
       return __merge;
     }
 
     // _S_store {{{2
-    static inline void _S_store(const _MaskMember __bitmask,
-				bool* __mem) noexcept
+    static constexpr inline void
+    _S_store(const _MaskMember __bitmask, bool* __mem) noexcept
     {
       if constexpr (_Np == 1)
 	__mem[0] = __bitmask[0];
@@ -1929,18 +1912,19 @@ template <int _Np, typename>
     }
 
     // _S_masked_store {{{2
-    static inline void _S_masked_store(const _MaskMember __v, bool* __mem,
-				       const _MaskMember __k) noexcept
+    static constexpr inline void
+    _S_masked_store(const _MaskMember __v, bool* __mem, const _MaskMember __k) noexcept
     {
-      _BitOps::_S_bit_iteration(__k, [&](auto __i) { __mem[__i] = __v[__i]; });
+      _BitOps::_S_bit_iteration(
+	__k, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA { __mem[__i] = __v[__i]; });
     }
 
     // logical and bitwise operators {{{2
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
     _S_logical_and(const _MaskMember& __x, const _MaskMember& __y) noexcept
     { return __x & __y; }
 
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
     _S_logical_or(const _MaskMember& __x, const _MaskMember& __y) noexcept
     { return __x | __y; }
 
@@ -1948,33 +1932,31 @@ template <int _Np, typename>
     _S_bit_not(const _MaskMember& __x) noexcept
     { return ~__x; }
 
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
     _S_bit_and(const _MaskMember& __x, const _MaskMember& __y) noexcept
     { return __x & __y; }
 
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
     _S_bit_or(const _MaskMember& __x, const _MaskMember& __y) noexcept
     { return __x | __y; }
 
-    _GLIBCXX_SIMD_INTRINSIC static _MaskMember
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
     _S_bit_xor(const _MaskMember& __x, const _MaskMember& __y) noexcept
     { return __x ^ __y; }
 
     // smart_reference access {{{2
-    _GLIBCXX_SIMD_INTRINSIC static void _S_set(_MaskMember& __k, int __i,
-					       bool __x) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
+    _S_set(_MaskMember& __k, int __i, bool __x) noexcept
     { __k.set(__i, __x); }
 
     // _S_masked_assign {{{2
-    _GLIBCXX_SIMD_INTRINSIC static void
-    _S_masked_assign(const _MaskMember __k, _MaskMember& __lhs,
-		     const _MaskMember __rhs)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
+    _S_masked_assign(const _MaskMember __k, _MaskMember& __lhs, const _MaskMember __rhs)
     { __lhs = (__lhs & ~__k) | (__rhs & __k); }
 
     // Optimization for the case where the RHS is a scalar.
-    _GLIBCXX_SIMD_INTRINSIC static void _S_masked_assign(const _MaskMember __k,
-							 _MaskMember& __lhs,
-							 const bool __rhs)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
+    _S_masked_assign(const _MaskMember __k, _MaskMember& __lhs, const bool __rhs)
     {
       if (__rhs)
 	__lhs |= __k;
@@ -1985,25 +1967,28 @@ template <int _Np, typename>
     // }}}2
     // _S_all_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_all_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+      _S_all_of(simd_mask<_Tp, _Abi> __k)
       { return __data(__k).all(); }
 
     // }}}
     // _S_any_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_any_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+      _S_any_of(simd_mask<_Tp, _Abi> __k)
       { return __data(__k).any(); }
 
     // }}}
     // _S_none_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_none_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+      _S_none_of(simd_mask<_Tp, _Abi> __k)
       { return __data(__k).none(); }
 
     // }}}
     // _S_some_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool
+      _GLIBCXX_SIMD_INTRINSIC static constexpr bool
       _S_some_of([[maybe_unused]] simd_mask<_Tp, _Abi> __k)
       {
 	if constexpr (_Np == 1)
@@ -2015,20 +2000,21 @@ template <int _Np, typename>
     // }}}
     // _S_popcount {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static int _S_popcount(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static constexpr int
+      _S_popcount(simd_mask<_Tp, _Abi> __k)
       { return __data(__k).count(); }
 
     // }}}
     // _S_find_first_set {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static int
+      _GLIBCXX_SIMD_INTRINSIC static constexpr int
       _S_find_first_set(simd_mask<_Tp, _Abi> __k)
       { return std::__countr_zero(__data(__k).to_ullong()); }
 
     // }}}
     // _S_find_last_set {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static int
+      _GLIBCXX_SIMD_INTRINSIC static constexpr int
       _S_find_last_set(simd_mask<_Tp, _Abi> __k)
       { return std::__bit_width(__data(__k).to_ullong()) - 1; }
 
--- a/src/libstdc++-v3/include/experimental/bits/simd_math.h
+++ b/src/libstdc++-v3/include/experimental/bits/simd_math.h
@@ -788,7 +788,7 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
 
 	// __exponent(__x) returns the exponent value (bias removed) as
 	// simd<_Up> with integral _Up
-	auto&& __exponent = [](const _V& __v) {
+	auto&& __exponent = [](const _V& __v) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  using namespace std::experimental::__proposed;
 	  using _IV = rebind_simd_t<
 	    conditional_t<sizeof(_Tp) == sizeof(_LLong), _LLong, int>, _V>;
@@ -931,7 +931,7 @@ template <typename _R, typename _ToApply, typename _Tp, typename... _Tps>
   {
     return {__private_init,
 	    __data(__arg0)._M_apply_per_chunk(
-	      [&](auto __impl, const auto&... __inner) {
+	      [&](auto __impl, const auto&... __inner) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		using _V = typename decltype(__impl)::simd_type;
 		return __data(__apply(_V(__private_init, __inner)...));
 	      },
@@ -1092,8 +1092,9 @@ _GLIBCXX_SIMD_CVTING2(hypot)
     if constexpr (__is_fixed_size_abi_v<_Abi> && _V::size() > 1)
       {
 	return __fixed_size_apply<simd<_Tp, _Abi>>(
-	  [](auto __a, auto __b, auto __c) { return hypot(__a, __b, __c); },
-	  __x, __y, __z);
+		 [](auto __a, auto __b, auto __c) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return hypot(__a, __b, __c);
+		 }, __x, __y, __z);
       }
     else
       {
@@ -1380,9 +1381,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
 		 const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __m,
 		 const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>([&](auto __i) {
-      return std::assoc_laguerre(__n[__i], __m[__i], __x[__i]);
-    });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::assoc_laguerre(__n[__i], __m[__i], __x[__i]);
+	   });
   }
 
 template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
@@ -1391,9 +1392,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
 		 const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __m,
 		 const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>([&](auto __i) {
-      return std::assoc_legendre(__n[__i], __m[__i], __x[__i]);
-    });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::assoc_legendre(__n[__i], __m[__i], __x[__i]);
+	   });
   }
 
 _GLIBCXX_SIMD_MATH_CALL2_(beta, _Tp)
@@ -1414,8 +1415,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
   hermite(const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __n,
 	  const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>(
-      [&](auto __i) { return std::hermite(__n[__i], __x[__i]); });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::hermite(__n[__i], __x[__i]);
+	   });
   }
 
 template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
@@ -1423,8 +1425,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
   laguerre(const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __n,
 	   const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>(
-      [&](auto __i) { return std::laguerre(__n[__i], __x[__i]); });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::laguerre(__n[__i], __x[__i]);
+	   });
   }
 
 template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
@@ -1432,8 +1435,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
   legendre(const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __n,
 	   const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>(
-      [&](auto __i) { return std::legendre(__n[__i], __x[__i]); });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::legendre(__n[__i], __x[__i]);
+	   });
   }
 
 _GLIBCXX_SIMD_MATH_CALL_(riemann_zeta)
@@ -1443,8 +1447,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
   sph_bessel(const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __n,
 	     const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>(
-      [&](auto __i) { return std::sph_bessel(__n[__i], __x[__i]); });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::sph_bessel(__n[__i], __x[__i]);
+	   });
   }
 
 template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
@@ -1453,9 +1458,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
 	       const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __m,
 	       const simd<_Tp, _Abi>& theta)
   {
-    return simd<_Tp, _Abi>([&](auto __i) {
-      return std::assoc_legendre(__l[__i], __m[__i], theta[__i]);
-    });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::assoc_legendre(__l[__i], __m[__i], theta[__i]);
+	   });
   }
 
 template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
@@ -1463,8 +1468,9 @@ template <typename _Tp, typename _Abi, typename = __detail::__odr_helper>
   sph_neumann(const fixed_size_simd<unsigned, simd_size_v<_Tp, _Abi>>& __n,
 	      const simd<_Tp, _Abi>& __x)
   {
-    return simd<_Tp, _Abi>(
-      [&](auto __i) { return std::sph_neumann(__n[__i], __x[__i]); });
+    return simd<_Tp, _Abi>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+	     return std::sph_neumann(__n[__i], __x[__i]);
+	   });
   }
 // }}}
 
--- a/src/libstdc++-v3/include/experimental/bits/simd_neon.h
+++ b/src/libstdc++-v3/include/experimental/bits/simd_neon.h
@@ -61,7 +61,7 @@ template <typename _Abi, typename>
       _S_masked_load(_SimdWrapper<_Tp, _Np> __merge, _MaskMember<_Tp> __k,
 		     const _Up* __mem) noexcept
       {
-	__execute_n_times<_Np>([&](auto __i) {
+	__execute_n_times<_Np>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  if (__k[__i] != 0)
 	    __merge._M_set(__i, static_cast<_Tp>(__mem[__i]));
 	});
@@ -75,7 +75,7 @@ template <typename _Abi, typename>
       _S_masked_store_nocvt(_SimdWrapper<_Tp, _Np> __v, _Tp* __mem,
 			    _MaskMember<_Tp> __k)
       {
-	__execute_n_times<_Np>([&](auto __i) {
+	__execute_n_times<_Np>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  if (__k[__i] != 0)
 	    __mem[__i] = __v[__i];
 	});
@@ -84,57 +84,54 @@ template <typename _Abi, typename>
     // }}}
     // _S_reduce {{{
     template <typename _Tp, typename _BinaryOperation>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
       _S_reduce(simd<_Tp, _Abi> __x, _BinaryOperation&& __binary_op)
       {
-	constexpr size_t _Np = __x.size();
-	if constexpr (sizeof(__x) == 16 && _Np >= 4
-		      && !_Abi::template _S_is_partial<_Tp>)
-	  {
-	    const auto __halves = split<simd<_Tp, simd_abi::_Neon<8>>>(__x);
-	    const auto __y = __binary_op(__halves[0], __halves[1]);
-	    return _SimdImplNeon<simd_abi::_Neon<8>>::_S_reduce(
-	      __y, static_cast<_BinaryOperation&&>(__binary_op));
-	  }
-	else if constexpr (_Np == 8)
-	  {
-	    __x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
-				     __vector_permute<1, 0, 3, 2, 5, 4, 7, 6>(
-				       __x._M_data)));
-	    __x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
-				     __vector_permute<3, 2, 1, 0, 7, 6, 5, 4>(
-				       __x._M_data)));
-	    __x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
-				     __vector_permute<7, 6, 5, 4, 3, 2, 1, 0>(
-				       __x._M_data)));
-	    return __x[0];
-	  }
-	else if constexpr (_Np == 4)
-	  {
-	    __x
-	      = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
-				   __vector_permute<1, 0, 3, 2>(__x._M_data)));
-	    __x
-	      = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
-				   __vector_permute<3, 2, 1, 0>(__x._M_data)));
-	    return __x[0];
-	  }
-	else if constexpr (_Np == 2)
+	if (not __builtin_is_constant_evaluated())
 	  {
-	    __x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
-				     __vector_permute<1, 0>(__x._M_data)));
-	    return __x[0];
+	    constexpr size_t _Np = __x.size();
+	    if constexpr (sizeof(__x) == 16 && _Np >= 4
+			    && !_Abi::template _S_is_partial<_Tp>)
+	      {
+		const auto __halves = split<simd<_Tp, simd_abi::_Neon<8>>>(__x);
+		const auto __y = __binary_op(__halves[0], __halves[1]);
+		return _SimdImplNeon<simd_abi::_Neon<8>>::_S_reduce(
+			 __y, static_cast<_BinaryOperation&&>(__binary_op));
+	      }
+	    else if constexpr (_Np == 8)
+	      {
+		__x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
+					 __vector_permute<1, 0, 3, 2, 5, 4, 7, 6>(__x._M_data)));
+		__x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
+					 __vector_permute<3, 2, 1, 0, 7, 6, 5, 4>(__x._M_data)));
+		__x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
+					 __vector_permute<7, 6, 5, 4, 3, 2, 1, 0>(__x._M_data)));
+		return __x[0];
+	      }
+	    else if constexpr (_Np == 4)
+	      {
+		__x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
+					 __vector_permute<1, 0, 3, 2>(__x._M_data)));
+		__x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
+					 __vector_permute<3, 2, 1, 0>(__x._M_data)));
+		return __x[0];
+	      }
+	    else if constexpr (_Np == 2)
+	      {
+		__x = __binary_op(__x, _Base::template _M_make_simd<_Tp, _Np>(
+					 __vector_permute<1, 0>(__x._M_data)));
+		return __x[0];
+	      }
 	  }
-	else
-	  return _Base::_S_reduce(__x,
-				  static_cast<_BinaryOperation&&>(__binary_op));
+	return _Base::_S_reduce(__x, static_cast<_BinaryOperation&&>(__binary_op));
       }
 
     // }}}
     // math {{{
     // _S_sqrt {{{
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp _S_sqrt(_Tp __x)
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_sqrt(_Tp __x)
       {
 	if constexpr (__have_neon_a64)
 	  {
@@ -157,7 +154,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_trunc {{{
     template <typename _TW, typename _TVT = _VectorTraits<_TW>>
-      _GLIBCXX_SIMD_INTRINSIC static _TW _S_trunc(_TW __x)
+      _GLIBCXX_SIMD_INTRINSIC static _TW
+      _S_trunc(_TW __x)
       {
 	using _Tp = typename _TVT::value_type;
 	if constexpr (__have_neon_a32)
@@ -216,7 +214,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_floor {{{
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp _S_floor(_Tp __x)
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_floor(_Tp __x)
       {
 	if constexpr (__have_neon_a32)
 	  {
@@ -239,7 +238,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_ceil {{{
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp _S_ceil(_Tp __x)
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_ceil(_Tp __x)
       {
 	if constexpr (__have_neon_a32)
 	  {
@@ -286,7 +286,7 @@ struct _MaskImplNeonMixin
 	    {
 	      constexpr auto __bitsel
 		= __generate_from_n_evaluations<16, __vector_type_t<_I, 16>>(
-		  [&](auto __i) {
+		  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		    return static_cast<_I>(
 		      __i < _Np ? (__i < 8 ? 1 << __i : 1 << (__i - 8)) : 0);
 		  });
@@ -306,7 +306,7 @@ struct _MaskImplNeonMixin
 	    {
 	      constexpr auto __bitsel
 		= __generate_from_n_evaluations<8, __vector_type_t<_I, 8>>(
-		  [&](auto __i) {
+		  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		    return static_cast<_I>(__i < _Np ? 1 << __i : 0);
 		  });
 	      __asint &= __bitsel;
@@ -322,7 +322,7 @@ struct _MaskImplNeonMixin
 	    {
 	      constexpr auto __bitsel
 		= __generate_from_n_evaluations<4, __vector_type_t<_I, 4>>(
-		  [&](auto __i) {
+		  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		    return static_cast<_I>(__i < _Np ? 1 << __i : 0);
 		  });
 	      __asint &= __bitsel;
@@ -346,7 +346,7 @@ struct _MaskImplNeonMixin
 	    {
 	      constexpr auto __bitsel
 		= __generate_from_n_evaluations<8, __vector_type_t<_I, 8>>(
-		  [&](auto __i) {
+		  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		    return static_cast<_I>(__i < _Np ? 1 << __i : 0);
 		  });
 	      __asint &= __bitsel;
@@ -361,7 +361,7 @@ struct _MaskImplNeonMixin
 	    {
 	      constexpr auto __bitsel
 		= __generate_from_n_evaluations<4, __vector_type_t<_I, 4>>(
-		  [&](auto __i) {
+		  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		    return static_cast<_I>(__i < _Np ? 1 << __i : 0);
 		  });
 	      __asint &= __bitsel;
@@ -400,7 +400,8 @@ template <typename _Abi, typename>
 
     // _S_all_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_all_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_all_of(simd_mask<_Tp, _Abi> __k)
       {
 	const auto __kk
 	  = __vector_bitcast<char>(__k._M_data)
@@ -419,7 +420,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_any_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_any_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_any_of(simd_mask<_Tp, _Abi> __k)
       {
 	const auto __kk
 	  = __vector_bitcast<char>(__k._M_data)
@@ -438,7 +440,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_none_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_none_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_none_of(simd_mask<_Tp, _Abi> __k)
       {
 	const auto __kk = _Abi::_S_masked(__k._M_data);
 	if constexpr (sizeof(__k) == 16)
@@ -472,7 +475,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_popcount {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static int _S_popcount(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static int
+      _S_popcount(simd_mask<_Tp, _Abi> __k)
       {
 	if constexpr (sizeof(_Tp) == 1)
 	  {
--- a/src/libstdc++-v3/include/experimental/bits/simd_ppc.h
+++ b/src/libstdc++-v3/include/experimental/bits/simd_ppc.h
@@ -64,7 +64,7 @@ template <typename _Abi, typename>
 	__x = _Base::_S_bit_shift_left(__x, __y);
 	if constexpr (sizeof(_Tp) < sizeof(int))
 	  {
-	    if (__y >= sizeof(_Tp) * __CHAR_BIT__)
+	    if (__y >= int(sizeof(_Tp) * __CHAR_BIT__))
 	      return {};
 	  }
 	return __x;
@@ -124,12 +124,14 @@ template <typename _Abi, typename>
 
     // _S_popcount {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static int _S_popcount(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static int
+      _S_popcount(simd_mask<_Tp, _Abi> __k)
       {
 	const auto __kv = __as_vector(__k);
 	if constexpr (__have_power10vec)
 	  {
-	    return vec_cntm(__to_intrin(__kv), 1);
+	    using _Intrin = __intrinsic_type16_t<make_unsigned_t<__int_for_sizeof_t<_Tp>>>;
+	    return vec_cntm(reinterpret_cast<_Intrin>(__kv), 1);
 	  }
 	else if constexpr (sizeof(_Tp) >= sizeof(int))
 	  {
--- a/src/libstdc++-v3/include/experimental/bits/simd_scalar.h
+++ b/src/libstdc++-v3/include/experimental/bits/simd_scalar.h
@@ -74,7 +74,8 @@ struct simd_abi::_Scalar
   template <typename _Tp>
     static constexpr bool _S_is_valid_v = _IsValid<_Tp>::value;
 
-  _GLIBCXX_SIMD_INTRINSIC static constexpr bool _S_masked(bool __x)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_masked(bool __x)
   { return __x; }
 
   using _CommonImpl = _CommonImplScalar;
@@ -110,7 +111,8 @@ struct _CommonImplScalar
 {
   // _S_store {{{
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static void _S_store(_Tp __x, void* __addr)
+    _GLIBCXX_SIMD_INTRINSIC static void
+    _S_store(_Tp __x, void* __addr)
     { __builtin_memcpy(__addr, &__x, sizeof(_Tp)); }
 
   // }}}
@@ -138,26 +140,26 @@ struct _SimdImplScalar
 
   // _S_broadcast {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp _S_broadcast(_Tp __x) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_broadcast(_Tp __x) noexcept
     { return __x; }
 
   // _S_generator {{{2
   template <typename _Fp, typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp _S_generator(_Fp&& __gen,
-							      _TypeTag<_Tp>)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_generator(_Fp&& __gen, _TypeTag<_Tp>)
     { return __gen(_SizeConstant<0>()); }
 
   // _S_load {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_load(const _Up* __mem,
-					       _TypeTag<_Tp>) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_load(const _Up* __mem, _TypeTag<_Tp>) noexcept
     { return static_cast<_Tp>(__mem[0]); }
 
   // _S_masked_load {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC
-    static _Tp _S_masked_load(_Tp __merge, bool __k,
-				     const _Up* __mem) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_masked_load(_Tp __merge, bool __k, const _Up* __mem) noexcept
     {
       if (__k)
 	__merge = static_cast<_Tp>(__mem[0]);
@@ -166,97 +168,95 @@ struct _SimdImplScalar
 
   // _S_store {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC
-    static void _S_store(_Tp __v, _Up* __mem, _TypeTag<_Tp>) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
+    _S_store(_Tp __v, _Up* __mem, _TypeTag<_Tp>) noexcept
     { __mem[0] = static_cast<_Up>(__v); }
 
   // _S_masked_store {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC
-    static void _S_masked_store(const _Tp __v, _Up* __mem,
-				       const bool __k) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
+    _S_masked_store(const _Tp __v, _Up* __mem, const bool __k) noexcept
     { if (__k) __mem[0] = __v; }
 
   // _S_negate {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr bool _S_negate(_Tp __x) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_negate(_Tp __x) noexcept
     { return !__x; }
 
   // _S_reduce {{{2
   template <typename _Tp, typename _BinaryOperation>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
     _S_reduce(const simd<_Tp, simd_abi::scalar>& __x, const _BinaryOperation&)
     { return __x._M_data; }
 
   // _S_min, _S_max {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_min(const _Tp __a, const _Tp __b)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_min(const _Tp __a, const _Tp __b)
     { return std::min(__a, __b); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_max(const _Tp __a, const _Tp __b)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_max(const _Tp __a, const _Tp __b)
     { return std::max(__a, __b); }
 
   // _S_complement {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_complement(_Tp __x) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_complement(_Tp __x) noexcept
     { return static_cast<_Tp>(~__x); }
 
   // _S_unary_minus {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_unary_minus(_Tp __x) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_unary_minus(_Tp __x) noexcept
     { return static_cast<_Tp>(-__x); }
 
   // arithmetic operators {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_plus(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_plus(_Tp __x, _Tp __y)
     {
       return static_cast<_Tp>(__promote_preserving_unsigned(__x)
 			      + __promote_preserving_unsigned(__y));
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_minus(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_minus(_Tp __x, _Tp __y)
     {
       return static_cast<_Tp>(__promote_preserving_unsigned(__x)
 			      - __promote_preserving_unsigned(__y));
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_multiplies(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_multiplies(_Tp __x, _Tp __y)
     {
       return static_cast<_Tp>(__promote_preserving_unsigned(__x)
 			      * __promote_preserving_unsigned(__y));
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_divides(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_divides(_Tp __x, _Tp __y)
     {
       return static_cast<_Tp>(__promote_preserving_unsigned(__x)
 			      / __promote_preserving_unsigned(__y));
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_modulus(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_modulus(_Tp __x, _Tp __y)
     {
       return static_cast<_Tp>(__promote_preserving_unsigned(__x)
 			      % __promote_preserving_unsigned(__y));
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_bit_and(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_bit_and(_Tp __x, _Tp __y)
     {
       if constexpr (is_floating_point_v<_Tp>)
 	{
@@ -269,8 +269,8 @@ struct _SimdImplScalar
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_bit_or(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_bit_or(_Tp __x, _Tp __y)
     {
       if constexpr (is_floating_point_v<_Tp>)
 	{
@@ -283,8 +283,8 @@ struct _SimdImplScalar
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_bit_xor(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_bit_xor(_Tp __x, _Tp __y)
     {
       if constexpr (is_floating_point_v<_Tp>)
 	{
@@ -297,13 +297,13 @@ struct _SimdImplScalar
     }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_bit_shift_left(_Tp __x, int __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_bit_shift_left(_Tp __x, int __y)
     { return static_cast<_Tp>(__promote_preserving_unsigned(__x) << __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    static constexpr _Tp _S_bit_shift_right(_Tp __x, int __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_bit_shift_right(_Tp __x, int __y)
     { return static_cast<_Tp>(__promote_preserving_unsigned(__x) >> __y); }
 
   // math {{{2
@@ -312,300 +312,362 @@ struct _SimdImplScalar
     using _ST = _SimdTuple<_Tp, simd_abi::scalar>;
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_acos(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_acos(_Tp __x)
     { return std::acos(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_asin(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_asin(_Tp __x)
     { return std::asin(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_atan(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_atan(_Tp __x)
     { return std::atan(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_cos(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_cos(_Tp __x)
     { return std::cos(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_sin(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_sin(_Tp __x)
     { return std::sin(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_tan(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_tan(_Tp __x)
     { return std::tan(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_acosh(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_acosh(_Tp __x)
     { return std::acosh(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_asinh(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_asinh(_Tp __x)
     { return std::asinh(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_atanh(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_atanh(_Tp __x)
     { return std::atanh(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_cosh(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_cosh(_Tp __x)
     { return std::cosh(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_sinh(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_sinh(_Tp __x)
     { return std::sinh(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_tanh(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_tanh(_Tp __x)
     { return std::tanh(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_atan2(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_atan2(_Tp __x, _Tp __y)
     { return std::atan2(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_exp(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_exp(_Tp __x)
     { return std::exp(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_exp2(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_exp2(_Tp __x)
     { return std::exp2(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_expm1(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_expm1(_Tp __x)
     { return std::expm1(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_log(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_log(_Tp __x)
     { return std::log(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_log10(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_log10(_Tp __x)
     { return std::log10(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_log1p(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_log1p(_Tp __x)
     { return std::log1p(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_log2(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_log2(_Tp __x)
     { return std::log2(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_logb(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_logb(_Tp __x)
     { return std::logb(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _ST<int> _S_ilogb(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _ST<int>
+    _S_ilogb(_Tp __x)
     { return {std::ilogb(__x)}; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_pow(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_pow(_Tp __x, _Tp __y)
     { return std::pow(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_abs(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_abs(_Tp __x)
     { return std::abs(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_fabs(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_fabs(_Tp __x)
     { return std::fabs(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_sqrt(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_sqrt(_Tp __x)
     { return std::sqrt(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_cbrt(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_cbrt(_Tp __x)
     { return std::cbrt(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_erf(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_erf(_Tp __x)
     { return std::erf(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_erfc(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_erfc(_Tp __x)
     { return std::erfc(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_lgamma(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_lgamma(_Tp __x)
     { return std::lgamma(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_tgamma(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_tgamma(_Tp __x)
     { return std::tgamma(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_trunc(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_trunc(_Tp __x)
     { return std::trunc(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_floor(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_floor(_Tp __x)
     { return std::floor(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_ceil(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_ceil(_Tp __x)
     { return std::ceil(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_nearbyint(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_nearbyint(_Tp __x)
     { return std::nearbyint(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_rint(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_rint(_Tp __x)
     { return std::rint(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _ST<long> _S_lrint(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _ST<long>
+    _S_lrint(_Tp __x)
     { return {std::lrint(__x)}; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _ST<long long> _S_llrint(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _ST<long long>
+    _S_llrint(_Tp __x)
     { return {std::llrint(__x)}; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_round(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_round(_Tp __x)
     { return std::round(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _ST<long> _S_lround(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _ST<long>
+    _S_lround(_Tp __x)
     { return {std::lround(__x)}; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _ST<long long> _S_llround(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static _ST<long long>
+    _S_llround(_Tp __x)
     { return {std::llround(__x)}; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_ldexp(_Tp __x, _ST<int> __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_ldexp(_Tp __x, _ST<int> __y)
     { return std::ldexp(__x, __y.first); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_scalbn(_Tp __x, _ST<int> __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_scalbn(_Tp __x, _ST<int> __y)
     { return std::scalbn(__x, __y.first); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_scalbln(_Tp __x, _ST<long> __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_scalbln(_Tp __x, _ST<long> __y)
     { return std::scalbln(__x, __y.first); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_fmod(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_fmod(_Tp __x, _Tp __y)
     { return std::fmod(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_remainder(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_remainder(_Tp __x, _Tp __y)
     { return std::remainder(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_nextafter(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_nextafter(_Tp __x, _Tp __y)
     { return std::nextafter(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_fdim(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_fdim(_Tp __x, _Tp __y)
     { return std::fdim(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_fmax(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_fmax(_Tp __x, _Tp __y)
     { return std::fmax(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_fmin(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_fmin(_Tp __x, _Tp __y)
     { return std::fmin(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_fma(_Tp __x, _Tp __y, _Tp __z)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_fma(_Tp __x, _Tp __y, _Tp __z)
     { return std::fma(__x, __y, __z); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_remquo(_Tp __x, _Tp __y, _ST<int>* __z)
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_remquo(_Tp __x, _Tp __y, _ST<int>* __z)
     { return std::remquo(__x, __y, &__z->first); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static _ST<int> _S_fpclassify(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _ST<int>
+    _S_fpclassify(_Tp __x)
     { return {std::fpclassify(__x)}; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isfinite(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_isfinite(_Tp __x)
     { return std::isfinite(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isinf(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_isinf(_Tp __x)
     { return std::isinf(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isnan(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_isnan(_Tp __x)
     { return std::isnan(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isnormal(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_isnormal(_Tp __x)
     { return std::isnormal(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_signbit(_Tp __x)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_signbit(_Tp __x)
     { return std::signbit(__x); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isgreater(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_isgreater(_Tp __x, _Tp __y)
     { return std::isgreater(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isgreaterequal(_Tp __x,
-								    _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_isgreaterequal(_Tp __x, _Tp __y)
     { return std::isgreaterequal(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isless(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_isless(_Tp __x, _Tp __y)
     { return std::isless(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_islessequal(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_islessequal(_Tp __x, _Tp __y)
     { return std::islessequal(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_islessgreater(_Tp __x,
-								   _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_islessgreater(_Tp __x, _Tp __y)
     { return std::islessgreater(__x, __y); }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_isunordered(_Tp __x,
-								 _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_isunordered(_Tp __x, _Tp __y)
     { return std::isunordered(__x, __y); }
 
   // _S_increment & _S_decrement{{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    constexpr static void _S_increment(_Tp& __x)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
+    _S_increment(_Tp& __x)
     { ++__x; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC
-    constexpr static void _S_decrement(_Tp& __x)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
+    _S_decrement(_Tp& __x)
     { --__x; }
 
 
   // compares {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_equal_to(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_equal_to(_Tp __x, _Tp __y)
     { return __x == __y; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_not_equal_to(_Tp __x,
-								  _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_not_equal_to(_Tp __x, _Tp __y)
     { return __x != __y; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_less(_Tp __x, _Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_less(_Tp __x, _Tp __y)
     { return __x < __y; }
 
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool _S_less_equal(_Tp __x,
-								_Tp __y)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_less_equal(_Tp __x, _Tp __y)
     { return __x <= __y; }
 
   // smart_reference access {{{2
   template <typename _Tp, typename _Up>
-    _GLIBCXX_SIMD_INTRINSIC
-    constexpr static void _S_set(_Tp& __v, [[maybe_unused]] int __i,
-				 _Up&& __x) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
+    _S_set(_Tp& __v, [[maybe_unused]] int __i, _Up&& __x) noexcept
     {
       _GLIBCXX_DEBUG_ASSERT(__i == 0);
       __v = static_cast<_Up&&>(__x);
@@ -613,20 +675,20 @@ struct _SimdImplScalar
 
   // _S_masked_assign {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static void
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_masked_assign(bool __k, _Tp& __lhs, _Tp __rhs)
     { if (__k) __lhs = __rhs; }
 
   // _S_masked_cassign {{{2
   template <typename _Op, typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static void
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_masked_cassign(const bool __k, _Tp& __lhs, const _Tp __rhs, _Op __op)
     { if (__k) __lhs = __op(_SimdImplScalar{}, __lhs, __rhs); }
 
   // _S_masked_unary {{{2
   template <template <typename> class _Op, typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static _Tp _S_masked_unary(const bool __k,
-								 const _Tp __v)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
+    _S_masked_unary(const bool __k, const _Tp __v)
     { return static_cast<_Tp>(__k ? _Op<_Tp>{}(__v) : __v); }
 
   // }}}2
@@ -643,13 +705,15 @@ struct _MaskImplScalar
   // }}}
   // _S_broadcast {{{
   template <typename>
-    _GLIBCXX_SIMD_INTRINSIC static constexpr bool _S_broadcast(bool __x)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_broadcast(bool __x)
     { return __x; }
 
   // }}}
   // _S_load {{{
   template <typename>
-    _GLIBCXX_SIMD_INTRINSIC static constexpr bool _S_load(const bool* __mem)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+    _S_load(const bool* __mem)
     { return __mem[0]; }
 
   // }}}
@@ -673,12 +737,12 @@ struct _MaskImplScalar
   // }}}
   // _S_from_bitmask {{{2
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_from_bitmask(_SanitizedBitMask<1> __bits, _TypeTag<_Tp>) noexcept
     { return __bits[0]; }
 
   // _S_masked_load {{{2
-  _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
   _S_masked_load(bool __merge, bool __mask, const bool* __mem) noexcept
   {
     if (__mask)
@@ -687,11 +751,12 @@ struct _MaskImplScalar
   }
 
   // _S_store {{{2
-  _GLIBCXX_SIMD_INTRINSIC static void _S_store(bool __v, bool* __mem) noexcept
+  _GLIBCXX_SIMD_INTRINSIC static constexpr void
+  _S_store(bool __v, bool* __mem) noexcept
   { __mem[0] = __v; }
 
   // _S_masked_store {{{2
-  _GLIBCXX_SIMD_INTRINSIC static void
+  _GLIBCXX_SIMD_INTRINSIC static constexpr void
   _S_masked_store(const bool __v, bool* __mem, const bool __k) noexcept
   {
     if (__k)
@@ -699,42 +764,41 @@ struct _MaskImplScalar
   }
 
   // logical and bitwise operators {{{2
-  _GLIBCXX_SIMD_INTRINSIC
-  static constexpr bool _S_logical_and(bool __x, bool __y)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_logical_and(bool __x, bool __y)
   { return __x && __y; }
 
-  _GLIBCXX_SIMD_INTRINSIC
-  static constexpr bool _S_logical_or(bool __x, bool __y)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_logical_or(bool __x, bool __y)
   { return __x || __y; }
 
-  _GLIBCXX_SIMD_INTRINSIC
-  static constexpr bool _S_bit_not(bool __x)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_bit_not(bool __x)
   { return !__x; }
 
-  _GLIBCXX_SIMD_INTRINSIC
-  static constexpr bool _S_bit_and(bool __x, bool __y)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_bit_and(bool __x, bool __y)
   { return __x && __y; }
 
-  _GLIBCXX_SIMD_INTRINSIC
-  static constexpr bool _S_bit_or(bool __x, bool __y)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_bit_or(bool __x, bool __y)
   { return __x || __y; }
 
-  _GLIBCXX_SIMD_INTRINSIC
-  static constexpr bool _S_bit_xor(bool __x, bool __y)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr bool
+  _S_bit_xor(bool __x, bool __y)
   { return __x != __y; }
 
   // smart_reference access {{{2
-  _GLIBCXX_SIMD_INTRINSIC
-  constexpr static void _S_set(bool& __k, [[maybe_unused]] int __i,
-			       bool __x) noexcept
+  _GLIBCXX_SIMD_INTRINSIC static constexpr void
+  _S_set(bool& __k, [[maybe_unused]] int __i, bool __x) noexcept
   {
     _GLIBCXX_DEBUG_ASSERT(__i == 0);
     __k = __x;
   }
 
   // _S_masked_assign {{{2
-  _GLIBCXX_SIMD_INTRINSIC static void _S_masked_assign(bool __k, bool& __lhs,
-						       bool __rhs)
+  _GLIBCXX_SIMD_INTRINSIC static constexpr void
+  _S_masked_assign(bool __k, bool& __lhs, bool __rhs)
   {
     if (__k)
       __lhs = __rhs;
@@ -743,49 +807,49 @@ struct _MaskImplScalar
   // }}}2
   // _S_all_of {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_all_of(simd_mask<_Tp, _Abi> __k)
     { return __k._M_data; }
 
   // }}}
   // _S_any_of {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_any_of(simd_mask<_Tp, _Abi> __k)
     { return __k._M_data; }
 
   // }}}
   // _S_none_of {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_none_of(simd_mask<_Tp, _Abi> __k)
     { return !__k._M_data; }
 
   // }}}
   // _S_some_of {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static bool
+    _GLIBCXX_SIMD_INTRINSIC static constexpr bool
     _S_some_of(simd_mask<_Tp, _Abi>)
     { return false; }
 
   // }}}
   // _S_popcount {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static int
+    _GLIBCXX_SIMD_INTRINSIC static constexpr int
     _S_popcount(simd_mask<_Tp, _Abi> __k)
     { return __k._M_data; }
 
   // }}}
   // _S_find_first_set {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static int
+    _GLIBCXX_SIMD_INTRINSIC static constexpr int
     _S_find_first_set(simd_mask<_Tp, _Abi>)
     { return 0; }
 
   // }}}
   // _S_find_last_set {{{
   template <typename _Tp, typename _Abi>
-    _GLIBCXX_SIMD_INTRINSIC constexpr static int
+    _GLIBCXX_SIMD_INTRINSIC static constexpr int
     _S_find_last_set(simd_mask<_Tp, _Abi>)
     { return 0; }
 
--- a/src/libstdc++-v3/include/experimental/bits/simd_x86.h
+++ b/src/libstdc++-v3/include/experimental/bits/simd_x86.h
@@ -40,10 +40,7 @@ _GLIBCXX_SIMD_BEGIN_NAMESPACE
 template <typename _Tp, size_t _Np>
   _GLIBCXX_SIMD_INTRINSIC constexpr _SimdWrapper<__int_for_sizeof_t<_Tp>, _Np>
   __to_masktype(_SimdWrapper<_Tp, _Np> __x)
-  {
-    return reinterpret_cast<__vector_type_t<__int_for_sizeof_t<_Tp>, _Np>>(
-      __x._M_data);
-  }
+  { return reinterpret_cast<__vector_type_t<__int_for_sizeof_t<_Tp>, _Np>>(__x._M_data); }
 
 template <typename _TV,
 	  typename _TVT
@@ -366,6 +363,53 @@ template <typename _Tp>
 
 // }}}
 
+#ifdef __clang__
+template <size_t _Np, typename _Tp, typename _Kp>
+  _GLIBCXX_SIMD_INTRINSIC constexpr auto
+  __movm(_Kp __k) noexcept
+  {
+    static_assert(is_unsigned_v<_Kp>);
+    if constexpr (sizeof(_Tp) == 1 && __have_avx512bw)
+      {
+	if constexpr (_Np <= 16 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2b128(__k);
+	else if constexpr (_Np <= 32 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2b256(__k);
+	else
+	  return __builtin_ia32_cvtmask2b512(__k);
+      }
+    else if constexpr (sizeof(_Tp) == 2 && __have_avx512bw)
+      {
+	if constexpr (_Np <= 8 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2w128(__k);
+	else if constexpr (_Np <= 16 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2w256(__k);
+	else
+	  return __builtin_ia32_cvtmask2w512(__k);
+      }
+    else if constexpr (sizeof(_Tp) == 4 && __have_avx512dq)
+      {
+	if constexpr (_Np <= 4 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2d128(__k);
+	else if constexpr (_Np <= 8 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2d256(__k);
+	else
+	  return __builtin_ia32_cvtmask2d512(__k);
+      }
+    else if constexpr (sizeof(_Tp) == 8 && __have_avx512dq)
+      {
+	if constexpr (_Np <= 2 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2q128(__k);
+	else if constexpr (_Np <= 4 && __have_avx512vl)
+	  return __builtin_ia32_cvtmask2q256(__k);
+	else
+	  return __builtin_ia32_cvtmask2q512(__k);
+      }
+    else
+      __assert_unreachable<_Tp>();
+  }
+#endif // __clang__
+
 #ifdef _GLIBCXX_SIMD_WORKAROUND_PR85048
 #include "simd_x86_conversions.h"
 #endif
@@ -434,7 +478,8 @@ struct _CommonImplX86 : _CommonImplBuiltin
 #ifdef _GLIBCXX_SIMD_WORKAROUND_PR85048
   // _S_converts_via_decomposition {{{
   template <typename _From, typename _To, size_t _ToSize>
-    static constexpr bool _S_converts_via_decomposition()
+    static constexpr bool
+    _S_converts_via_decomposition()
     {
       if constexpr (is_integral_v<
 		      _From> && is_integral_v<_To> && sizeof(_From) == 8
@@ -465,12 +510,14 @@ struct _CommonImplX86 : _CommonImplBuiltin
   using _CommonImplBuiltin::_S_store;
 
   template <typename _Tp, size_t _Np>
-    _GLIBCXX_SIMD_INTRINSIC static void _S_store(_SimdWrapper<_Tp, _Np> __x,
-						 void* __addr)
+    _GLIBCXX_SIMD_INTRINSIC static constexpr void
+    _S_store(_SimdWrapper<_Tp, _Np> __x, void* __addr)
     {
       constexpr size_t _Bytes = _Np * sizeof(_Tp);
 
-      if constexpr ((_Bytes & (_Bytes - 1)) != 0 && __have_avx512bw_vl)
+      if (__builtin_is_constant_evaluated())
+	_CommonImplBuiltin::_S_store(__x, __addr);
+      else if constexpr ((_Bytes & (_Bytes - 1)) != 0 && __have_avx512bw_vl)
 	{
 	  const auto __v = __to_intrin(__x);
 
@@ -536,17 +583,20 @@ struct _CommonImplX86 : _CommonImplBuiltin
     _GLIBCXX_SIMD_INTRINSIC static constexpr void
     _S_store_bool_array(const _BitMask<_Np, _Sanitized> __x, bool* __mem)
     {
-      if constexpr (__have_avx512bw_vl) // don't care for BW w/o VL
-	_S_store<_Np>(1 & __vector_bitcast<_UChar, _Np>([=]() constexpr {
-			if constexpr (_Np <= 16)
-			  return _mm_movm_epi8(__x._M_to_bits());
-			else if constexpr (_Np <= 32)
-			  return _mm256_movm_epi8(__x._M_to_bits());
-			else if constexpr (_Np <= 64)
-			  return _mm512_movm_epi8(__x._M_to_bits());
-			else
-			  __assert_unreachable<_SizeConstant<_Np>>();
-		      }()),
+      if (__builtin_is_constant_evaluated())
+	_CommonImplBuiltin::_S_store_bool_array(__x, __mem);
+      else if constexpr (__have_avx512bw_vl) // don't care for BW w/o VL
+	_S_store<_Np>(1 & __vector_bitcast<_UChar, _Np>(
+			    [=]() constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+			      if constexpr (_Np <= 16)
+				return _mm_movm_epi8(__x._M_to_bits());
+			      else if constexpr (_Np <= 32)
+				return _mm256_movm_epi8(__x._M_to_bits());
+			      else if constexpr (_Np <= 64)
+				return _mm512_movm_epi8(__x._M_to_bits());
+			      else
+				__assert_unreachable<_SizeConstant<_Np>>();
+			    }()),
 		      __mem);
       else if constexpr (__have_bmi2)
 	{
@@ -554,7 +604,7 @@ struct _CommonImplX86 : _CommonImplBuiltin
 	    _S_store<_Np>(_pdep_u32(__x._M_to_bits(), 0x01010101U), __mem);
 	  else
 	    __execute_n_times<__div_roundup(_Np, sizeof(size_t))>(
-	      [&](auto __i) {
+	      [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		constexpr size_t __offset = __i * sizeof(size_t);
 		constexpr int __todo = std::min(sizeof(size_t), _Np - __offset);
 		if constexpr (__todo == 1)
@@ -575,7 +625,7 @@ struct _CommonImplX86 : _CommonImplBuiltin
 	      });
 	}
       else if constexpr (__have_sse2 && _Np > 7)
-	__execute_n_times<__div_roundup(_Np, 16)>([&](auto __i) {
+	__execute_n_times<__div_roundup(_Np, 16)>([&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 	  constexpr int __offset = __i * 16;
 	  constexpr int __todo = std::min(16, int(_Np) - __offset);
 	  const int __bits = __x.template _M_extract<__offset>()._M_to_bits();
@@ -620,14 +670,13 @@ struct _CommonImplX86 : _CommonImplBuiltin
     _GLIBCXX_SIMD_INTRINSIC static _TV
     _S_blend_avx512(const _Kp __k, const _TV __a, const _TV __b) noexcept
     {
-#ifdef __clang__
-      // FIXME: this does a boolean choice, not a blend
-      return __k ? __a : __b;
-#else
       static_assert(__is_vector_type_v<_TV>);
       using _Tp = typename _VectorTraits<_TV>::value_type;
       static_assert(sizeof(_TV) >= 16);
       static_assert(sizeof(_Tp) <= 8);
+#ifdef __clang__
+      return __movm<_VectorTraits<_TV>::_S_full_size, _Tp>(__k) ? __b : __a;
+#else
       using _IntT
 	= conditional_t<(sizeof(_Tp) > 2),
 			conditional_t<sizeof(_Tp) == 4, int, long long>,
@@ -701,8 +750,8 @@ struct _CommonImplX86 : _CommonImplBuiltin
   // Requires: _Tp to be an intrinsic type (integers blend per byte) and 16/32
   //           Bytes wide
   template <typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static _Tp _S_blend_intrin(_Tp __k, _Tp __a,
-						       _Tp __b) noexcept
+    _GLIBCXX_SIMD_INTRINSIC static _Tp
+    _S_blend_intrin(_Tp __k, _Tp __a, _Tp __b) noexcept
     {
       static_assert(is_same_v<decltype(__to_intrin(__a)), _Tp>);
       constexpr struct
@@ -765,9 +814,10 @@ struct _CommonImplX86 : _CommonImplBuiltin
       static_assert(is_same_v<_Tp, _Tp> && __have_avx512f);
       if (__k._M_is_constprop() && __at0._M_is_constprop()
 	  && __at1._M_is_constprop())
-	return __generate_from_n_evaluations<_Np,
-					     __vector_type_t<_Tp, _Np>>([&](
-	  auto __i) constexpr { return __k[__i] ? __at1[__i] : __at0[__i]; });
+	return __generate_from_n_evaluations<_Np, __vector_type_t<_Tp, _Np>>(
+		 [&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		   return __k[__i] ? __at1[__i] : __at0[__i];
+		 });
       else if constexpr (sizeof(__at0) == 64
 			 || (__have_avx512vl && sizeof(__at0) >= 16))
 	return _S_blend_avx512(__k._M_data, __at0._M_data, __at1._M_data);
@@ -841,6 +891,7 @@ template <typename _Abi, typename>
 	= (sizeof(_Tp) >= 4 && __have_avx512f) || __have_avx512bw  ? 64
 	  : (is_floating_point_v<_Tp>&& __have_avx) || __have_avx2 ? 32
 								   : 16;
+
     using _MaskImpl = typename _Abi::_MaskImpl;
 
     // _S_masked_load {{{
@@ -994,9 +1045,8 @@ template <typename _Abi, typename>
 	      }
 	    else
 	      _BitOps::_S_bit_iteration(_MaskImpl::_S_to_bits(__k),
-					[&](auto __i) {
-					  __merge._M_set(__i, static_cast<_Tp>(
-								__mem[__i]));
+					[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+					  __merge._M_set(__i, static_cast<_Tp>(__mem[__i]));
 					});
 	  }
 	/* Very uncertain, that the following improves anything. Needs
@@ -1032,8 +1082,7 @@ template <typename _Abi, typename>
     // _S_masked_store_nocvt {{{
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static void
-      _S_masked_store_nocvt(_SimdWrapper<_Tp, _Np> __v, _Tp* __mem,
-			    _SimdWrapper<bool, _Np> __k)
+      _S_masked_store_nocvt(_SimdWrapper<_Tp, _Np> __v, _Tp* __mem, _SimdWrapper<bool, _Np> __k)
       {
 	[[maybe_unused]] const auto __vi = __to_intrin(__v);
 	if constexpr (sizeof(__vi) == 64)
@@ -1300,7 +1349,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_multiplies {{{
     template <typename _V, typename _VVT = _VectorTraits<_V>>
-      _GLIBCXX_SIMD_INTRINSIC static constexpr _V _S_multiplies(_V __x, _V __y)
+      _GLIBCXX_SIMD_INTRINSIC static constexpr _V
+      _S_multiplies(_V __x, _V __y)
       {
 	using _Tp = typename _VVT::value_type;
 	if (__builtin_is_constant_evaluated() || __x._M_is_constprop()
@@ -1417,11 +1467,12 @@ template <typename _Abi, typename>
 	      const auto __yf = __convert_all<_FloatV, __n_floatv>(
 		_Abi::__make_padding_nonzero(__as_vector(__y)));
 	      return __call_with_n_evaluations<__n_floatv>(
-		[](auto... __quotients) {
+		[](auto... __quotients) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  return __vector_convert<_R>(__quotients...);
 		},
-		[&__xf,
-		 &__yf](auto __i) -> _SimdWrapper<_Float, __n_intermediate> {
+		[&__xf, &__yf](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA
+		  -> _SimdWrapper<_Float, __n_intermediate>
+		{
 #if __RECIPROCAL_MATH__
 		  // If -freciprocal-math is active, using the `/` operator is
 		  // incorrect because it may be translated to an imprecise
@@ -1477,6 +1528,8 @@ template <typename _Abi, typename>
 	  */
 	return _Base::_S_divides(__x, __y);
       }
+#else
+    using _Base::_S_divides;
 #endif // _GLIBCXX_SIMD_WORKAROUND_PR90993
 
     // }}}
@@ -1980,7 +2033,7 @@ template <typename _Abi, typename>
 	      {
 		auto __mask = __vector_bitcast<_UChar>(
 		  __vector_bitcast<_UShort>(__iy) << 5);
-		auto __maskl = [&]() {
+		auto __maskl = [&]() _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  return __to_intrin(__vector_bitcast<_UShort>(__mask) << 8);
 		};
 		auto __xh = __vector_bitcast<short>(__ix);
@@ -2067,19 +2120,20 @@ template <typename _Abi, typename>
 	  }                                                      //}}}
 	else if constexpr (sizeof(_Up) == 2 && sizeof(__x) >= 4) //{{{
 	  {
-	    [[maybe_unused]] auto __blend_0xaa = [](auto __a, auto __b) {
-	      if constexpr (sizeof(__a) == 16)
-		return _mm_blend_epi16(__to_intrin(__a), __to_intrin(__b),
-				       0xaa);
-	      else if constexpr (sizeof(__a) == 32)
-		return _mm256_blend_epi16(__to_intrin(__a), __to_intrin(__b),
-					  0xaa);
-	      else if constexpr (sizeof(__a) == 64)
-		return _mm512_mask_blend_epi16(0xaaaa'aaaaU, __to_intrin(__a),
-					       __to_intrin(__b));
-	      else
-		__assert_unreachable<decltype(__a)>();
-	    };
+	    [[maybe_unused]] auto __blend_0xaa
+	      = [](auto __a, auto __b) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		if constexpr (sizeof(__a) == 16)
+		  return _mm_blend_epi16(__to_intrin(__a), __to_intrin(__b),
+					 0xaa);
+		else if constexpr (sizeof(__a) == 32)
+		  return _mm256_blend_epi16(__to_intrin(__a), __to_intrin(__b),
+					    0xaa);
+		else if constexpr (sizeof(__a) == 64)
+		  return _mm512_mask_blend_epi16(0xaaaa'aaaaU, __to_intrin(__a),
+						 __to_intrin(__b));
+		else
+		  __assert_unreachable<decltype(__a)>();
+	      };
 	    if constexpr (__have_avx512bw_vl && sizeof(_Tp) <= 16)
 	      return __intrin_bitcast<_V>(is_signed_v<_Up>
 					    ? _mm_srav_epi16(__ix, __iy)
@@ -2136,9 +2190,10 @@ template <typename _Abi, typename>
 	      {
 		auto __k = __vector_bitcast<_UShort>(__iy) << 11;
 		auto __x128 = __vector_bitcast<_Up>(__ix);
-		auto __mask = [](__vector_type16_t<_UShort> __kk) {
-		  return __vector_bitcast<short>(__kk) < 0;
-		};
+		auto __mask
+		  = [](__vector_type16_t<_UShort> __kk) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		    return __vector_bitcast<short>(__kk) < 0;
+		  };
 		// do __x128 = 0 where __y[4] is set
 		__x128 = __mask(__k) ? decltype(__x128)() : __x128;
 		// do __x128 =>> 8 where __y[3] is set
@@ -2178,7 +2233,7 @@ template <typename _Abi, typename>
 	      }
 	    else
 	      {
-		auto __shift = [](auto __a, auto __b) {
+		auto __shift = [](auto __a, auto __b) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  if constexpr (is_signed_v<_Up>)
 		    return _mm_sra_epi32(__a, __b);
 		  else
@@ -2268,14 +2323,14 @@ template <typename _Abi, typename>
 	  } // }}}
 	else if (__builtin_is_constant_evaluated())
 	  return _Base::_S_equal_to(__x, __y);
-	else if constexpr (sizeof(__x) == 8) // {{{
+	else if constexpr (sizeof(__x) == 8)
 	  {
 	    const auto __r128 = __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__x)
 				== __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__y);
-	    _MaskMember<_Tp> __r64;
+	    _MaskMember<_Tp> __r64{};
 	    __builtin_memcpy(&__r64._M_data, &__r128, sizeof(__r64));
 	    return __r64;
-	  } // }}}
+	  }
 	else
 	  return _Base::_S_equal_to(__x, __y);
       }
@@ -2346,7 +2401,7 @@ template <typename _Abi, typename>
 	  {
 	    const auto __r128 = __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__x)
 				!= __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__y);
-	    _MaskMember<_Tp> __r64;
+	    _MaskMember<_Tp> __r64{};
 	    __builtin_memcpy(&__r64._M_data, &__r128, sizeof(__r64));
 	    return __r64;
 	  }
@@ -2454,7 +2509,7 @@ template <typename _Abi, typename>
 	  {
 	    const auto __r128 = __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__x)
 				< __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__y);
-	    _MaskMember<_Tp> __r64;
+	    _MaskMember<_Tp> __r64{};
 	    __builtin_memcpy(&__r64._M_data, &__r128, sizeof(__r64));
 	    return __r64;
 	  }
@@ -2562,7 +2617,7 @@ template <typename _Abi, typename>
 	  {
 	    const auto __r128 = __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__x)
 				<= __vector_bitcast<_Tp, 16 / sizeof(_Tp)>(__y);
-	    _MaskMember<_Tp> __r64;
+	    _MaskMember<_Tp> __r64{};
 	    __builtin_memcpy(&__r64._M_data, &__r128, sizeof(__r64));
 	    return __r64;
 	  }
@@ -2735,7 +2790,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_nearbyint {{{
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp _S_nearbyint(_Tp __x) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_nearbyint(_Tp __x) noexcept
       {
 	if constexpr (_TVT::template _S_is<float, 16>)
 	  return _mm512_roundscale_ps(__x, 0x0c);
@@ -2760,7 +2816,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_rint {{{
     template <typename _Tp, typename _TVT = _VectorTraits<_Tp>>
-      _GLIBCXX_SIMD_INTRINSIC static _Tp _S_rint(_Tp __x) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static _Tp
+      _S_rint(_Tp __x) noexcept
       {
 	if constexpr (_TVT::template _S_is<float, 16>)
 	  return _mm512_roundscale_ps(__x, 0x04);
@@ -2908,7 +2965,8 @@ template <typename _Abi, typename>
     // _S_isnonzerovalue_mask {{{
     // (isnormal | is subnormal == !isinf & !isnan & !is zero)
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static auto _S_isnonzerovalue_mask(_Tp __x)
+      _GLIBCXX_SIMD_INTRINSIC static auto
+      _S_isnonzerovalue_mask(_Tp __x)
       {
 	using _Traits = _VectorTraits<_Tp>;
 	if constexpr (__have_avx512dq_vl)
@@ -3175,8 +3233,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_isgreater {{{
     template <typename _Tp, size_t _Np>
-      static constexpr _MaskMember<_Tp> _S_isgreater(_SimdWrapper<_Tp, _Np> __x,
-						     _SimdWrapper<_Tp, _Np> __y)
+      static constexpr _MaskMember<_Tp>
+      _S_isgreater(_SimdWrapper<_Tp, _Np> __x, _SimdWrapper<_Tp, _Np> __y)
       {
 	const auto __xi = __to_intrin(__x);
 	const auto __yi = __to_intrin(__y);
@@ -3293,8 +3351,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_isless {{{
     template <typename _Tp, size_t _Np>
-      static constexpr _MaskMember<_Tp> _S_isless(_SimdWrapper<_Tp, _Np> __x,
-						  _SimdWrapper<_Tp, _Np> __y)
+      static constexpr _MaskMember<_Tp>
+      _S_isless(_SimdWrapper<_Tp, _Np> __x, _SimdWrapper<_Tp, _Np> __y)
       {
 	const auto __xi = __to_intrin(__x);
 	const auto __yi = __to_intrin(__y);
@@ -3458,6 +3516,76 @@ template <typename _Abi, typename>
       }
 
     //}}} }}}
+    template <template <typename> class _Op, typename _Tp, typename _K, size_t _Np>
+      _GLIBCXX_SIMD_INTRINSIC static _SimdWrapper<_Tp, _Np>
+      _S_masked_unary(const _SimdWrapper<_K, _Np> __k, const _SimdWrapper<_Tp, _Np> __v)
+      {
+	if (__k._M_is_constprop_none_of())
+	  return __v;
+	else if (__k._M_is_constprop_all_of())
+	  {
+	    auto __vv = _Base::_M_make_simd(__v);
+	    _Op<decltype(__vv)> __op;
+	    return __data(__op(__vv));
+	  }
+	else if constexpr (__is_bitmask_v<decltype(__k)>
+			     && (is_same_v<_Op<void>, __increment<void>>
+				   || is_same_v<_Op<void>, __decrement<void>>))
+	  {
+	    // optimize masked unary increment and decrement as masked sub +/-1
+	    constexpr int __pm_one
+	      = is_same_v<_Op<void>, __increment<void>> ? -1 : 1;
+#ifdef __clang__
+	    return __movm<_Np, _Tp>(__k._M_data) ? __v._M_data - __pm_one : __v._M_data;
+#else // __clang__
+	    if constexpr (is_integral_v<_Tp>)
+	      {
+		constexpr bool __lp64 = sizeof(long) == sizeof(long long);
+		using _Ip = std::make_signed_t<_Tp>;
+		using _Up = std::conditional_t<
+			      std::is_same_v<_Ip, long>,
+			      std::conditional_t<__lp64, long long, int>,
+			      std::conditional_t<
+				std::is_same_v<_Ip, signed char>, char, _Ip>>;
+		const auto __value = __vector_bitcast<_Up>(__v._M_data);
+#define _GLIBCXX_SIMD_MASK_SUB(_Sizeof, _Width, _Instr)                        \
+  if constexpr (sizeof(_Tp) == _Sizeof && sizeof(__v) == _Width)               \
+    return __vector_bitcast<_Tp>(__builtin_ia32_##_Instr##_mask(__value,       \
+	     __vector_broadcast<_Np>(_Up(__pm_one)), __value, __k._M_data))
+		_GLIBCXX_SIMD_MASK_SUB(1, 64, psubb512);
+		_GLIBCXX_SIMD_MASK_SUB(1, 32, psubb256);
+		_GLIBCXX_SIMD_MASK_SUB(1, 16, psubb128);
+		_GLIBCXX_SIMD_MASK_SUB(2, 64, psubw512);
+		_GLIBCXX_SIMD_MASK_SUB(2, 32, psubw256);
+		_GLIBCXX_SIMD_MASK_SUB(2, 16, psubw128);
+		_GLIBCXX_SIMD_MASK_SUB(4, 64, psubd512);
+		_GLIBCXX_SIMD_MASK_SUB(4, 32, psubd256);
+		_GLIBCXX_SIMD_MASK_SUB(4, 16, psubd128);
+		_GLIBCXX_SIMD_MASK_SUB(8, 64, psubq512);
+		_GLIBCXX_SIMD_MASK_SUB(8, 32, psubq256);
+		_GLIBCXX_SIMD_MASK_SUB(8, 16, psubq128);
+#undef _GLIBCXX_SIMD_MASK_SUB
+	      }
+	    else
+	      {
+#define _GLIBCXX_SIMD_MASK_SUB(_Sizeof, _Width, _Instr)                        \
+  if constexpr (sizeof(_Tp) == _Sizeof && sizeof(__v) == _Width)               \
+    return __builtin_ia32_##_Instr##_mask(                                     \
+	     __v._M_data, __vector_broadcast<_Np>(_Tp(__pm_one)), __v._M_data, \
+	     __k._M_data, _MM_FROUND_CUR_DIRECTION)
+		_GLIBCXX_SIMD_MASK_SUB(4, 64, subps512);
+		_GLIBCXX_SIMD_MASK_SUB(4, 32, subps256);
+		_GLIBCXX_SIMD_MASK_SUB(4, 16, subps128);
+		_GLIBCXX_SIMD_MASK_SUB(8, 64, subpd512);
+		_GLIBCXX_SIMD_MASK_SUB(8, 32, subpd256);
+		_GLIBCXX_SIMD_MASK_SUB(8, 16, subpd128);
+#undef _GLIBCXX_SIMD_MASK_SUB
+	      }
+#endif // __clang__
+	  }
+	else
+	  return _Base::template _S_masked_unary<_Op>(__k, __v);
+      }
   };
 
 // }}}
@@ -3471,8 +3599,8 @@ struct _MaskImplX86Mixin
 
   // _S_to_maskvector(bool) {{{
   template <typename _Up, size_t _ToN = 1, typename _Tp>
-    _GLIBCXX_SIMD_INTRINSIC static constexpr enable_if_t<
-      is_same_v<_Tp, bool>, _SimdWrapper<_Up, _ToN>>
+    _GLIBCXX_SIMD_INTRINSIC static constexpr
+    enable_if_t<is_same_v<_Tp, bool>, _SimdWrapper<_Up, _ToN>>
     _S_to_maskvector(_Tp __x)
     {
       static_assert(is_same_v<_Up, __int_for_sizeof_t<_Up>>);
@@ -3482,8 +3610,7 @@ struct _MaskImplX86Mixin
 
   // }}}
   // _S_to_maskvector(_SanitizedBitMask) {{{
-  template <typename _Up, size_t _UpN = 0, size_t _Np,
-	    size_t _ToN = _UpN == 0 ? _Np : _UpN>
+  template <typename _Up, size_t _UpN = 0, size_t _Np, size_t _ToN = _UpN == 0 ? _Np : _UpN>
     _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Up, _ToN>
     _S_to_maskvector(_SanitizedBitMask<_Np> __x)
     {
@@ -3495,7 +3622,7 @@ struct _MaskImplX86Mixin
 	return _S_to_maskvector<_Up, _ToN>(__k);
       else if (__x._M_is_constprop() || __builtin_is_constant_evaluated())
 	return __generate_from_n_evaluations<std::min(_ToN, _Np), _UV>(
-	  [&](auto __i) -> _Up { return -__x[__i.value]; });
+	  [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA -> _Up { return -__x[__i.value]; });
       else if constexpr (sizeof(_Up) == 1)
 	{
 	  if constexpr (sizeof(_UI) == 16)
@@ -3740,9 +3867,9 @@ struct _MaskImplX86Mixin
       else if constexpr (__bits_per_element >= _ToN)
 	{
 	  constexpr auto __bitmask
-	    = __generate_vector<_V>([](auto __i) constexpr->_UpUInt {
-		return __i < _ToN ? 1ull << __i : 0;
-	      });
+	    = __generate_vector<_V>([](auto __i)
+				    constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA -> _UpUInt
+				    { return __i < _ToN ? 1ull << __i : 0; });
 	  const auto __bits
 	    = __vector_broadcast<_ToN, _UpUInt>(__k) & __bitmask;
 	  if constexpr (__bits_per_element > _ToN)
@@ -3753,11 +3880,11 @@ struct _MaskImplX86Mixin
       else
 	{
 	  const _V __tmp
-	    = __generate_vector<_V>([&](auto __i) constexpr {
+	    = __generate_vector<_V>([&](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		return static_cast<_UpUInt>(
 		  __k >> (__bits_per_element * (__i / __bits_per_element)));
 	      })
-	      & __generate_vector<_V>([](auto __i) constexpr {
+	      & __generate_vector<_V>([](auto __i) constexpr _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  return static_cast<_UpUInt>(1ull
 					      << (__i % __bits_per_element));
 		}); // mask bit index
@@ -3793,7 +3920,7 @@ struct _MaskImplX86Mixin
 	      const auto __y = __vector_bitcast<__int_for_sizeof_t<_Tp>>(__x);
 	      return __generate_from_n_evaluations<std::min(_ToN, _Np),
 						   __vector_type_t<_Up, _ToN>>(
-		[&](auto __i) -> _Up { return __y[__i.value]; });
+		[&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA -> _Up { return __y[__i.value]; });
 	    }
 	  using _To = __vector_type_t<_Up, _ToN>;
 	  [[maybe_unused]] constexpr size_t _FromN = _Np;
@@ -4128,8 +4255,11 @@ struct _MaskImplX86Mixin
 	    {
 	      const auto __bools = -__x._M_data;
 	      const _ULLong __k = __call_with_n_evaluations<_Np>(
-		[](auto... __bits) { return (__bits | ...); },
-		[&](auto __i) { return _ULLong(__bools[+__i]) << __i; });
+		[](auto... __bits) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		  return (__bits | ...);
+		}, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
+		  return _ULLong(__bools[+__i]) << __i;
+		});
 	      if (__builtin_is_constant_evaluated()
 		  || __builtin_constant_p(__k))
 		return __k;
@@ -4283,15 +4413,28 @@ template <typename _Abi, typename>
       _S_load(const bool* __mem)
       {
 	static_assert(is_same_v<_Tp, __int_for_sizeof_t<_Tp>>);
-	if constexpr (__have_avx512bw)
+	if (__builtin_is_constant_evaluated())
 	  {
-	    const auto __to_vec_or_bits = [](auto __bits) -> decltype(auto) {
-	      if constexpr (__is_avx512_abi<_Abi>())
-		return __bits;
-	      else
-		return _S_to_maskvector<_Tp>(
-		  _BitMask<_S_size<_Tp>>(__bits)._M_sanitized());
-	    };
+	    if constexpr (__is_avx512_abi<_Abi>())
+	      {
+		_MaskMember<_Tp> __r{};
+		for (size_t __i = 0; __i < _S_size<_Tp>; ++__i)
+		  __r._M_data |= _ULLong(__mem[__i]) << __i;
+		return __r;
+	      }
+	    else
+	      return _Base::template _S_load<_Tp>(__mem);
+	  }
+	else if constexpr (__have_avx512bw)
+	  {
+	    const auto __to_vec_or_bits
+	      = [](auto __bits) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA -> decltype(auto) {
+		if constexpr (__is_avx512_abi<_Abi>())
+		  return __bits;
+		else
+		  return _S_to_maskvector<_Tp>(
+			   _BitMask<_S_size<_Tp>>(__bits)._M_sanitized());
+	      };
 
 	    if constexpr (_S_size<_Tp> <= 16 && __have_avx512vl)
 	      {
@@ -4478,7 +4621,7 @@ template <typename _Abi, typename>
 	      }
 	    else
 	      {
-		_BitOps::_S_bit_iteration(__mask, [&](auto __i) {
+		_BitOps::_S_bit_iteration(__mask, [&](auto __i) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  __merge._M_set(__i, __mem[__i]);
 		});
 		return __merge;
@@ -4550,14 +4693,16 @@ template <typename _Abi, typename>
 
     // _S_store {{{2
     template <typename _Tp, size_t _Np>
-      _GLIBCXX_SIMD_INTRINSIC static void _S_store(_SimdWrapper<_Tp, _Np> __v,
-						   bool* __mem) noexcept
+      _GLIBCXX_SIMD_INTRINSIC static constexpr void
+      _S_store(_SimdWrapper<_Tp, _Np> __v, bool* __mem) noexcept
       {
-	if constexpr (__is_avx512_abi<_Abi>())
+	if (__builtin_is_constant_evaluated())
+	  _Base::_S_store(__v, __mem);
+	else if constexpr (__is_avx512_abi<_Abi>())
 	  {
 	    if constexpr (__have_avx512bw_vl)
 	      _CommonImplX86::_S_store<_Np>(
-		__vector_bitcast<char>([](auto __data) {
+		__vector_bitcast<char>([](auto __data) _GLIBCXX_SIMD_ALWAYS_INLINE_LAMBDA {
 		  if constexpr (_Np <= 16)
 		    return _mm_maskz_set1_epi8(__data, 1);
 		  else if constexpr (_Np <= 32)
@@ -4635,7 +4780,7 @@ template <typename _Abi, typename>
 	    if constexpr (_Np <= 4 && sizeof(_Tp) == 8)
 	      {
 		auto __k = __intrin_bitcast<__m256i>(__to_intrin(__v));
-		int __bool4;
+		int __bool4{};
 		if constexpr (__have_avx2)
 		  __bool4 = _mm256_movemask_epi8(__k);
 		else
@@ -4715,12 +4860,13 @@ template <typename _Abi, typename>
     // logical and bitwise operators {{{2
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_logical_and(const _SimdWrapper<_Tp, _Np>& __x,
-		     const _SimdWrapper<_Tp, _Np>& __y)
+      _S_logical_and(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
-	    if constexpr (__have_avx512dq && _Np <= 8)
+	    if (__builtin_is_constant_evaluated())
+	      return __x._M_data & __y._M_data;
+	    else if constexpr (__have_avx512dq && _Np <= 8)
 	      return _kand_mask8(__x._M_data, __y._M_data);
 	    else if constexpr (_Np <= 16)
 	      return _kand_mask16(__x._M_data, __y._M_data);
@@ -4737,12 +4883,13 @@ template <typename _Abi, typename>
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_logical_or(const _SimdWrapper<_Tp, _Np>& __x,
-		    const _SimdWrapper<_Tp, _Np>& __y)
+      _S_logical_or(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
-	    if constexpr (__have_avx512dq && _Np <= 8)
+	    if (__builtin_is_constant_evaluated())
+	      return __x._M_data | __y._M_data;
+	    else if constexpr (__have_avx512dq && _Np <= 8)
 	      return _kor_mask8(__x._M_data, __y._M_data);
 	    else if constexpr (_Np <= 16)
 	      return _kor_mask16(__x._M_data, __y._M_data);
@@ -4763,7 +4910,9 @@ template <typename _Abi, typename>
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
-	    if constexpr (__have_avx512dq && _Np <= 8)
+	    if (__builtin_is_constant_evaluated())
+	      return __x._M_data ^ _Abi::template __implicit_mask_n<_Np>();
+	    else if constexpr (__have_avx512dq && _Np <= 8)
 	      return _kandn_mask8(__x._M_data,
 				  _Abi::template __implicit_mask_n<_Np>());
 	    else if constexpr (_Np <= 16)
@@ -4784,12 +4933,13 @@ template <typename _Abi, typename>
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_bit_and(const _SimdWrapper<_Tp, _Np>& __x,
-		 const _SimdWrapper<_Tp, _Np>& __y)
+      _S_bit_and(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
-	    if constexpr (__have_avx512dq && _Np <= 8)
+	    if (__builtin_is_constant_evaluated())
+	      return __x._M_data & __y._M_data;
+	    else if constexpr (__have_avx512dq && _Np <= 8)
 	      return _kand_mask8(__x._M_data, __y._M_data);
 	    else if constexpr (_Np <= 16)
 	      return _kand_mask16(__x._M_data, __y._M_data);
@@ -4806,12 +4956,13 @@ template <typename _Abi, typename>
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_bit_or(const _SimdWrapper<_Tp, _Np>& __x,
-		const _SimdWrapper<_Tp, _Np>& __y)
+      _S_bit_or(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
-	    if constexpr (__have_avx512dq && _Np <= 8)
+	    if (__builtin_is_constant_evaluated())
+	      return __x._M_data | __y._M_data;
+	    else if constexpr (__have_avx512dq && _Np <= 8)
 	      return _kor_mask8(__x._M_data, __y._M_data);
 	    else if constexpr (_Np <= 16)
 	      return _kor_mask16(__x._M_data, __y._M_data);
@@ -4828,12 +4979,13 @@ template <typename _Abi, typename>
 
     template <typename _Tp, size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static constexpr _SimdWrapper<_Tp, _Np>
-      _S_bit_xor(const _SimdWrapper<_Tp, _Np>& __x,
-		 const _SimdWrapper<_Tp, _Np>& __y)
+      _S_bit_xor(const _SimdWrapper<_Tp, _Np>& __x, const _SimdWrapper<_Tp, _Np>& __y)
       {
 	if constexpr (is_same_v<_Tp, bool>)
 	  {
-	    if constexpr (__have_avx512dq && _Np <= 8)
+	    if (__builtin_is_constant_evaluated())
+	      return __x._M_data ^ __y._M_data;
+	    else if constexpr (__have_avx512dq && _Np <= 8)
 	      return _kxor_mask8(__x._M_data, __y._M_data);
 	    else if constexpr (_Np <= 16)
 	      return _kxor_mask16(__x._M_data, __y._M_data);
@@ -4853,8 +5005,7 @@ template <typename _Abi, typename>
     template <size_t _Np>
       _GLIBCXX_SIMD_INTRINSIC static void
       _S_masked_assign(_SimdWrapper<bool, _Np> __k,
-		       _SimdWrapper<bool, _Np>& __lhs,
-		       _SimdWrapper<bool, _Np> __rhs)
+		       _SimdWrapper<bool, _Np>& __lhs, _SimdWrapper<bool, _Np> __rhs)
       {
 	__lhs._M_data
 	  = (~__k._M_data & __lhs._M_data) | (__k._M_data & __rhs._M_data);
@@ -4876,7 +5027,8 @@ template <typename _Abi, typename>
     //}}}
     // _S_all_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_all_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_all_of(simd_mask<_Tp, _Abi> __k)
       {
 	if constexpr (__is_sse_abi<_Abi>() || __is_avx_abi<_Abi>())
 	  {
@@ -4932,7 +5084,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_any_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_any_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_any_of(simd_mask<_Tp, _Abi> __k)
       {
 	if constexpr (__is_sse_abi<_Abi>() || __is_avx_abi<_Abi>())
 	  {
@@ -4967,7 +5120,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_none_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_none_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_none_of(simd_mask<_Tp, _Abi> __k)
       {
 	if constexpr (__is_sse_abi<_Abi>() || __is_avx_abi<_Abi>())
 	  {
@@ -5002,7 +5156,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_some_of {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static bool _S_some_of(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static bool
+      _S_some_of(simd_mask<_Tp, _Abi> __k)
       {
 	if constexpr (__is_sse_abi<_Abi>() || __is_avx_abi<_Abi>())
 	  {
@@ -5043,7 +5198,8 @@ template <typename _Abi, typename>
     // }}}
     // _S_popcount {{{
     template <typename _Tp>
-      _GLIBCXX_SIMD_INTRINSIC static int _S_popcount(simd_mask<_Tp, _Abi> __k)
+      _GLIBCXX_SIMD_INTRINSIC static int
+      _S_popcount(simd_mask<_Tp, _Abi> __k)
       {
 	constexpr size_t _Np = simd_size_v<_Tp, _Abi>;
 	const auto __kk = _Abi::_S_masked(__k._M_data)._M_data;
--- a/src/libstdc++-v3/python/libstdcxx/v6/printers.py
+++ b/src/libstdc++-v3/python/libstdcxx/v6/printers.py
@@ -1216,9 +1216,34 @@ class StdExpAnyPrinter(SingleObjContainerPrinter):
             mgrname = m.group(1)
             # FIXME need to expand 'std::string' so that gdb.lookup_type works
             if 'std::string' in mgrname:
-                mgrname = re.sub("std::string(?!\w)", str(gdb.lookup_type('std::string').strip_typedefs()), m.group(1))
-
-            mgrtype = gdb.lookup_type(mgrname)
+                # This lookup for std::string might return the __cxx11 version,
+                # but that's not necessarily the one used by the std::any
+                # manager function we're trying to find.
+                strings = {str(gdb.lookup_type('std::string').strip_typedefs())}
+                # So also consider all the other possible std::string types!
+                s = 'basic_string<char, std::char_traits<char>, std::allocator<char> >'
+                quals = ['std::', 'std::__cxx11::', 'std::' + _versioned_namespace]
+                strings |= {q+s for q in quals} # set of unique strings
+                mgrtypes = []
+                for s in strings:
+                    try:
+                        x = re.sub("std::string(?!\w)", s, m.group(1))
+                        # The following lookup might raise gdb.error if the
+                        # manager function was never instantiated for 's' in the
+                        # program, because there will be no such type.
+                        mgrtypes.append(gdb.lookup_type(x))
+                    except gdb.error:
+                        pass
+                if len(mgrtypes) != 1:
+                    # FIXME: this is unlikely in practice, but possible for
+                    # programs that use both old and new string types with
+                    # std::any in a single program. Can we do better?
+                    # Maybe find the address of each type's _S_manage and
+                    # compare to the address stored in _M_manager?
+                    raise ValueError('Cannot uniquely determine std::string type used in std::any')
+                mgrtype = mgrtypes[0]
+            else:
+                mgrtype = gdb.lookup_type(mgrname)
             self.contained_type = mgrtype.template_argument(0)
             valptr = None
             if '::_Manager_internal' in mgrname:
--- a/src/libstdc++-v3/src/c++17/memory_resource.cc
+++ b/src/libstdc++-v3/src/c++17/memory_resource.cc
@@ -506,7 +506,7 @@ namespace pmr
     }
 
     // Allocated size of chunk:
-    uint32_t _M_bytes = 0;
+    bitset::size_type _M_bytes = 0;
     // Start of allocated chunk:
     std::byte* _M_p = nullptr;
 
@@ -580,7 +580,7 @@ namespace pmr
   // For 16-bit pointers it's five pointers (10 bytes).
   // TODO pad 64-bit to 4*sizeof(void*) to avoid splitting across cache lines?
   static_assert(sizeof(chunk)
-      == sizeof(bitset::size_type) + sizeof(uint32_t) + 2 * sizeof(void*));
+      == 2 * sizeof(bitset::size_type) + 2 * sizeof(void*));
 
   // An oversized allocation that doesn't fit in a pool.
   struct big_block
@@ -735,7 +735,7 @@ namespace pmr
 	  _M_blocks_per_chunk = std::min({
 	      max_blocks,
 	      __opts.max_blocks_per_chunk,
-	      (size_t)_M_blocks_per_chunk * 2
+	      size_t(_M_blocks_per_chunk * 2)
 	  });
 	}
     }
@@ -1058,7 +1058,8 @@ namespace pmr
 	// Decide on initial number of blocks per chunk.
 	// At least 16 blocks per chunk seems reasonable,
 	// more for smaller blocks:
-	size_t blocks_per_chunk = std::max(size_t(16), 1024 / block_size);
+	size_t blocks_per_chunk = 1024 / block_size;
+	blocks_per_chunk = std::max(size_t(16), blocks_per_chunk);
 	// But don't exceed the requested max_blocks_per_chunk:
 	blocks_per_chunk
 	  = std::min(blocks_per_chunk, _M_opts.max_blocks_per_chunk);
--- a/src/libstdc++-v3/testsuite/20_util/from_chars/4.cc
+++ b/src/libstdc++-v3/testsuite/20_util/from_chars/4.cc
@@ -18,6 +18,7 @@
 // <charconv> is supported in C++14 as a GNU extension
 // { dg-do run { target c++14 } }
 // { dg-add-options ieee }
+// { dg-additional-options "-DSKIP_LONG_DOUBLE" { target aarch64-*-vxworks* x86_64-*-vxworks* } }
 
 #include <charconv>
 #include <string>
@@ -354,7 +355,7 @@ test06()
 {
   test_max_mantissa<float, unsigned long>();
   test_max_mantissa<double, unsigned long long>();
-#ifdef __GLIBCXX_TYPE_INT_N_0
+#if defined __GLIBCXX_TYPE_INT_N_0 && !defined SKIP_LONG_DOUBLE
   test_max_mantissa<long double, unsigned __GLIBCXX_TYPE_INT_N_0>();
 #endif
 }
--- a/src/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
+++ b/src/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
@@ -34,6 +34,10 @@
 // more portable and robust to differences in system printf behavior.
 // { dg-xfail-run-if "Non-conforming printf (see PR98384)" { *-*-solaris* *-*-darwin* } }
 
+// On systems that use double-precision from_chars for long double,
+// this is expected to fail.
+// { dg-xfail-run-if "from_chars limited to double-precision" { aarch64-*-vxworks* i*86-*-vxworks* x86_64-*-vxworks* } }
+
 // { dg-require-effective-target ieee_floats }
 // { dg-require-effective-target size32plus }
 
new file mode 100644
--- /dev/null
+++ b/src/libstdc++-v3/testsuite/experimental/simd/pr109261_constexpr_simd.cc
@@ -0,0 +1,92 @@
+// { dg-options "-std=gnu++17" }
+// { dg-do compile { target c++17 } }
+// { dg-require-cmath "" }
+
+#include <experimental/simd>
+
+namespace stdx = std::experimental;
+
+template <typename T, typename V>
+  void
+  test01()
+  {
+    constexpr T data[V::size()] = {};
+    constexpr auto a = V(data, stdx::element_aligned);
+
+    constexpr auto b = []() constexpr {
+      V x = T(1);
+      where(x > T(), x) = T();
+      where(x < T(), x) += T();
+      where(x >= T(), x) -= T();
+      where(x <= T(), x) *= T();
+      where(x == T(), x) /= T(1);
+      where(x != T(), x) += T(1);
+      return x;
+    }();
+
+    constexpr T c = V()[0];
+
+    constexpr auto d = !V() && !!V() || !V() & !V() | !V() ^ !V();
+
+    constexpr auto e = []() constexpr {
+      T data[V::size()] = {};
+      V(T(1)).copy_to(data, stdx::element_aligned);
+      V x = T();
+      x[0] = T(1);
+      x.copy_from(data, stdx::element_aligned);
+      bool mask[V::size()] = {};
+      auto k = hmin(x + x - x * x) == x / x;
+      k.copy_to(mask, stdx::element_aligned);
+      mask[0] = false;
+      using M = typename V::mask_type;
+      return M(mask, stdx::element_aligned);
+    }();
+
+    static_assert(not e[0]);
+    static_assert(popcount(e) == V::size() - 1);
+
+    static_assert(all_of(V(T(1)) == []() constexpr {
+      float data[V::size()] = {};
+      V(T(1)).copy_to(data, stdx::element_aligned);
+      V x = T();
+      x.copy_from(data, stdx::element_aligned);
+      return x;
+    }()));
+
+    static_assert(hmin(V()) == T());
+    static_assert(hmax(V()) == T());
+    static_assert(reduce(V(1)) == T(V::size()));
+  }
+
+template <typename T>
+  void
+  iterate_abis()
+  {
+    test01<T, stdx::simd<T, stdx::simd_abi::scalar>>();
+    test01<T, stdx::simd<T>>();
+    test01<T, stdx::native_simd<T>>();
+    test01<T, stdx::fixed_size_simd<T, 3>>();
+    test01<T, stdx::fixed_size_simd<T, stdx::simd_abi::max_fixed_size<T> - 4>>();
+  }
+
+int main()
+{
+  iterate_abis<char>();
+  iterate_abis<wchar_t>();
+  iterate_abis<char16_t>();
+  iterate_abis<char32_t>();
+
+  iterate_abis<signed char>();
+  iterate_abis<unsigned char>();
+  iterate_abis<short>();
+  iterate_abis<unsigned short>();
+  iterate_abis<int>();
+  iterate_abis<unsigned int>();
+  iterate_abis<long>();
+  iterate_abis<unsigned long>();
+  iterate_abis<long long>();
+  iterate_abis<unsigned long long>();
+  iterate_abis<float>();
+  iterate_abis<double>();
+  iterate_abis<long double>();
+}
new file mode 100644
--- /dev/null
+++ b/src/libstdc++-v3/testsuite/experimental/simd/pr109822_cast_functions.cc
@@ -0,0 +1,63 @@
+// { dg-options "-std=gnu++17" }
+// { dg-do compile { target c++17 } }
+
+#include <experimental/simd>
+
+namespace stdx = std::experimental;
+
+template <typename T, typename V>
+  void
+  test01()
+  {
+    using M = typename V::mask_type;
+    [[maybe_unused]] auto x = to_fixed_size(V());
+    [[maybe_unused]] auto k = to_fixed_size(M());
+    if constexpr (stdx::simd<T>::size() == V::size())
+      {
+	[[maybe_unused]] auto xx = to_compatible(x);
+	[[maybe_unused]] auto kk = to_compatible(k);
+	x = to_fixed_size(xx);
+	k = to_fixed_size(kk);
+      }
+    if constexpr (stdx::native_simd<T>::size() == V::size())
+      {
+	[[maybe_unused]] auto xx = to_native(x);
+	[[maybe_unused]] auto kk = to_native(k);
+	x = to_fixed_size(xx);
+	k = to_fixed_size(kk);
+      }
+  }
+
+template <typename T>
+  void
+  iterate_abis()
+  {
+    test01<T, stdx::simd<T, stdx::simd_abi::scalar>>();
+    test01<T, stdx::simd<T>>();
+    test01<T, stdx::native_simd<T>>();
+    test01<T, stdx::fixed_size_simd<T, 3>>();
+    test01<T, stdx::fixed_size_simd<T, stdx::simd_abi::max_fixed_size<T> - 4>>();
+  }
+
+int
+main()
+{
+  iterate_abis<char>();
+  iterate_abis<wchar_t>();
+  iterate_abis<char16_t>();
+  iterate_abis<char32_t>();
+
+  iterate_abis<signed char>();
+  iterate_abis<unsigned char>();
+  iterate_abis<short>();
+  iterate_abis<unsigned short>();
+  iterate_abis<int>();
+  iterate_abis<unsigned int>();
+  iterate_abis<long>();
+  iterate_abis<unsigned long>();
+  iterate_abis<long long>();
+  iterate_abis<unsigned long long>();
+  iterate_abis<float>();
+  iterate_abis<double>();
+  iterate_abis<long double>();
+}
--- a/src/libstdc++-v3/testsuite/experimental/simd/tests/fpclassify.cc
+++ b/src/libstdc++-v3/testsuite/experimental/simd/tests/fpclassify.cc
@@ -40,9 +40,11 @@ template <typename V>
   {
     using T = typename V::value_type;
     using intv = std::experimental::fixed_size_simd<int, V::size()>;
+#if __GCC_IEC_559 >= 2
     constexpr T inf = std::__infinity_v<T>;
     constexpr T denorm_min = std::__infinity_v<T>;
     constexpr T nan = std::__quiet_NaN_v<T>;
+#endif
     constexpr T max = std::__finite_max_v<T>;
     constexpr T norm_min = std::__norm_min_v<T>;
     test_values<V>(
--- a/src/libstdc++-v3/testsuite/experimental/simd/tests/frexp.cc
+++ b/src/libstdc++-v3/testsuite/experimental/simd/tests/frexp.cc
@@ -27,11 +27,17 @@ template <typename V>
   {
     using int_v = std::experimental::fixed_size_simd<int, V::size()>;
     using T = typename V::value_type;
+#if __GCC_IEC_559 >= 2 || defined __STDC_IEC_559__
     constexpr auto denorm_min = std::__denorm_min_v<T>;
+#endif
+#if __GCC_IEC_559 >= 2
     constexpr auto norm_min = std::__norm_min_v<T>;
+#endif
     constexpr auto max = std::__finite_max_v<T>;
+#if defined __STDC_IEC_559__
     constexpr auto nan = std::__quiet_NaN_v<T>;
     constexpr auto inf = std::__infinity_v<T>;
+#endif
     test_values<V>(
       {0, 0.25, 0.5, 1, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
        20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 32, 31, -0., -0.25, -0.5, -1,
--- a/src/libstdc++-v3/testsuite/experimental/simd/tests/integer_operators.cc
+++ b/src/libstdc++-v3/testsuite/experimental/simd/tests/integer_operators.cc
@@ -180,11 +180,10 @@ template <typename V>
 	  for (int j = 0; j < 100; ++j)
 	    {
 	      const V seq([&](auto i) -> T { return (j + i) % n_promo_bits; });
-	      COMPARE(V(1) >> seq, V([&](auto i) { return T(T(1) >> seq[i]); }))
-		<< "seq = " << seq;
-	      COMPARE(make_value_unknown(V(1)) >> make_value_unknown(seq),
-		V([&](auto i) { return T(T(1) >> seq[i]); }))
-		<< "seq = " << seq;
+	      const V expect([&](auto i) { return seq[i] == 0 ? T(1) : T(0); });
+	      COMPARE(V(1) >> seq, expect) << "\nseq = " << seq;
+	      COMPARE(make_value_unknown(V(1)) >> make_value_unknown(seq), expect)
+		<< "\nseq = " << seq;
 	    }
 	  for_constexpr<int, 0, n_promo_bits - 1>([](auto shift_ic) {
 	    constexpr int shift = shift_ic;
--- a/src/libstdc++-v3/testsuite/experimental/simd/tests/ldexp_scalbn_scalbln_modf.cc
+++ b/src/libstdc++-v3/testsuite/experimental/simd/tests/ldexp_scalbn_scalbln_modf.cc
@@ -139,7 +139,6 @@ template <typename V>
 	if (modf_is_broken)
 	  return;
 	V integral = {};
-	const V totest = modf(input, &integral);
 	auto&& expected = [&](const auto& v) -> std::pair<const V, const V> {
 	  std::pair<V, V> tmp = {};
 	  using std::modf;
@@ -151,8 +150,9 @@ template <typename V>
 	    }
 	  return tmp;
 	};
-	const auto expect1 = expected(input);
 #ifdef __STDC_IEC_559__
+	const V totest = modf(input, &integral);
+	const auto expect1 = expected(input);
 	COMPARE(isnan(totest), isnan(expect1.first))
 	  << "modf(" << input << ", iptr) = " << totest << " != " << expect1;
 	COMPARE(isnan(integral), isnan(expect1.second))
--- a/src/libstdc++-v3/testsuite/experimental/simd/tests/logarithm.cc
+++ b/src/libstdc++-v3/testsuite/experimental/simd/tests/logarithm.cc
@@ -30,11 +30,13 @@ template <typename V>
     vir::test::setFuzzyness<double>(1);
 
     using T = typename V::value_type;
+#ifdef __STDC_IEC_559__
     constexpr T nan = std::__quiet_NaN_v<T>;
     constexpr T inf = std::__infinity_v<T>;
     constexpr T denorm_min = std::__denorm_min_v<T>;
-    constexpr T norm_min = std::__norm_min_v<T>;
     constexpr T min = std::__finite_min_v<T>;
+#endif
+    constexpr T norm_min = std::__norm_min_v<T>;
     constexpr T max = std::__finite_max_v<T>;
     test_values<V>({1,
 		    2,
--- a/src/libstdc++-v3/testsuite/experimental/simd/tests/operator_cvt.cc
+++ b/src/libstdc++-v3/testsuite/experimental/simd/tests/operator_cvt.cc
@@ -220,8 +220,6 @@ template <typename V>
 	binary_op_return_type<vldouble, short>();
 	binary_op_return_type<vldouble, ushort>();
 	binary_op_return_type<vldouble, uint>();
-	binary_op_return_type<vldouble, long>();
-	binary_op_return_type<vldouble, ulong>();
 	binary_op_return_type<vldouble, float>();
 	binary_op_return_type<vldouble, double>();
 
@@ -231,8 +229,6 @@ template <typename V>
 	binary_op_return_type<vf64<long double>, ushort>();
 	binary_op_return_type<vf64<long double>, int>();
 	binary_op_return_type<vf64<long double>, uint>();
-	binary_op_return_type<vf64<long double>, long>();
-	binary_op_return_type<vf64<long double>, ulong>();
 	binary_op_return_type<vf64<long double>, float>();
 	binary_op_return_type<vf64<long double>, double>();
 	binary_op_return_type<vf64<long double>, vf64<long double>>();
@@ -245,8 +241,6 @@ template <typename V>
 	binary_op_return_type<simd<long double, A>, ushort>();
 	binary_op_return_type<simd<long double, A>, int>();
 	binary_op_return_type<simd<long double, A>, uint>();
-	binary_op_return_type<simd<long double, A>, long>();
-	binary_op_return_type<simd<long double, A>, ulong>();
 	binary_op_return_type<simd<long double, A>, float>();
 	binary_op_return_type<simd<long double, A>, double>();
 
@@ -258,6 +252,24 @@ template <typename V>
 	    VERIFY((is_substitution_failure<vf64<ldouble>, ullong>));
 	    VERIFY((is_substitution_failure<simd<ldouble, A>, llong>));
 	    VERIFY((is_substitution_failure<simd<ldouble, A>, ullong>));
+	    if constexpr (sizeof(long) == sizeof(llong))
+	      {
+		VERIFY((is_substitution_failure<vldouble, long>));
+		VERIFY((is_substitution_failure<vldouble, ulong>));
+		VERIFY((is_substitution_failure<vf64<ldouble>, long>));
+		VERIFY((is_substitution_failure<vf64<ldouble>, ulong>));
+		VERIFY((is_substitution_failure<simd<ldouble, A>, long>));
+		VERIFY((is_substitution_failure<simd<ldouble, A>, ulong>));
+	      }
+	    else
+	      {
+		binary_op_return_type<vldouble, long>();
+		binary_op_return_type<vldouble, ulong>();
+		binary_op_return_type<vf64<long double>, long>();
+		binary_op_return_type<vf64<long double>, ulong>();
+		binary_op_return_type<simd<long double, A>, long>();
+		binary_op_return_type<simd<long double, A>, ulong>();
+	      }
 	  }
 	else
 	  {
@@ -267,6 +279,12 @@ template <typename V>
 	    binary_op_return_type<vf64<long double>, ullong>();
 	    binary_op_return_type<simd<long double, A>, llong>();
 	    binary_op_return_type<simd<long double, A>, ullong>();
+	    binary_op_return_type<vldouble, long>();
+	    binary_op_return_type<vldouble, ulong>();
+	    binary_op_return_type<vf64<long double>, long>();
+	    binary_op_return_type<vf64<long double>, ulong>();
+	    binary_op_return_type<simd<long double, A>, long>();
+	    binary_op_return_type<simd<long double, A>, ulong>();
 	  }
 
 	VERIFY((is_substitution_failure<vf64<long double>, vldouble>));
--- a/src/libstdc++-v3/testsuite/experimental/simd/tests/reductions.cc
+++ b/src/libstdc++-v3/testsuite/experimental/simd/tests/reductions.cc
@@ -114,6 +114,7 @@ template <typename V>
       T acc = x[0];
       for (size_t i = 1; i < V::size(); ++i)
 	acc += x[i];
-      ULP_COMPARE(reduce(x), acc, V::size() / 2).on_failure("x = ", x);
+      const T max_distance = std::is_integral_v<T> ? 0 : V::size() / 2;
+      ULP_COMPARE(reduce(x), acc, max_distance).on_failure("x = ", x);
     });
   }
--- a/src/libstdc++-v3/testsuite/experimental/simd/tests/trunc_ceil_floor.cc
+++ b/src/libstdc++-v3/testsuite/experimental/simd/tests/trunc_ceil_floor.cc
@@ -25,8 +25,10 @@ template <typename V>
   test()
   {
     using T = typename V::value_type;
+#ifdef __STDC_IEC_559__
     constexpr T inf = std::__infinity_v<T>;
     constexpr T denorm_min = std::__denorm_min_v<T>;
+#endif
     constexpr T norm_min = std::__norm_min_v<T>;
     constexpr T max = std::__finite_max_v<T>;
     constexpr T min = std::__finite_min_v<T>;
