# ZBX_CPLD

The top is defined in HDL source file zbx_top_cpld.v.

## P1 Content

### Register map for 'ZBX_CPLD' core team members

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## ports

This section lists all common communication interfaces of the ZBX CPLD. Each input port will point to a regmap. The SPI port can reach out to each register. The GPIO port can access a subset of all register, where the use case is mainly RF configuration to enable fast changes.

### Port GPIO (input)

Target Regmap = GPIO_REGMAP

Controlport requests from the FPGA GPIO lines.

This port is defined in HDL source file zbx_top_cpld.v.

### Port SPI (input)

Target Regmap = SPI_REGMAP

Controlport requests from this SPI interface are driven by the PL part of the RFSoC via the MB CPLD.

This port is defined in HDL source file zbx_top_cpld.v.

# ATR_REGMAP

## ATR_REGISTERS

This regmap contains settings for the active configuration of RF 0 and 1. There are two sets of configurations. One set comprises RF switches and LEDs, the other set comprises the attenuators (DSA).

### ATR_OPTIONS Enumeration

Contains the options available for RF 0 and RF 1. The chosen setting affects how the active configuration of up to 8 bits is derived.

Value | Name
0 | SW_DEFINED Uses the respective value of SW_CONFIG_REG as configuration.
1 | CLASSIC_ATR This option assumes the FPGA state to be assigned with: Bit 0 = RF 0 RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3 = RF 1 TX running. The configuration for each RF chain is built up of the 2 bits for the RF chain (4 possible states: IDLE, RX only, TX only, TX/RX).
2 | FPGA_STATE The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states.

This enumerated type is defined in HDL source file atr_controller.v.

### Offset 0x0000: CURRENT_CONFIG_REG Register (R)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS
0x000000
CURRENT_CONFIG_REG
offset=0x0000
Total Offset =
0x001000
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Total Offset =
0x001000

Initial Value not specified

This register is defined in HDL source file atr_controller.v.

Contains the current active configuration.

Bits | Name
31..24 | CURRENT_RF1_DSA_CONFIG Current active configuration for DSAs of RF 1.
23..16 | CURRENT_RF0_DSA_CONFIG Current active configuration for DSAs of RF 0.
15..8 | CURRENT_RF1_CONFIG Current active configuration for switches and LEDs of RF 1.
7..0 | CURRENT_RF0_CONFIG Current active configuration for switches and LEDs of RF 0.

### Offset 0x0004: OPTION_REG Register (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS
0x000000
OPTION_REG
offset=0x0004
Total Offset =
0x001004
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Total Offset =
0x001004

Initial Value = 0x00000000

This register is defined in HDL source file atr_controller.v.

Set the option to be used for the RF chains.

Bits | Name
31..26 | Reserved
25..24 | RF1_DSA_OPTION (initialvalue=SW_DEFINED) Option used for DSAs of RF 1. The values for this bitfield are in the ATR_OPTIONS table. (show here) Contains the options available for RF 0 and RF 1. The chosen setting affects how the active configuration of up to 8 bits is derived.
Value | Name
0 | SW_DEFINED Uses the respective value of SW_CONFIG_REG as configuration.
1 | CLASSIC_ATR This option assumes the FPGA state to be assigned with: Bit 0 = RF 0 RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3 = RF 1 TX running. The configuration for each RF chain is built up of the 2 bits for the RF chain (4 possible states: IDLE, RX only, TX only, TX/RX).
2 | FPGA_STATE The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states.
This enumerated type is defined in HDL source file atr_controller.v.
23..18 | Reserved
17..16 | RF0_DSA_OPTION (initialvalue=SW_DEFINED) Option used for DSAs of RF 0. The values for this bitfield are in the ATR_OPTIONS table. (show here) Contains the options available for RF 0 and RF 1. The chosen setting affects how the active configuration of up to 8 bits is derived.
Value | Name
0 | SW_DEFINED Uses the respective value of SW_CONFIG_REG as configuration.
1 | CLASSIC_ATR This option assumes the FPGA state to be assigned with: Bit 0 = RF 0 RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3 = RF 1 TX running. The configuration for each RF chain is built up of the 2 bits for the RF chain (4 possible states: IDLE, RX only, TX only, TX/RX).
2 | FPGA_STATE The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states.
This enumerated type is defined in HDL source file atr_controller.v.
15..10 | Reserved
9..8 | RF1_OPTION (initialvalue=SW_DEFINED) Option used for switches and LEDs of RF 1. The values for this bitfield are in the ATR_OPTIONS table. (show here) Contains the options available for RF 0 and RF 1. The chosen setting affects how the active configuration of up to 8 bits is derived.
Value | Name
0 | SW_DEFINED Uses the respective value of SW_CONFIG_REG as configuration.
1 | CLASSIC_ATR This option assumes the FPGA state to be assigned with: Bit 0 = RF 0 RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3 = RF 1 TX running. The configuration for each RF chain is built up of the 2 bits for the RF chain (4 possible states: IDLE, RX only, TX only, TX/RX).
2 | FPGA_STATE The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states.
This enumerated type is defined in HDL source file atr_controller.v.
7..2 | Reserved
1..0 | RF0_OPTION (initialvalue=SW_DEFINED) Option used for switches and LEDs of RF 0. The values for this bitfield are in the ATR_OPTIONS table. (show here) Contains the options available for RF 0 and RF 1. The chosen setting affects how the active configuration of up to 8 bits is derived.
Value | Name
0 | SW_DEFINED Uses the respective value of SW_CONFIG_REG as configuration.
1 | CLASSIC_ATR This option assumes the FPGA state to be assigned with: Bit 0 = RF 0 RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3 = RF 1 TX running. The configuration for each RF chain is built up of the 2 bits for the RF chain (4 possible states: IDLE, RX only, TX only, TX/RX).
2 | FPGA_STATE The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states.
This enumerated type is defined in HDL source file atr_controller.v.

### Offset 0x0008: SW_CONFIG_REG Register (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS
0x000000
SW_CONFIG_REG
offset=0x0008
Total Offset =
0x001008
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Total Offset =
0x001008

Initial Value = 0x00000000

This register is defined in HDL source file atr_controller.v.

Contains the configuration to be applied in case SW_DEFINED option is chosen.

Bits | Name
31..24 | SW_RF1_DSA_CONFIG (initialvalue=0) SW defined configuration for DSAs of RF 1.
23..16 | SW_RF0_DSA_CONFIG (initialvalue=0) SW defined configuration for DSAs of RF 0.
15..8 | SW_RF1_CONFIG (initialvalue=0) SW defined configuration for switches and LEDs of RF 1.
7..0 | SW_RF0_CONFIG (initialvalue=0) SW defined configuration for switches and LEDs of RF 0.

# BASIC_REGS_REGMAP

## BASIC_REGS_REGISTERS

This regmap contains the revision registers, signature register, a scratch register, and a slave control reg.

### BASIC_REGISTERS_VALUES Enumeration

This enum is used to create the constants held in the basic registers in both verilog and vhdl.

Value | Name
Dec | Hex
16386 | 0x00004002 | BOARD_ID_VALUE
537986577 | 0x20110611 | OLDEST_CPLD_REVISION
554767892 | 0x21111614 | CPLD_REVISION

This enumerated type is defined in HDL source file basic_regs.v.

### Offset 0x0000: SLAVE_SIGNATURE Register (R)

(show extended info)

Port GPIO
GPIO_REGMAP|BASE_WINDOW_GPIO
0x000000
SLAVE_SIGNATURE
offset=0x0000
Total Offset =
0x000000
Port SPI
SPI_REGMAP|BASE_WINDOW_SPI
0x000000
Total Offset =
0x000000

Initial Value not specified

This register is defined in HDL source file basic_regs.v.

This register contains the unique signature of the DB. This signature is the same value as the one stored on the board ID EEPROM

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..0 | BOARD_ID Board ID corresponds to the las 16 digits of the daughterboard part number.

### Offset 0x0004: SLAVE_REVISION Register (R)

(show extended info)

Port GPIO
GPIO_REGMAP|BASE_WINDOW_GPIO
0x000000
SLAVE_REVISION
offset=0x0004
Total Offset =
0x000004
Port SPI
SPI_REGMAP|BASE_WINDOW_SPI
0x000000
Total Offset =
0x000004

Initial Value not specified

This register is defined in HDL source file basic_regs.v.

This register contains the revision number of the current build

Bits | Name
31..0 | REVISION_REG Returns the revision in YYMMDDHH format

### Offset 0x0008: SLAVE_OLDEST_REVISION Register (R)

(show extended info)

Port GPIO
GPIO_REGMAP|BASE_WINDOW_GPIO
0x000000
SLAVE_OLDEST_REVISION
offset=0x0008
Total Offset =
0x000008
Port SPI
SPI_REGMAP|BASE_WINDOW_SPI
0x000000
Total Offset =
0x000008

Initial Value not specified

This register is defined in HDL source file basic_regs.v.

This register contains the revision number of the oldest compatible revision

Bits | Name
31..0 | OLDEST_REVISION_REG Returns the oldest compatible revision in YYMMDDHH format

### Offset 0x000C: SLAVE_SCRATCH Register (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|BASE_WINDOW_GPIO
0x000000
SLAVE_SCRATCH
offset=0x000C
Total Offset =
0x00000C
Port SPI
SPI_REGMAP|BASE_WINDOW_SPI
0x000000
Total Offset =
0x00000C

Initial Value = 0x00000000

This register is defined in HDL source file basic_regs.v.

Read/write scratch register

Bits | Name
31..0 | SCRATCH_REG (initialvalue=0) Returns the value written here previously.

### Offset 0x0010: GIT_HASH_REGISTER Register (R)

(show extended info)

Port GPIO
GPIO_REGMAP|BASE_WINDOW_GPIO
0x000000
GIT_HASH_REGISTER
offset=0x0010
Total Offset =
0x000010
Port SPI
SPI_REGMAP|BASE_WINDOW_SPI
0x000000
Total Offset =
0x000010

Initial Value not specified

This register is defined in HDL source file basic_regs.v.

Git hash of commit used to build this image.
Value equals 0xDEADBEEF if the git hash was not used during synthesis.

Bits | Name
31..28 | GIT_CLEAN 0x0 in case the git status was clean 0xF in case there were uncommitted changes
27..0 | GIT_HASH 7 hex digit hash code of the commit

# DB_CONTROL_REGMAP

## DB_CONTROL_WINDOWS

Windows need to be without gaps to guarantee response to combiners.

### Offset 0x0000: ATR_CONTROLLER_REGS Window (R|W)

Target regmap = ATR_REGMAP

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
ATR_CONTROLLER_REGS
offset=0x0000
size=0x20 (32 bytes)
Total Offset =
0x001000
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Total Offset =
0x001000

This window is defined in HDL source file zbx_top_cpld.v.

### Offset 0x0020: LO_CONTROL_REGS Window (R|W)

Target regmap = LO_CONTROL_REGMAP

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
LO_CONTROL_REGS
offset=0x0020
size=0x3E0 (992 bytes)
Total Offset =
0x001020
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Total Offset =
0x001020

This window is defined in HDL source file zbx_top_cpld.v.

Extended original size of 0x20 to fill gap to next window.

### Offset 0x0400: LED_SETUP_REGS Window (R|W)

Target regmap = LED_SETUP_REGMAP

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
LED_SETUP_REGS
offset=0x0400
size=0xC00 (3 Kbytes)
Total Offset =
0x001400
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Total Offset =
0x001400

This window is defined in HDL source file zbx_top_cpld.v.

Extended original size of 0x400 to fill gap to next window.

### Offset 0x1000: SWITCH_SETUP_REGS Window (R|W)

Target regmap = SWITCH_SETUP_REGMAP

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
SWITCH_SETUP_REGS
offset=0x1000
size=0x1000 (4 Kbytes)
Total Offset =
0x002000
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Total Offset =
0x002000

This window is defined in HDL source file zbx_top_cpld.v.

### Offset 0x2000: DSA_SETUP_REGS Window (R|W)

Target regmap = DSA_SETUP_REGMAP

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DSA_SETUP_REGS
offset=0x2000
size=0x3000 (12 Kbytes)
Total Offset =
0x003000
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Total Offset =
0x003000

This window is defined in HDL source file zbx_top_cpld.v.

## REGISTER_ENDPOINTS

### REGISTER_BLOCKS Enumeration

Value | Name
0 | ATR_REGISTERS
1 | LED_REGISTERS
2 | LO_SPI
3 | SW_CONTROL
4 | DSA_CONTROL

This enumerated type is defined in HDL source file zbx_cpld_core.v.

# DSA_SETUP_REGMAP

## DSA_SETUP_REGISTERS

The following registers control the digital step attenuators (DSA).

There are two ways to set the DSA values, which are applied to the DB ICs.

1. The ...DSA_ATR registers can be used to access the raw values of each ATR configuration.

2. Gain tables can be used as intermediate step to abstract from the raw DB values. This gain table can be modified using the ...DSA_TABLE registers according to the content of the registers from the first option. Initially each gain table is empty (all zeros). Each gain table entry can be accessed at any time. Once the table is filled with values the ...DSA_TABLE_SELECT registers can be used to get one gain table entry with index TABLE_INDEX and write it to the appropriate ATR configuration given by the address (see show extended info link below the register array headlines)

### Offset 0x0000: TX0_DSA_ATR(255:0) Register Array (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|DSA_SETUP_REGS
0x002000
TX0_DSA_ATR
offset=0x0000 + i*4
Cannot determine accessibility through this path
Total Offset =
0x003000 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x003000 + i*4

Initial Values

default | => | 0x00001F1F

This register is defined in HDL source file dsa_control.v.
It uses RegType TX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

Controls the Tx0 DSAs by accessing the raw attenuation levels.

This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..13 | Reserved
12..8 | TX_DSA2 (initialvalue=31) Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
7..5 | Reserved
4..0 | TX_DSA1 (initialvalue=31) Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

### Offset 0x0400: TX1_DSA_ATR(255:0) Register Array (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|DSA_SETUP_REGS
0x002000
TX1_DSA_ATR
offset=0x0400 + i*4
Cannot determine accessibility through this path
Total Offset =
0x003400 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x003400 + i*4

Initial Values

default | => | 0x00001F1F

This register is defined in HDL source file dsa_control.v.
It uses RegType TX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

Controls the Tx1 DSAs by accessing the raw attenuation levels.

This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..13 | Reserved
12..8 | TX_DSA2 (initialvalue=31) Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
7..5 | Reserved
4..0 | TX_DSA1 (initialvalue=31) Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

### Offset 0x0800: RX0_DSA_ATR(255:0) Register Array (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|DSA_SETUP_REGS
0x002000
RX0_DSA_ATR
offset=0x0800 + i*4
Cannot determine accessibility through this path
Total Offset =
0x003800 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x003800 + i*4

Initial Values

default | => | 0x0000FFFF

This register is defined in HDL source file dsa_control.v.
It uses RegType RX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

Controls the Rx0 DSAs by accessing the raw attenuation levels.

This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..12 | RX_DSA3_B (initialvalue=15) Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/}
11..8 | RX_DSA3_A (initialvalue=15) Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
7..4 | RX_DSA2 (initialvalue=15) Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
3..0 | RX_DSA1 (initialvalue=15) Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

### Offset 0x0C00: RX1_DSA_ATR(255:0) Register Array (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|DSA_SETUP_REGS
0x002000
RX1_DSA_ATR
offset=0x0C00 + i*4
Cannot determine accessibility through this path
Total Offset =
0x003C00 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x003C00 + i*4

Initial Values

default | => | 0x0000FFFF

This register is defined in HDL source file dsa_control.v.
It uses RegType RX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

Controls the Rx1 DSAs by accessing the raw attenuation levels.

This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..12 | RX_DSA3_B (initialvalue=15) Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/}
11..8 | RX_DSA3_A (initialvalue=15) Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
7..4 | RX_DSA2 (initialvalue=15) Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
3..0 | RX_DSA1 (initialvalue=15) Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

### Offset 0x1000: TX0_DSA_TABLE_SELECT(255:0) Register Array (W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|DSA_SETUP_REGS
0x002000
TX0_DSA_TABLE_SELECT
offset=0x1000 + i*4
Cannot determine accessibility through this path
Total Offset =
0x004000 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x004000 + i*4

Initial Value not specified

This register is defined in HDL source file dsa_control.v.
It uses RegType DSA_TABLE_CONTROL which is defined in HDL source file dsa_control.v.

Controls the Tx0 DSAs by using the gain table to translate the table index to raw attenuation levels. The register offset (i) is targeting an ATR configuration to store the values from the gain table.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..0w | TABLE_INDEX Gain table index to be used for getting the raw attenuation values.

### Offset 0x1400: TX1_DSA_TABLE_SELECT(255:0) Register Array (W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|DSA_SETUP_REGS
0x002000
TX1_DSA_TABLE_SELECT
offset=0x1400 + i*4
Cannot determine accessibility through this path
Total Offset =
0x004400 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x004400 + i*4

Initial Value not specified

This register is defined in HDL source file dsa_control.v.
It uses RegType DSA_TABLE_CONTROL which is defined in HDL source file dsa_control.v.

Controls the Tx1 DSAs by using the gain table to translate the table index to raw attenuation levels. The register offset (i) is targeting an ATR configuration to store the values from the gain table.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..0w | TABLE_INDEX Gain table index to be used for getting the raw attenuation values.

### Offset 0x1800: RX0_DSA_TABLE_SELECT(255:0) Register Array (W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|DSA_SETUP_REGS
0x002000
RX0_DSA_TABLE_SELECT
offset=0x1800 + i*4
Cannot determine accessibility through this path
Total Offset =
0x004800 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x004800 + i*4

Initial Value not specified

This register is defined in HDL source file dsa_control.v.
It uses RegType DSA_TABLE_CONTROL which is defined in HDL source file dsa_control.v.

Controls the Rx0 DSAs by using the gain table to translate the table index to raw attenuation levels. The register offset (i) is targeting an ATR configuration to store the values from the gain table.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..0w | TABLE_INDEX Gain table index to be used for getting the raw attenuation values.

### Offset 0x1C00: RX1_DSA_TABLE_SELECT(255:0) Register Array (W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|DSA_SETUP_REGS
0x002000
RX1_DSA_TABLE_SELECT
offset=0x1C00 + i*4
Cannot determine accessibility through this path
Total Offset =
0x004C00 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x004C00 + i*4

Initial Value not specified

This register is defined in HDL source file dsa_control.v.
It uses RegType DSA_TABLE_CONTROL which is defined in HDL source file dsa_control.v.

Controls the Rx1 DSAs by using the gain table to translate the table index to raw attenuation levels. The register offset (i) is targeting an ATR configuration to store the values from the gain table.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..0w | TABLE_INDEX Gain table index to be used for getting the raw attenuation values.

### Offset 0x2000: TX0_DSA_TABLE(255:0) Register Array (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|DSA_SETUP_REGS
0x002000
TX0_DSA_TABLE
offset=0x2000 + i*4
Cannot determine accessibility through this path
Total Offset =
0x005000 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x005000 + i*4

Initial Values

default | => | 0x00001F1F

This register is defined in HDL source file dsa_control.v.
It uses RegType TX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

Provides access to the gain table for Tx0.

Each entry i will be saved in the gain table without any implications on HW. Enables SW to use the table index in TX0_DSA_TABLE_SELECT to modify the ATR configurations.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..13 | Reserved
12..8 | TX_DSA2 (initialvalue=31) Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
7..5 | Reserved
4..0 | TX_DSA1 (initialvalue=31) Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

### Offset 0x2400: TX1_DSA_TABLE(255:0) Register Array (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|DSA_SETUP_REGS
0x002000
TX1_DSA_TABLE
offset=0x2400 + i*4
Cannot determine accessibility through this path
Total Offset =
0x005400 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x005400 + i*4

Initial Values

default | => | 0x00001F1F

This register is defined in HDL source file dsa_control.v.
It uses RegType TX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

Provides access to the gain table for Tx1.

Each entry i will be saved in the gain table without any implications on HW. Enables SW to use the table index in TX1_DSA_TABLE_SELECT to modify the ATR configurations.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..13 | Reserved
12..8 | TX_DSA2 (initialvalue=31) Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
7..5 | Reserved
4..0 | TX_DSA1 (initialvalue=31) Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

### Offset 0x2800: RX0_DSA_TABLE(255:0) Register Array (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|DSA_SETUP_REGS
0x002000
RX0_DSA_TABLE
offset=0x2800 + i*4
Cannot determine accessibility through this path
Total Offset =
0x005800 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x005800 + i*4

Initial Values

default | => | 0x0000FFFF

This register is defined in HDL source file dsa_control.v.
It uses RegType RX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

Provides access to the gain table for Rx0.

Each entry i will be saved in the gain table without any implications on HW. Enables SW to use the table index in RX0_DSA_TABLE_SELECT to modify the ATR configurations.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..12 | RX_DSA3_B (initialvalue=15) Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/}
11..8 | RX_DSA3_A (initialvalue=15) Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
7..4 | RX_DSA2 (initialvalue=15) Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
3..0 | RX_DSA1 (initialvalue=15) Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

### Offset 0x2C00: RX1_DSA_TABLE(255:0) Register Array (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|DSA_SETUP_REGS
0x002000
RX1_DSA_TABLE
offset=0x2C00 + i*4
Cannot determine accessibility through this path
Total Offset =
0x005C00 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x005C00 + i*4

Initial Values

default | => | 0x0000FFFF

This register is defined in HDL source file dsa_control.v.
It uses RegType RX_DSA_CONTROL which is defined in HDL source file dsa_control.v.

Provides access to the gain table for Rx1.

Each entry i will be saved in the gain table without any implications on HW. Enables SW to use the table index in RX1_DSA_TABLE_SELECT to modify the ATR configurations.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..12 | RX_DSA3_B (initialvalue=15) Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/}
11..8 | RX_DSA3_A (initialvalue=15) Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
7..4 | RX_DSA2 (initialvalue=15) Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
3..0 | RX_DSA1 (initialvalue=15) Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).

# GPIO_REGMAP

## GPIO_REGMAP_WINDOWS

### Offset 0x0000: BASE_WINDOW_GPIO Window (R|W)

Target regmap = BASIC_REGS_REGMAP

(show extended info)

Port GPIO
BASE_WINDOW_GPIO
offset=0x0000
size=0x20 (32 bytes)
Total Offset =
0x000000

This window is defined in HDL source file zbx_top_cpld.v.

### Offset 0x1000: DB_CONTROL_WINDOW_GPIO Window (R|W)

Target regmap = DB_CONTROL_REGMAP

(show extended info)

Port GPIO
DB_CONTROL_WINDOW_GPIO
offset=0x1000
size=0x5000 (20 Kbytes)
Total Offset =
0x001000

This window is defined in HDL source file zbx_top_cpld.v.

# LED_SETUP_REGMAP

## LED_SETUP_REGISTERS

Contains registers that control the LEDs.

### Offset 0x0000: LED_CONTROL(255:0) Register Array (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|LED_SETUP_REGS
0x000400
LED_CONTROL
offset=0x0000 + i*4
Cannot determine accessibility through this path
Total Offset =
0x001400 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x001400 + i*4

Initial Values

default | => | 0x00000000

This register is defined in HDL source file led_control.v.
It uses RegType LED_CONTROL_TYPE which is defined in HDL source file led_control.v.

Defines LED functionality.
This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.

Bits | Name
31..24 | Reserved
23..19 | Reserved
18..17 | CH1_TRX1_LED_EN (initialvalue=0) This bitfield controls the RG LED Bit 15 controls the Ch1 Rx Green LED Bit 14 controls the Ch1 Tx Red LED
16 | CH1_RX2_LED_EN (initialvalue=0) Enables the Ch1 Rx2 Green LED
15..8 | Reserved
7..3 | Reserved
2..1 | CH0_TRX1_LED_EN (initialvalue=0) This bitfield controls the RG LED Bit 6 controls the Ch0 Rx Green LED Bit 7 controls the Ch0 Tx Red LED
0 | CH0_RX2_LED_EN (initialvalue=0) Enables the Ch0 Rx2 Green LED

# LO_CONTROL_REGMAP

## LO_SPI_REGISTERS

Controls the SPI transaction to the LMX2572

### LO_CHIP_SELECT Enumeration

Value | Name
0 | TX0_LO1
1 | TX0_LO2
2 | TX1_LO1
3 | TX1_LO2
4 | RX0_LO1
5 | RX0_LO2
6 | RX1_LO1
7 | RX1_LO2

This enumerated type is defined in HDL source file lo_control.v.

### Offset 0x0000: LO_SPI_SETUP Register (W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|LO_CONTROL_REGS
0x000020
LO_SPI_SETUP
offset=0x0000
Total Offset =
0x001020
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Total Offset =
0x001020

Initial Value = 0x00000000

This register is defined in HDL source file lo_control.v.

This register sets up the SPI transaction to read/write to/from to the LMX2572.

Bits | Name
31..29 | Reserved
28w | LO_SPI_START_TRANSACTION (Strobe, initialvalue=0) Strobe this bit high to start the SPI transaction with the bitfields below
27 | Reserved
26..24w | LO_SELECT (Strobe, initialvalue=TX0_LO1) Sets the CS to the selected LO. The CS will assert until after LO_SPI_START_TRANSACTION has been asserted. The values for this bitfield are in the LO_CHIP_SELECT table. (show here)
Value | Name
0 | TX0_LO1
1 | TX0_LO2
2 | TX1_LO1
3 | TX1_LO2
4 | RX0_LO1
5 | RX0_LO2
6 | RX1_LO1
7 | RX1_LO2
This enumerated type is defined in HDL source file lo_control.v.
23w | LO_SPI_RD (initialvalue=0) Set this bit to '1' to read from the LMX2572. Set this bit to '0' to write to the LMX2572.
22..16w | LO_SPI_WT_ADDR (initialvalue=0) 7 bit address of the LMX2572
15..0w | LO_SPI_WT_DATA (initialvalue=0) Write Data to the LMX2572

### Offset 0x0000: LO_SPI_STATUS Register (R)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|LO_CONTROL_REGS
0x000020
LO_SPI_STATUS
offset=0x0000
Total Offset =
0x001020
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Total Offset =
0x001020

Initial Value = 0x00000000

This register is defined in HDL source file lo_control.v.

This register returns the SPI master status, and also returns the read data from the LMX2572

Bits | Name
31 | LO_SPI_DATA_VALID (initialvalue=0) Returns '1' when a read SPI transaction is complete. This bit will remain high until a new SPI transaction has started. i.e. LO_SPI_START_TRANSACTION is strobed. Poll this when expecting data from a read transaction.
30 | LO_SPI_READY (initialvalue=0) If this bit returns '1' then LMX2572 is ready for transaction. If it returns '0' then it is busy with a previous SPI transaction. Poll this bit before starting a SPI transaction.
29..27 | Reserved
26..24 | LO_SELECT_STATUS (initialvalue=TX0_LO1) Returns the current selected CS. This bitfield will return the value written to LO_SELECT bitfield in the LO_SPI_SETUP reg. The values for this bitfield are in the LO_CHIP_SELECT table. (show here)
Value | Name
0 | TX0_LO1
1 | TX0_LO2
2 | TX1_LO1
3 | TX1_LO2
4 | RX0_LO1
5 | RX0_LO2
6 | RX1_LO1
7 | RX1_LO2
This enumerated type is defined in HDL source file lo_control.v.
23 | Reserved
22..16 | LO_SPI_RD_ADDR (initialvalue=0) Returns the address of the current SPI address setup
15..0 | LO_SPI_RD_DATA (initialvalue=0) Returns the data of the SPI read. This bitfield will return 0x0000 until LO_SPI_DATA_VALID is true. This bit field will maintain it's read value until a new SPI transaction has started. i.e. LO_SPI_START_TRANSACTION is strobed.

## LO_SYNC_REGS

Contains registers that control the logic lines in charge of synchronization

### Offset 0x0004: LO_PULSE_SYNC Register (W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|LO_CONTROL_REGS
0x000020
LO_PULSE_SYNC
offset=0x0004
Total Offset =
0x001024
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Total Offset =
0x001024

Initial Value = 0x00000000

This register is defined in HDL source file lo_control.v.

Controls pulses driven to the SYNC pins of the LMX2572 chips

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..9 | Reserved
8w | BYPASS_SYNC_REGISTER (initialvalue=0) Setting this bit to '1' will ignore writes to the PULSE_X_SYNC fields and allow a buffered input SYNC pulse to be driven out instead.
7w | PULSE_RX1_LO2_SYNC (Strobe, initialvalue=0) Creates a single cycle pulse on the RX1_LO2_SYNC line.
6w | PULSE_RX1_LO1_SYNC (Strobe, initialvalue=0) Creates a single cycle pulse on the RX1_LO1_SYNC line.
5w | PULSE_RX0_LO2_SYNC (Strobe, initialvalue=0) Creates a single cycle pulse on the RX0_LO2_SYNC line.
4w | PULSE_RX0_LO1_SYNC (Strobe, initialvalue=0) Creates a single cycle pulse on the RX0_LO1_SYNC line.
3w | PULSE_TX1_LO2_SYNC (Strobe, initialvalue=0) Creates a single cycle pulse on the TX1_LO2_SYNC line.
2w | PULSE_TX1_LO1_SYNC (Strobe, initialvalue=0) Creates a single cycle pulse on the TX1_LO1_SYNC line.
1w | PULSE_TX0_LO2_SYNC (Strobe, initialvalue=0) Creates a single cycle pulse on the TX0_LO2_SYNC line.
0w | PULSE_TX0_LO1_SYNC (Strobe, initialvalue=0) Creates a single cycle pulse on the TX0_LO1_SYNC line.

# POWER_REGS_REGMAP

This regmap has readablestrobes="true", so all strobe bits are readable by default. This attribute should only be used for older regmaps to maintain compatibility with previous versions of XmlParse. New regmaps should either use the 'clearable' attribute or should explicitly define readable bits in the same bit position as the strobe bits.

## POWER_REGS_REGISTERS

This regmap contains the registers to control the power supplies and the clock buffer for PLL reference clock.

### Offset 0x0000: RF_POWER_CONTROL Register (R|W)

(show extended info)

Port SPI
SPI_REGMAP|POWER_REGS
0x000040
RF_POWER_CONTROL
offset=0x0000
Total Offset =
0x000040

Initial Value = 0x00000000

This register is defined in HDL source file power_regs.v.

This register controls power supply enables to the Tx/Rx amps, switch control, and clk buffers. During normal operations, all three power supplies should be enabled.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..3 | Reserved
2 | ENABLE_3v3 (initialvalue=0) This power supply sources the switch control, and the clock buffers. By default this power supply is off. The internal LOs will not work unless this bit is enabled.
1 | ENABLE_RX_7V0 (initialvalue=0) This power supply sources the Rx0 and Rx1 amps. By default this power supply is off.The Rx0/1 path will not be active unless this power supply is enabled. Disabling this bit is similar to RX RF blanking note to digital engineer, this is Pos7v0B
0 | ENABLE_TX_7V0 (initialvalue=0) This power supply sources the Tx0 and Tx1 amps. By default this power supply is off. The Tx0/1 path will not be active unless this power supply is enabled. Disabling this bit is similar to TX RF blanking note to digital engineer, this is Pos7v0A

### Offset 0x0004: RF_POWER_STATUS Register (R)

(show extended info)

Port SPI
SPI_REGMAP|POWER_REGS
0x000040
RF_POWER_STATUS
offset=0x0004
Total Offset =
0x000044

Initial Value not specified

This register is defined in HDL source file power_regs.v.

Returns status of PowerGood indicators across the daughterboard.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..2 | Reserved
1 | P7V_B_STATUS Returns status of 7V switching regulator B.
0 | P7V_A_STATUS Returns status of 7V switching regulator A.

### Offset 0x0008: PRC_CONTROL Register (R|W)

(show extended info)

Port SPI
SPI_REGMAP|POWER_REGS
0x000040
PRC_CONTROL
offset=0x0008
Total Offset =
0x000048

Initial Value = 0x00000000

This register is defined in HDL source file power_regs.v.

Offers ability to enable or disable the PLL reference clock.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..8 | Reserved
7..1 | Reserved
0 | PLL_REF_CLOCK_ENABLE (initialvalue=0) If set PLL reference clock is enabled.

# RECONFIG_REGMAP

## RECONFIG_REGS

These registers are used to upload and verify a new primary image to the Max 10 FPGA on-chip flash when configured to support dual configuration images. The steps below outline the process of verifying/preparing the new image to be written, erasing the current image, writing the new image, and verifying the new image was successfully written.

Prepare the data...

1. The Max 10 FPGA build should generate a *cfm0_auto.rpd file The *.rpd file is a "raw programming data" file holding all data related to the configuration image (CFM0). There are two important items to note regarding the addresses. First the *rpd data uses byte addresses. Second, the start/end addresses defined by FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses

2. As a sanity check, verify the size of the raw programming data for CFM0 correspond to the address range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by reading the values from FLASH_CFM0_START_ADDR_REG and FLASH_CFM0_END_ADDR, subtract both values, add one and multiply by four.

3. Having passed the sanity check the *.rpd data must now be manipulated into the form required by Altera's on-chip flash IP. Two operations must be performed. First the data must be converted from bytes to 32-bit words. Second the bit order must be reversed. This is illustrated in in the following table which shows byte address and data from the *.rpd file compared to the word address and data to be written to the on-chip flash.

   .Map Addr | .Map Data | Flash Addr | Flash Data
   0x2B800 | 0x01 | 0xAC00 | 0x8040C020
   0x2B801 | 0x02
   0x2B802 | 0x03
   0x2B803 | 0x04
   0x2B804 | 0x05 | 0xAC01 | 0xA060E010
   0x2B805 | 0x06
   0x2B806 | 0x07
   0x2B807 | 0x08

4. The resulting set of flash address data pairs should be used when writing FLASH_ADDR_REG and FLASH_WRITE_DATA_REG to update the CFM0 image. However, prior to writing the new image the old image must be erased.

Erase the current primary flash image...

1. Read FLASH_STATUS_REG and verify no error bits are asserted and that all read, write, and erase operations are idle.

2. Disable write protection of the flash by strobing the FLASH_DISABLE_WP_STB bit of FLASH_CONTROL_REG.

3. Verify write protection is disabled and no errors are present by reading FLASH_STATUS_REG.

4. Initiate the erase operation by setting FLASH_ERASE_SECTOR and strobing FLASH_ERASE_STB of FLASH_CONTROL_REG.

5. Poll the FLASH_ERASE_IDLE bit of FLASH_STATUS_REG until it de-asserts indicating the erase operation is complete, then verify the operation was successful by checking that the FLASH_ERASE_ERR bit is de-asserted. Erase operations are expected to take a maximum of 350 msec. Upon completion of the erase operation write protection will remain disabled.

6. Erase additional sectors as required (see FLASH_ERASE_SECTOR for details) by restarting with first step.

Write the new primary flash image...

1. Read FLASH_STATUS_REG and verify no error bits are asserted, all read, write, and erase operations are idle, and write protection is disabled.

2. Set the target address for the write to the Max 10 on-chip flash by writing value from FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.

3. Set the data to be written to this address by writing the new 32-bit word of the new image to FLASH_WRITE_DATA_REG.

4. Initiate the write by strobing FLASH_WRITE_STB of FLASH_CONTROL_REG.

5. Poll the FLASH_WRITE_IDLE bit of FLASH_STATUS_REG until it de-asserts indicating the write operation is complete, then verify the operation was successful by checking that the FLASH_WRITE_ERR bit is de-asserted. Write operations are expected to take a maximum of 550 usec.

6. Upon completion of the write operation return to step 2, incrementing the target address by one, and writing the next 32-bit word to Max10FlashWriteDatReg. If this was the last write, indicated by writing to FLASH_PRIMARY_IMAGE_END_ADDR, proceed to the next step to enable write protection.

7. After writing the new image enable write protection by strobing the FLASH_ENABLE_WP_STB bit of FLASH_CONTROL_REG.

Verify the new primary flash image...

1. Read FLASH_STATUS_REG and verify no error bits are asserted and that all read, write, and erase operations are idle.

2. Set the target address for the read in the Max 10 on-chip flash by writing value from FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.

3. Initiate the read by strobing FLASH_READ_STB of FLASH_CONTROL_REG.

4. Poll the FLASH_READ_IDLE bit of FLASH_STATUS_REG until it de-asserts indicating the read operation is complete, then verify the operation was successful by checking that the FLASH_READ_ERR bit is de-asserted. There is no guidance on exactly how long reads take to complete, but they are expected to be fairly quick. A very conservative timeout on this polling would be similar to that used for write operations.

5. Upon completion of the read operation the resulting data returned by the on-chip flash will be available in Max10FlashReadDatReg. Read this register, compare to expected value previously written, and ensure they match.

6. Return to step 2, incrementing the target address by one. If this was the last read verification is complete and no further action is required.

After the flash has been erased, programmed, and verified, a power cycle is required for the new image to become active.

### FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration

These values are the start and end address of the CFM image flash sector from Intel's On-Chip Flash IP Generator. Be aware that three different values exist per each of the two supported MAX10 variants: 10M04 and 10M08 Note that the values given in the IP generator are byte based where the values of this enum are U32 based (divided by 4).

Value | Name
Dec | Hex
4096 | 0x01000 | FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04
8192 | 0x02000 | FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08
39936 | 0x09C00 | FLASH_PRIMARY_IMAGE_START_ADDR_10M04
44032 | 0x0AC00 | FLASH_PRIMARY_IMAGE_START_ADDR_10M08
75775 | 0x127FF | FLASH_PRIMARY_IMAGE_END_ADDR_10M04
79871 | 0x137FF | FLASH_PRIMARY_IMAGE_END_ADDR_10M08

This enumerated type is defined in HDL source file reconfig_engine.v.

### Offset 0x0000: FLASH_STATUS_REG Register (R)

(show extended info)

Port SPI
SPI_REGMAP|RECONFIG
0x000020
FLASH_STATUS_REG
offset=0x0000
Total Offset =
0x000020

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..24 | Reserved
23..17 | Reserved
16 | FLASH_MEM_INIT_ENABLED This bit is asserted when the flash can hold an image with memory initialization.
15..14 | Reserved
13 | FLASH_WRITE_ERR This bit is asserted when write operation fails. Clear this error by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In the event of a write error... the primary configuration image may be corrupted, and power cycling the board may result unknown behavior. write protection of the flash will automatically be re-enabled. attempts to disable write protection will be ignored. attempts to read/write/erase the flash will be ignored.
12 | FLASH_WRITE_IDLE This bit is de-asserted when a write operation is in progress. Poll this bit after strobing the FLASH_WRITE_STB bit of FLASH_CONTROL_REG to determine when the write operation has completed, then check the FLASH_WRITE_ERR bit to verify the operation was successful.
11..10 | Reserved
9 | FLASH_ERASE_ERR This bit is asserted when an erase operation fails. Clear this error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In the event of an erase error... the primary configuration image may be corrupted, and power cycling the board may result in unknown behavior. write protection of the flash will automatically be re-enabled. attempts to disable write protection will be ignored. attempts to read/write/erase the flash will be ignored.
8 | FLASH_ERASE_IDLE This bit is de-asserted when an erase operation is in progress. Poll this bit after strobing the FLASH_ERASE_STB bit of FLASH_CONTROL_REG to determine when the erase operation has completed, then check the FLASH_ERASE_ERR bit to verify the operation was successful.
7..6 | Reserved
5 | FLASH_READ_ERR This bit is asserted when a read operation fails. Clear this error by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the event of a read error... the data in FLASH_READ_DATA_REG is invalid. attempts to disable write protection will be ignored. attempts to read/write/erase the flash will be ignored.
4 | FLASH_READ_IDLE This bit is de-asserted when a read operation is in progress. Poll this bit after strobing the FLASH_READ_STB bit of FLASH_CONTROL_REG to determine when the read operation has completed, then check the FLASH_READ_ERR bit to verify the operation was successful.
3..1 | Reserved
0 | FLASH_WP_ENABLED This bit is asserted when the flash is write protected and de-asserted when write protection is disabled. Write protection must be enabled prior to performing read operations. Write protection must be disabled prior to performing write and erase operations.

### Offset 0x0004: FLASH_CONTROL_REG Register (W)

(show extended info)

Port SPI
SPI_REGMAP|RECONFIG
0x000020
FLASH_CONTROL_REG
offset=0x0004
Total Offset =
0x000024

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..24 | Reserved
23..16 | Reserved
15..11 | Reserved
10w | CLEAR_FLASH_ERASE_ERROR_STB (Strobe) Strobe this bit to clear an erase error.
9w | CLEAR_FLASH_WRITE_ERROR_STB (Strobe) Strobe this bit to clear a write error.
8w | CLEAR_FLASH_READ_ERROR_STB (Strobe) Strobe this bit to clear a read error.
7..5w | FLASH_ERASE_SECTOR (Strobe) Defines the sector to be erased. Has to be set latest with the write access which starts the erase operation by strobing FLASH_ERASE_STB. With 10M04 variants, if the flash is configured to support memory initialization (see FLASH_MEM_INIT_ENABLED flag) the sectors 2 to 4 have to be erased. If the flag is not asserted only sector 4 has to be erased. With 10M08 variants, the sectors to be erased are 3 to 5 when using memory initialization or only sector 5 otherwise.
4w | FLASH_ERASE_STB (Strobe) Strobe this bit to erase the primary Max10 configuration image (CFM0). Prior to strobing this bit verify no other write or erase operations are in progress, write protection is disabled, and no error bits are asserted by reading FLASH_STATUS_REG. Attempts to erase the primary image while other write or erase operations are in progress will be ignored. Attempts to erase the primary image when write protection is enabled will be ignored. Strobing this bit and FLASH_WRITE_STB simultaneously will result both the erase and the write operation being ignored, both corresponding error bits being set, and write protection being re-enabled. After strobing this bit poll the FLASH_ERASE_IDLE and FLASH_ERASE_ERR bits of FLASH_STATUS_REG to determine when the erase operation is complete and if it was successful.
3w | FLASH_WRITE_STB (Strobe) Strobe this bit to write the data contained in FLASH_WRITE_DATA_REG to the flash address identified in FLASH_ADDR_REG. The flash must be erased before writing new data. Prior to strobing this bit verify write protection is disabled, no other write or erase operations are in progress, and no error bits are asserted by reading FLASH_STATUS_REG. Attempts to write data while other write or erase operations are in progress will be ignored. Attempts to write data with write protection enabled will be ignored. Strobing this bit and FLASH_ERASE_STB simultaneously will result in both the write and erase operation being ignored, both corresponding error bits being set, and write protection being re-enabled. After strobing this bit poll theMax10FlashWriteIdle and FLASH_WRITE_ERR bits of FLASH_STATUS_REG to determine when the write operation is complete and if it was successful.
2w | FLASH_READ_STB (Strobe) Strobe this bit to read data from the flash address identified in FLASH_ADDR_REG. Prior to strobing this bit verify no read, write, or erase operations are in progress, no error bits are asserted, and write protection is enabled by reading FLASH_STATUS_REG. Attempts to read data while other operations are in progress or while write protection is disabled will be ignored. After strobing this bit poll the FLASH_READ_IDLE and FLASH_READ_ERR bits of FLASH_STATUS_REG to determine when the read operation is complete and if it was successful. Upon successful completion the data read from flash will be available in FLASH_READ_DATA_REG.
1w | FLASH_DISABLE_WP_STB (Strobe) Strobe this bit to disable write protection to the section of the Max 10 on-chip flash storing the primary configuration image (CFM0). Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to determine the current state of write protection. Prior to strobing this bit verify no read operations are in progress and no error bits are asserted by reading FLASH_STATUS_REG. Attempts to disable write protection while a read is in progress will be ignored. Attempts to disable write protection will be ignored if this bit is strobed simultaneously with either FLASH_READ_STB or FLASH_ENABLE_WP_STB. Write protection must be disabled prior to performing erase or write operations. Upon completion of erase/write operations write protection will remain disabled. When not actively erasing or writing a new image write protection should be enabled to avoid data corruption.
0w | FLASH_ENABLE_WP_STB (Strobe) Strobe this bit to enable write protection to the section of the Max 10 on-chip flash storing the primary configuration image (CFM0). Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to determine the current state of write protection. Prior to strobing this bit verify no write or erase operations are in progress and no error bits are asserted by reading FLASH_STATUS_REG. Attempts to enable write protection while erase or write operations are in progress will be ignored. Write protection must be enabled prior to performing read operations. Write protection should be enabled after completing write or erase operations to prevent data corruption.

### Offset 0x0008: FLASH_ADDR_REG Register (R|W)

(show extended info)

Port SPI
SPI_REGMAP|RECONFIG
0x000020
FLASH_ADDR_REG
offset=0x0008
Total Offset =
0x000028

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..24 | Reserved
23..17 | Reserved
16..0 | FLASH_ADDR This field holds the target address for the next read or write operation. Set this field prior to strobing the FLASH_WRITE_STB and FLASH_READ_STB bits of FLASH_CONTROL_REG. Valid addresses are defined by the FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration.

### Offset 0x000C: FLASH_WRITE_DATA_REG Register (W)

(show extended info)

Port SPI
SPI_REGMAP|RECONFIG
0x000020
FLASH_WRITE_DATA_REG
offset=0x000C
Total Offset =
0x00002C

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..0w | FLASH_WRITE_DATA Data in this register will be written to the flash at the address identified in FLASH_ADDR_REG when a successful write operation is executed.

### Offset 0x0010: FLASH_READ_DATA_REG Register (R)

(show extended info)

Port SPI
SPI_REGMAP|RECONFIG
0x000020
FLASH_READ_DATA_REG
offset=0x0010
Total Offset =
0x000030

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..0 | FLASH_READ_DATA This register contains data read from the flash address identified in FLASH_ADDR_REG after a successful read operation is executed.

### Offset 0x0014: FLASH_CFM0_START_ADDR_REG Register (R)

(show extended info)

Port SPI
SPI_REGMAP|RECONFIG
0x000020
FLASH_CFM0_START_ADDR_REG
offset=0x0014
Total Offset =
0x000034

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..0 | FLASH_CFM0_START_ADDR Start address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM).

### Offset 0x0018: FLASH_CFM0_END_ADDR_REG Register (R)

(show extended info)

Port SPI
SPI_REGMAP|RECONFIG
0x000020
FLASH_CFM0_END_ADDR_REG
offset=0x0018
Total Offset =
0x000038

Initial Value not specified

This register is defined in HDL source file reconfig_engine.v.

Bits | Name
31..0 | FLASH_CFM0_END_ADDR Last address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM).

# SPI_REGMAP

## SPI_REGMAP_WINDOWS

### Offset 0x0000: BASE_WINDOW_SPI Window (R|W)

Target regmap = BASIC_REGS_REGMAP

(show extended info)

Port SPI
BASE_WINDOW_SPI
offset=0x0000
size=0x20 (32 bytes)
Total Offset =
0x000000

This window is defined in HDL source file zbx_top_cpld.v.

### Offset 0x0020: RECONFIG Window (R|W)

Target regmap = RECONFIG_REGMAP

(show extended info)

Port SPI
RECONFIG
offset=0x0020
size=0x20 (32 bytes)
Total Offset =
0x000020

This window is defined in HDL source file zbx_top_cpld.v.

### Offset 0x0040: POWER_REGS Window (R|W)

Target regmap = POWER_REGS_REGMAP

(show extended info)

Port SPI
POWER_REGS
offset=0x0040
size=0x20 (32 bytes)
Total Offset =
0x000040

This window is defined in HDL source file zbx_top_cpld.v.

### Offset 0x1000: DB_CONTROL_WINDOW_SPI Window (R|W)

Target regmap = DB_CONTROL_REGMAP

(show extended info)

Port SPI
DB_CONTROL_WINDOW_SPI
offset=0x1000
size=0x5000 (20 Kbytes)
Total Offset =
0x001000

This window is defined in HDL source file zbx_top_cpld.v.

# SWITCH_SETUP_REGMAP

## SWITCH_SETUP_REGISTERS

The following registers are used to control the path that the RF signal takes for both Tx and Rx

### Offset 0x0000: TX0_PATH_CONTROL(255:0) Register Array (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|SWITCH_SETUP_REGS
0x001000
TX0_PATH_CONTROL
offset=0x0000 + i*4
Cannot determine accessibility through this path
Total Offset =
0x002000 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x002000 + i*4

Initial Values

default | => | 0x00000000

This register is defined in HDL source file switch_control.v.
It uses RegType TX_PATH_CONTROL which is defined in HDL source file switch_control.v.

This Register controls the switches along the Tx path. Note: default values refer to the RX0 path. RX1 has the same defaults, but their bit values may differ.
This Register controls the Tx0 paths.
This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.

Bits | Name
31..27 | Reserved
26 | TX_SWITCH_14 (initialvalue=0) Control for Tx Switch 13 LO path. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx external LO path Write 1 to select Tx internal LO path FOR TX1: Write 0 to select Tx internal LO path Write 1 to select Tx external LO path
25 | Reserved
24 | TX_SWITCH_13 (initialvalue=0) Control for Tx0 Switch 13 LO path. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx0 internal LO path Write 1 to select Tx0 external LO path FOR TX1: Write 0 to select Tx0 external LO path Write 1 to select Tx0 internal LO path
23..22 | Reserved
21..20 | TX_SWITCH_11 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 11. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx Rx path, RX_SWITCH_1 must also select the correct path Write 1 to select Tx highband amp path. TX_SWITCH_10 must also match this path. Write 2 to select Tx lowband amp path. TX_SWITCH_10 must also match this path. Write 3 to select Tx amplifier bypass path FOR TX1: Write 0 to select Tx Rx path, RX_SWITCH_1 must also select the correct path Write 1 to select Tx amplifier bypass path Write 2 to select Tx lowband amp path. TX_SWITCH_10 must also match this path. Write 3 to select Tx highband amp path. TX_SWITCH_10 must also match this path.
19..18 | TX_SWITCH_10 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 10. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx amplifier bypass path Write 1 to select Tx calibration loopback path Write 2 to select Tx lowband amp path. TX_Switch_11 must also match this path. Write 3 to select Tx highband amp path. TX_Switch_11 must also match this path. FOR TX1: Write 0 to select Tx highband amp path. TX_Switch_11 must also match this path. Write 1 to select Tx lowband amp path. TX_Switch_11 must also match this path. Write 2 to select Tx amplifier bypass path Write 3 to select Tx calibration loopback path
17..16 | TX_SWITCH_9 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 9. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx RF3 path, 2.3 GHz to 3.1 GHz Write 1 to select Tx RF1 path, 1.0 MHz to 1.95 GHz Write 2 to select Tx RF2 path, 1.95 GHz to 2.3 GHz Write 3 to select Tx RF4 path, 3.1 GHz to 8.0 GHz FOR TX1: Write 0 to select Tx RF4 path, 3.1 GHz to 8.0 GHz Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz Write 3 to select Tx RF3 path, 2.3 GHz to 3.1 GHz
15 | Reserved
14..12 | TX_SWITCH_8 (initialvalue=0) Control for Tx Switch 8, note this is one hot encoding and not binary. The configuration of this switch changes between TX paths. FOR TX0: Write 1 to select Tx RF3 path, 2.3 GHz to 3.1 GHz Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz Write 4 to select Tx RF2 path, 1.95 GHz to 2.3 GHz FOR TX1: Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz Write 4 to select Tx RF3 path, 2.3 GHz to 3.1 GHz *All other values are invalid
11..10 | TX_SWITCH_7 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 7. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select 50 ohm termination Write 1 to select no connect Write 2 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz Write 3 to select Tx lowbands RF1, RF2, RF3 path. See TX_SWITCH_8 for those controls FOR TX1: Write 0 to select Tx lowbands RF1, RF2, RF3 path. See TX_SWITCH_8 for those controls Write 1 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz Write 2 to select no connect Write 3 to select 50 ohm termination
9..8 | TX_SWITCH_6 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 6. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz Write 3 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See TX_SWITCH_5 for those controls FOR TX1: Write 0 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See TX_SWITCH_5 for those controls Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz Write 2 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz Write 3 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz
7..6 | TX_SWITCH_5 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 5. This switch path is only taken if TX_SWITCH_6 is set to 0. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz Write 3 to select Tx If1 Filter 50 ohm termination FOR TX1: Write 0 to select Tx If1 Filter 50 ohm termination Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz
5..4 | TX_SWITCH_4 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 4. This switch path is only taken if TX_SWITCH_4 is set to 0. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select 50 ohm termination Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz FOR TX1: Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz Write 3 to select 50 ohm termination
3..2 | TX_SWITCH_3 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 3. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See TX_SWITCH_4 for those controls Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz Write 2 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz Write 3 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz FOR TX1: Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz Write 3 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See TX_SWITCH_4 for those controls
1 | Reserved
0 | TX_SWITCH_1_2 (initialvalue=0) Write 0 to select Tx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz Write 1 to select Tx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz

### Offset 0x0400: TX1_PATH_CONTROL(255:0) Register Array (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|SWITCH_SETUP_REGS
0x001000
TX1_PATH_CONTROL
offset=0x0400 + i*4
Cannot determine accessibility through this path
Total Offset =
0x002400 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x002400 + i*4

Initial Values

default | => | 0x00000000

This register is defined in HDL source file switch_control.v.
It uses RegType TX_PATH_CONTROL which is defined in HDL source file switch_control.v.

This Register controls the switches along the Tx path. Note: default values refer to the RX0 path. RX1 has the same defaults, but their bit values may differ.
This Register controls the Tx1 paths.
This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.

Bits | Name
31..27 | Reserved
26 | TX_SWITCH_14 (initialvalue=0) Control for Tx Switch 13 LO path. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx external LO path Write 1 to select Tx internal LO path FOR TX1: Write 0 to select Tx internal LO path Write 1 to select Tx external LO path
25 | Reserved
24 | TX_SWITCH_13 (initialvalue=0) Control for Tx0 Switch 13 LO path. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx0 internal LO path Write 1 to select Tx0 external LO path FOR TX1: Write 0 to select Tx0 external LO path Write 1 to select Tx0 internal LO path
23..22 | Reserved
21..20 | TX_SWITCH_11 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 11. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx Rx path, RX_SWITCH_1 must also select the correct path Write 1 to select Tx highband amp path. TX_SWITCH_10 must also match this path. Write 2 to select Tx lowband amp path. TX_SWITCH_10 must also match this path. Write 3 to select Tx amplifier bypass path FOR TX1: Write 0 to select Tx Rx path, RX_SWITCH_1 must also select the correct path Write 1 to select Tx amplifier bypass path Write 2 to select Tx lowband amp path. TX_SWITCH_10 must also match this path. Write 3 to select Tx highband amp path. TX_SWITCH_10 must also match this path.
19..18 | TX_SWITCH_10 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 10. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx amplifier bypass path Write 1 to select Tx calibration loopback path Write 2 to select Tx lowband amp path. TX_Switch_11 must also match this path. Write 3 to select Tx highband amp path. TX_Switch_11 must also match this path. FOR TX1: Write 0 to select Tx highband amp path. TX_Switch_11 must also match this path. Write 1 to select Tx lowband amp path. TX_Switch_11 must also match this path. Write 2 to select Tx amplifier bypass path Write 3 to select Tx calibration loopback path
17..16 | TX_SWITCH_9 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 9. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx RF3 path, 2.3 GHz to 3.1 GHz Write 1 to select Tx RF1 path, 1.0 MHz to 1.95 GHz Write 2 to select Tx RF2 path, 1.95 GHz to 2.3 GHz Write 3 to select Tx RF4 path, 3.1 GHz to 8.0 GHz FOR TX1: Write 0 to select Tx RF4 path, 3.1 GHz to 8.0 GHz Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz Write 3 to select Tx RF3 path, 2.3 GHz to 3.1 GHz
15 | Reserved
14..12 | TX_SWITCH_8 (initialvalue=0) Control for Tx Switch 8, note this is one hot encoding and not binary. The configuration of this switch changes between TX paths. FOR TX0: Write 1 to select Tx RF3 path, 2.3 GHz to 3.1 GHz Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz Write 4 to select Tx RF2 path, 1.95 GHz to 2.3 GHz FOR TX1: Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz Write 4 to select Tx RF3 path, 2.3 GHz to 3.1 GHz *All other values are invalid
11..10 | TX_SWITCH_7 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 7. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select 50 ohm termination Write 1 to select no connect Write 2 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz Write 3 to select Tx lowbands RF1, RF2, RF3 path. See TX_SWITCH_8 for those controls FOR TX1: Write 0 to select Tx lowbands RF1, RF2, RF3 path. See TX_SWITCH_8 for those controls Write 1 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz Write 2 to select no connect Write 3 to select 50 ohm termination
9..8 | TX_SWITCH_6 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 6. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz Write 3 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See TX_SWITCH_5 for those controls FOR TX1: Write 0 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See TX_SWITCH_5 for those controls Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz Write 2 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz Write 3 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz
7..6 | TX_SWITCH_5 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 5. This switch path is only taken if TX_SWITCH_6 is set to 0. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz Write 3 to select Tx If1 Filter 50 ohm termination FOR TX1: Write 0 to select Tx If1 Filter 50 ohm termination Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz
5..4 | TX_SWITCH_4 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 4. This switch path is only taken if TX_SWITCH_4 is set to 0. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select 50 ohm termination Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz FOR TX1: Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz Write 3 to select 50 ohm termination
3..2 | TX_SWITCH_3 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Tx Switch 3. The configuration of this switch changes between TX paths. FOR TX0: Write 0 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See TX_SWITCH_4 for those controls Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz Write 2 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz Write 3 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz FOR TX1: Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz Write 3 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See TX_SWITCH_4 for those controls
1 | Reserved
0 | TX_SWITCH_1_2 (initialvalue=0) Write 0 to select Tx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz Write 1 to select Tx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz

### Offset 0x0800: RX0_PATH_CONTROL(255:0) Register Array (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|SWITCH_SETUP_REGS
0x001000
RX0_PATH_CONTROL
offset=0x0800 + i*4
Cannot determine accessibility through this path
Total Offset =
0x002800 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x002800 + i*4

Initial Values

default | => | 0x00000000

This register is defined in HDL source file switch_control.v.
It uses RegType RX_PATH_CONTROL which is defined in HDL source file switch_control.v.

This Register controls switches along Rx paths. Note: default values refer to the RX0 path. RX1 has the same defaults, but their bit values may differ.
This Register controls the Rx0 paths.
This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.

Bits | Name
31..24 | Reserved
23 | Reserved
22..20 | RX_SWITCH_11 (initialvalue=0) Control for Rx Switch 11, note to digital designer: Control V2 is pulled to ground. The configuration of this switch changes between RX paths. FOR RX0: Write 1 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz Write 4 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz FOR RX1: Write 1 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz Write 4 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz
19 | Reserved
18 | RX_SWITCH_10 (initialvalue=0) Control for Rx Switch 10 LO path. The configuration of this switch changes between RX paths. FOR RX0: Write 0 to select Rx internal LO path Write 1 to select Rx external LO path FOR RX1: Write 0 to select Rx external LO path Write 1 to select Rx internal LO path
17 | Reserved
16 | RX_SWITCH_9 (initialvalue=0) Control for Rx Switch 9 LO path. The configuration of this switch changes between RX paths. FOR RX0: Write 0 to select Rx internal LO path Write 1 to select Rx external LO path FOR RX1: Write 0 to select Rx external LO path Write 1 to select Rx internal LO path
15 | Reserved
14 | RX_SWITCH_7_8 (initialvalue=0) Shared control for Rx switch 7 and switch 8. FOR RX0: Write 0 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz Write 1 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz FOR RX1: Write 0 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz Write 1 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz
13..12 | RX_SWITCH_6 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Rx Switch 6. The configuration of this switch changes between RX paths. FOR RX0: Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path FOR RX1: Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path
11..10 | RX_SWITCH_5 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Rx Switch 5. The configuration of this switch changes between RX paths. FOR RX0: Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path FOR RX1: Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path
9 | Reserved
8 | RX_SWITCH_4 (initialvalue=0) note to digital designer: control A is the only control, and control B is tied to ground Control for Rx Switch 4. Write 0 to select Rx RF1/2 lowband path Write 1 to select Rx RF3 highband path
7 | Reserved
6..4 | RX_SWITCH_3 (initialvalue=0) Control for Rx Switch 3, note this is one hot encoding and not binary. The configuration of this switch changes between RX paths. FOR RX0: Write 1 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz Write 4 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz FOR RX1: Write 1 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz Write 4 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz *All other values are invalid
3 | Reserved
2 | RX_SWITCH_2 (initialvalue=0) note to digital designer: control A is the only control, and control B is pulled high Control for Rx Switch 2. The configuration of this switch changes between RX paths. FOR RX0: Write 0 to select Rx RF3 highband path Write 1 to select Rx RF1/2 lowband path FOR RX1: Write 0 to select Rx RF1/2 lowband path Write 1 to select Rx RF3 highband path
1..0 | RX_SWITCH_1 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Rx Switch 1. The configuration of this switch changes between RX paths. FOR RX0: Write 0 to select Rx calibration loopback Write 1 to select Rx 50 ohm termination path Write 2 to select Tx Rx path, TX_SWITCH_11 must also select the correct path Write 3 to select Rx input port FOR RX1: Write 0 to select Rx calibration loopback Write 1 to select Tx Rx path, TX_SWITCH_11 must also select the correct path Write 2 to select Rx input port Write 3 to select Rx 50 ohm termination path

### Offset 0x0C00: RX1_PATH_CONTROL(255:0) Register Array (R|W)

(show extended info)

Port GPIO
GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO
0x001000
DB_CONTROL_REGMAP|SWITCH_SETUP_REGS
0x001000
RX1_PATH_CONTROL
offset=0x0C00 + i*4
Cannot determine accessibility through this path
Total Offset =
0x002C00 + i*4
Port SPI
SPI_REGMAP|DB_CONTROL_WINDOW_SPI
0x001000
Cannot determine accessibility through this path
Total Offset =
0x002C00 + i*4

Initial Values

default | => | 0x00000000

This register is defined in HDL source file switch_control.v.
It uses RegType RX_PATH_CONTROL which is defined in HDL source file switch_control.v.

This Register controls switches along Rx paths. Note: default values refer to the RX0 path. RX1 has the same defaults, but their bit values may differ.
This Register controls the Rx1 paths.
This register array can hold settings for all ATR configurations. The register index equals the ATR configuration. The active configuration can be selected in ATR_REGMAP. Independently all configurations can be read/written at any time.

Bits | Name
31..24 | Reserved
23 | Reserved
22..20 | RX_SWITCH_11 (initialvalue=0) Control for Rx Switch 11, note to digital designer: Control V2 is pulled to ground. The configuration of this switch changes between RX paths. FOR RX0: Write 1 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz Write 4 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz FOR RX1: Write 1 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz Write 4 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz
19 | Reserved
18 | RX_SWITCH_10 (initialvalue=0) Control for Rx Switch 10 LO path. The configuration of this switch changes between RX paths. FOR RX0: Write 0 to select Rx internal LO path Write 1 to select Rx external LO path FOR RX1: Write 0 to select Rx external LO path Write 1 to select Rx internal LO path
17 | Reserved
16 | RX_SWITCH_9 (initialvalue=0) Control for Rx Switch 9 LO path. The configuration of this switch changes between RX paths. FOR RX0: Write 0 to select Rx internal LO path Write 1 to select Rx external LO path FOR RX1: Write 0 to select Rx external LO path Write 1 to select Rx internal LO path
15 | Reserved
14 | RX_SWITCH_7_8 (initialvalue=0) Shared control for Rx switch 7 and switch 8. FOR RX0: Write 0 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz Write 1 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz FOR RX1: Write 0 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz Write 1 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz
13..12 | RX_SWITCH_6 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Rx Switch 6. The configuration of this switch changes between RX paths. FOR RX0: Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path FOR RX1: Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path
11..10 | RX_SWITCH_5 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Rx Switch 5. The configuration of this switch changes between RX paths. FOR RX0: Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path FOR RX1: Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, RX_SWITCH_6 must also select this path Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, RX_SWITCH_6 must also select this path Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, RX_SWITCH_6 must also select this path Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, RX_SWITCH_6 must also select this path
9 | Reserved
8 | RX_SWITCH_4 (initialvalue=0) note to digital designer: control A is the only control, and control B is tied to ground Control for Rx Switch 4. Write 0 to select Rx RF1/2 lowband path Write 1 to select Rx RF3 highband path
7 | Reserved
6..4 | RX_SWITCH_3 (initialvalue=0) Control for Rx Switch 3, note this is one hot encoding and not binary. The configuration of this switch changes between RX paths. FOR RX0: Write 1 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz Write 4 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz FOR RX1: Write 1 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz Write 4 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz *All other values are invalid
3 | Reserved
2 | RX_SWITCH_2 (initialvalue=0) note to digital designer: control A is the only control, and control B is pulled high Control for Rx Switch 2. The configuration of this switch changes between RX paths. FOR RX0: Write 0 to select Rx RF3 highband path Write 1 to select Rx RF1/2 lowband path FOR RX1: Write 0 to select Rx RF1/2 lowband path Write 1 to select Rx RF3 highband path
1..0 | RX_SWITCH_1 (initialvalue=0) note to digital designer: control A is LSB, and control B is MSB Control for Rx Switch 1. The configuration of this switch changes between RX paths. FOR RX0: Write 0 to select Rx calibration loopback Write 1 to select Rx 50 ohm termination path Write 2 to select Tx Rx path, TX_SWITCH_11 must also select the correct path Write 3 to select Rx input port FOR RX1: Write 0 to select Rx calibration loopback Write 1 to select Tx Rx path, TX_SWITCH_11 must also select the correct path Write 2 to select Rx input port Write 3 to select Rx 50 ohm termination path