0. old reports waiting for ACK =============================================

1. 1.0.2 ===============================================================

2. 1.0.3 ==================================================================
- BUG: the autobuild system doesn't run tests?
- CLEANUP/BUG: connect attribute works only on existing ports {des2:55} [report: Majenko]
	- consider making it create ports
		- don't return -1 in std_cschem.c:157 because a second connection in the array is not processed then
	- or if not:
		- remove std_cschem.c:150 because it creates the port
	- also related to TODO#rgc below
		- we shouldn't get errors on bug_files/TODO/rgc1.rs - power rail symbols should probably request the error using an attribute explicitly
- FEATURE: BoM template language: concat'd lists:
		- use case: v1.1 should have color and tolerance in the value
		- allow creating new attributes (or rather macros) using the same template
		- create one with: %escape.sym.a.color|% %escape.sym.a.value|% %escape.sym.a.tolerance|%
		- print it as %escape.macro|(unknown)% for the value column
- FEATURE: implement attribute symlinks (see design doc)
	- BUG: altium had a =Device or =Footprint attribute somewhere, that should be a symlink [report: aron]
- FEATURE: symbol meta layer drawing: draw lines from floaters back to their parent?
- FEATURE: action binding for rtree searches (in pcb-rnd too?) [report: Majenko]
- FEATURE: tooltip on toolbar icons should also show the hotkey (librnd?) [report: rudolfii]
- FEATURE: "require graphical connection" attribute for gnd and vcc and rail, see TODO#rgc
- FEATURE: the integrity check shall verify rtree vs. data tree, that every object is in the rtree and rtree has no ghost objects [report: clarity]
- FEATURE: integrity check messages should contain the name/path of the sheet causing the problem [report: aron]
- FEATURE: io_geda: multiple net= attributes (e.g. in stock 7400) -> should be an array
- FEATURE: attribute edit dialog, abstract side: floater button to create a floater text based on an abstract attribute [report: aron]
- BUG: csch_grp_ref_embed(), used in sym loclib paste and right click symbol context menu toref (to loclib) conversion is not undoable [report: Igor2]
- BUG: boxsym-rnd: edakrill r1159: labels overlap [report: Igor2]
- BUG: polygon fill change not visible: bug_files/TODO/no_fill.* [report: Majenko]

3. NLnet ==========================================================
- hierarchic design [3]:
	- figure how to handle aux sheets from library (prefix?)
	- more generally: how to handle files from a different directory
		- BUG: bug_files/TODO/unl; sch-rnd project.lht; file/project/new unlisted; file name "/tmp/new.rs"; new sheet goes into a new, unnamed project [report: aron]
	- doc/usr/07_io/export_spice/pinout.html: look for TODO, verify
- extensions:
	- high level sim:
		- sim-to-spice compilation:
			- autodetect net type from pin types
			- auto-bridge as needed for mixed mode digital+analog
			- DOC: port type attributes (e.g. analog, ttl), also consider DRC, check coraleda std 2
			- lib_sim: elect network type (default is analog)
			- API? set port attributes for bridges where needed
		- BUG: stance is set temporarily using sch_sim_set_test_bench() for the compilation only but csch_stance_set() prints the permanent setting
		- BUG: womit_no_test_bench is not really implemented, see TODO#womit

4. Later releases ==========================================================
- a connection object should have x;y displacement for the graphical object to be useful (or is it a grp_ref?); at the moment we are not drawing it at all
- FEATURE: consider multiline text objects (nlnet ext?)
- FEATURE: allow svg schematic export with option of monochrome [report: Erich]
- FEATURE: DRC (requires query() on the abstract model):
	- noslot attribute (e.g. for resistors)
	- figure if fully overlapping ports (or symbols) can be or should be detected (see: two gnd symbols on top of eachother) [report: Erich]
	- it is easy to accidentally add a footprint to a terminal on a symbol instead of the symbol itself. This is not flagged on netlist export. Should it be harder to do this, or maybe a netlist exporter could indicate if footprints associated with terminals in symbols were not included in the export? [report: Erich]
	- accidentally adding a name to a rail exports a connection in the netlist with no associated component. Perhaps this would benefit from some sort of DRC check, like the "footprint attribute put on non-symbol" issue above. [report: Erich]
	- component pcb pinnum: check if pins are numbered from 1 (or 0) without discontinuities; could catch typos in footprint creation (example: Aron's orange pi zero usb pins on edakrill) [report: aron]
- FEATURE: text vertical alignment (in design doc and code); same rules as in halign [report: Ade]
- FEATURE: export of the schematic as a pcb-rnd/tedax subcircuit/footprint for placement on the PCB as a graphical element? For simpler circuits, this would be good for "documentation on the silk layer". [report: Erich]
- BUG: copy&paste wirenet line extension merge, see TODO#merge31 in the code [report: Igor2]
- needs librnd4.1 API upgrade:
	- library window "Use selected" should have a tooltip on what exactly it does (for devmap: returns name only, does not update loclib); API: close buttons can't have tooltips [report: aron]

5. Low prio ==========================================================
- FEATURE: check feasability: use non-graphical fawk sheet as calculator
	- e.g. voltage divider of R1 and R2 with input and output voltages specified, fawk calculates value for R1 and R2
	- how to query attributes of existing things?
	- how to guarantee the data sheet is compiled after the graphical sheets?
	-> probably better to have this in a "target script"
- BUG: enable multiport_net_merge, then bug_files/multiconn0.rs; move TP2 1k or 2k to the left; more than one connection is created because the vertical ports are overlapping and when the horizontal port is connected, but it figures connections only one by one so it doesn't dare to extend existing connections [report: Igor2]
- BUG: {e t} over a non-dyntext, resize window larger: entry remains small [report: aron]
- FEATURE: view window: open once, single perview widget, copy current zoom+pan, close when parent sheet closed; consider the same for pcb-rnd and camv-rnd [report: Vuokko]
- FEATURE: consider dangling wire end indication (see pool node)
- FEATURE: support for protel format? (.asc, differerent syntax and data model from io_altium) [report: Scott]
- TODO#38: rethink grp-ref-in-grp-ref with child xforms, maybe cache=1 is a bad idea
	- problem: ref1 -> ref2 -> grp -> text; ref2 is floater; if whole ref2 is rotated, we won't update anything in ref1's central xform list
- BUG: wirenet in group should work: load symnet.rs. select terminal and adjacent vertical line using negative selection box; convert selection to symbol. connect test point 1 to wire net. export netlist. do not assume wirenet is directly under the &direct in the tree [report: Erich]
- BUG: back annotation: abstract model: abstract model UUIDs are not implemented, annotation doesn't use them; either figure persistent uuids or use CMRs [report: Igor2]
- BUG: rewrite get_prjname() in dytext render
	- figure the path of the project file
	- project name change runtime (save-as); inalidate text objects (->rtext = NULL using csch_text_dyntext_inval()) to re-render the new name
- OPTIMIZE: do not re-create views multiple times in sch_rnd_prj_conf2prj(): start 'sch-rnd A.rs B.rs' from the same dir [report: Igor2]
- CLEANUP: code dups with pcb-rnd, consider moving some code to src_3rd/rnd_inclib:
	- query
	- propedit
	- undodialog
	- rename csch_ symbols to sch_rnd_ in plugins/
	- act_read
- librnd4.0.0:
	- remove the whole project loading plug io: project files will be handled by librnd
	- once multi is moved over:
		- extend oidpath to generate and accept sheet prefix with $uuid/
		- act_draw should be able to use it as scope
		- act_draw should be able to return oidpath with $uuid/
		- query() should be able to return/convert lists like that for scripting

6. TODO() tags ==========================================================
	- symedit:    needed for symbol editor support
	- bitmap:     needed for bitmap objects
	- fungw:      may need fungw API change
	- multi:      multiple sheet support
	- hierarchic: needed for hierarchic projects
