/*
 * SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2024 Napatech A/S
 */

/*
 * nthw_fpga_mod_defs.h
 *
 * Auto-generated file - do *NOT* edit
 *
 */

#ifndef _NTHW_FPGA_MOD_DEFS_H_
#define _NTHW_FPGA_MOD_DEFS_H_

#define MOD_UNKNOWN (0L)/* Unknown/uninitialized - keep this as the first element */
#define MOD_CAT (0x30b447c2UL)
#define MOD_CPY (0x1ddc186fUL)
#define MOD_CSU (0x3f470787UL)
#define MOD_DBS (0x80b29727UL)
#define MOD_FLM (0xe7ba53a4UL)
#define MOD_GFG (0xfc423807UL)
#define MOD_GMF (0x68b1d15aUL)
#define MOD_GPIO_PHY (0xbbe81659UL)
#define MOD_HFU (0x4a70e72UL)
#define MOD_HIF (0x7815363UL)
#define MOD_HSH (0x501484bfUL)
#define MOD_I2CM (0x93bc7780UL)
#define MOD_IFR (0x9b01f1e6UL)
#define MOD_IIC (0x7629cddbUL)
#define MOD_INS (0x24df4b78UL)
#define MOD_KM (0xcfbd9dbeUL)
#define MOD_MAC_PCS (0x7abe24c7UL)
#define MOD_MAC_RX (0x6347b490UL)
#define MOD_MAC_TX (0x351d1316UL)
#define MOD_PCIE3 (0xfbc48c18UL)
#define MOD_PCI_RD_TG (0x9ad9eed2UL)
#define MOD_PCI_WR_TG (0x274b69e1UL)
#define MOD_PDB (0xa7771bffUL)
#define MOD_QSL (0x448ed859UL)
#define MOD_RAC (0xae830b42UL)
#define MOD_RMC (0x236444eUL)
#define MOD_RPL (0x6de535c3UL)
#define MOD_RPF (0x8d30dcddUL)
#define MOD_RPP_LR (0xba7f945cUL)
#define MOD_RST9563 (0x385d6d1dUL)
#define MOD_SDC (0xd2369530UL)
#define MOD_SLC (0x1aef1f38UL)
#define MOD_SLC_LR (0x969fc50bUL)
#define MOD_STA (0x76fae64dUL)
#define MOD_TSM (0x35422a24UL)
#define MOD_TX_CPY (0x60acf217UL)
#define MOD_TX_INS (0x59afa100UL)
#define MOD_TX_RPL (0x1095dfbbUL)
#define MOD_IDX_COUNT (36)

/* aliases - only aliases go below this point */
#endif	/* _NTHW_FPGA_MOD_DEFS_H_ */
