/*
 * SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2024 Napatech A/S
 */

#ifndef _NTHW_FPGA_REG_DEFS_TSM_
#define _NTHW_FPGA_REG_DEFS_TSM_

/* TSM */
#define TSM_CON0_CONFIG (0xf893d371UL)
#define TSM_CON0_CONFIG_BLIND (0x59ccfcbUL)
#define TSM_CON0_CONFIG_DC_SRC (0x1879812bUL)
#define TSM_CON0_CONFIG_PORT (0x3ff0bb08UL)
#define TSM_CON0_CONFIG_PPSIN_2_5V (0xb8e78227UL)
#define TSM_CON0_CONFIG_SAMPLE_EDGE (0x4a4022ebUL)
#define TSM_CON0_INTERFACE (0x76e93b59UL)
#define TSM_CON0_INTERFACE_EX_TERM (0xd079b416UL)
#define TSM_CON0_INTERFACE_IN_REF_PWM (0x16f73c33UL)
#define TSM_CON0_INTERFACE_PWM_ENA (0x3629e73fUL)
#define TSM_CON0_INTERFACE_RESERVED (0xf9c5066UL)
#define TSM_CON0_INTERFACE_VTERM_PWM (0x6d2b1e23UL)
#define TSM_CON0_SAMPLE_HI (0x6e536b8UL)
#define TSM_CON0_SAMPLE_HI_SEC (0x5fc26159UL)
#define TSM_CON0_SAMPLE_LO (0x8bea5689UL)
#define TSM_CON0_SAMPLE_LO_NS (0x13d0010dUL)
#define TSM_CON1_CONFIG (0x3439d3efUL)
#define TSM_CON1_CONFIG_BLIND (0x98932ebdUL)
#define TSM_CON1_CONFIG_DC_SRC (0xa1825ac3UL)
#define TSM_CON1_CONFIG_PORT (0xe266628dUL)
#define TSM_CON1_CONFIG_PPSIN_2_5V (0x6f05027fUL)
#define TSM_CON1_CONFIG_SAMPLE_EDGE (0x2f2719adUL)
#define TSM_CON1_SAMPLE_HI (0xc76be978UL)
#define TSM_CON1_SAMPLE_HI_SEC (0xe639bab1UL)
#define TSM_CON1_SAMPLE_LO (0x4a648949UL)
#define TSM_CON1_SAMPLE_LO_NS (0x8edfe07bUL)
#define TSM_CON2_CONFIG (0xbab6d40cUL)
#define TSM_CON2_CONFIG_BLIND (0xe4f20b66UL)
#define TSM_CON2_CONFIG_DC_SRC (0xb0ff30baUL)
#define TSM_CON2_CONFIG_PORT (0x5fac0e43UL)
#define TSM_CON2_CONFIG_PPSIN_2_5V (0xcc5384d6UL)
#define TSM_CON2_CONFIG_SAMPLE_EDGE (0x808e5467UL)
#define TSM_CON2_SAMPLE_HI (0x5e898f79UL)
#define TSM_CON2_SAMPLE_HI_SEC (0xf744d0c8UL)
#define TSM_CON2_SAMPLE_LO (0xd386ef48UL)
#define TSM_CON2_SAMPLE_LO_NS (0xf2bec5a0UL)
#define TSM_CON3_CONFIG (0x761cd492UL)
#define TSM_CON3_CONFIG_BLIND (0x79fdea10UL)
#define TSM_CON3_CONFIG_PORT (0x823ad7c6UL)
#define TSM_CON3_CONFIG_SAMPLE_EDGE (0xe5e96f21UL)
#define TSM_CON3_SAMPLE_HI (0x9f0750b9UL)
#define TSM_CON3_SAMPLE_HI_SEC (0x4ebf0b20UL)
#define TSM_CON3_SAMPLE_LO (0x12083088UL)
#define TSM_CON3_SAMPLE_LO_NS (0x6fb124d6UL)
#define TSM_CON4_CONFIG (0x7cd9dd8bUL)
#define TSM_CON4_CONFIG_BLIND (0x1c3040d0UL)
#define TSM_CON4_CONFIG_PORT (0xff49d19eUL)
#define TSM_CON4_CONFIG_SAMPLE_EDGE (0x4adc9b2UL)
#define TSM_CON4_SAMPLE_HI (0xb63c453aUL)
#define TSM_CON4_SAMPLE_HI_SEC (0xd5be043aUL)
#define TSM_CON4_SAMPLE_LO (0x3b33250bUL)
#define TSM_CON4_SAMPLE_LO_NS (0xa7c8e16UL)
#define TSM_CON5_CONFIG (0xb073dd15UL)
#define TSM_CON5_CONFIG_BLIND (0x813fa1a6UL)
#define TSM_CON5_CONFIG_PORT (0x22df081bUL)
#define TSM_CON5_CONFIG_SAMPLE_EDGE (0x61caf2f4UL)
#define TSM_CON5_SAMPLE_HI (0x77b29afaUL)
#define TSM_CON5_SAMPLE_HI_SEC (0x6c45dfd2UL)
#define TSM_CON5_SAMPLE_LO (0xfabdfacbUL)
#define TSM_CON5_SAMPLE_LO_TIME (0x945d87e8UL)
#define TSM_CON6_CONFIG (0x3efcdaf6UL)
#define TSM_CON6_CONFIG_BLIND (0xfd5e847dUL)
#define TSM_CON6_CONFIG_PORT (0x9f1564d5UL)
#define TSM_CON6_CONFIG_SAMPLE_EDGE (0xce63bf3eUL)
#define TSM_CON6_SAMPLE_HI (0xee50fcfbUL)
#define TSM_CON6_SAMPLE_HI_SEC (0x7d38b5abUL)
#define TSM_CON6_SAMPLE_LO (0x635f9ccaUL)
#define TSM_CON6_SAMPLE_LO_NS (0xeb124abbUL)
#define TSM_CON7_HOST_SAMPLE_HI (0xdcd90e52UL)
#define TSM_CON7_HOST_SAMPLE_HI_SEC (0xd98d3618UL)
#define TSM_CON7_HOST_SAMPLE_LO (0x51d66e63UL)
#define TSM_CON7_HOST_SAMPLE_LO_NS (0x8f5594ddUL)
#define TSM_CONFIG (0xef5dec83UL)
#define TSM_CONFIG_NTTS_SRC (0x1b60227bUL)
#define TSM_CONFIG_NTTS_SYNC (0x43e0a69dUL)
#define TSM_CONFIG_TIMESET_EDGE (0x8c381127UL)
#define TSM_CONFIG_TIMESET_SRC (0xe7590a31UL)
#define TSM_CONFIG_TIMESET_UP (0x561980c1UL)
#define TSM_CONFIG_TS_FORMAT (0xe6efc2faUL)
#define TSM_INT_CONFIG (0x9a0d52dUL)
#define TSM_INT_CONFIG_AUTO_DISABLE (0x9581470UL)
#define TSM_INT_CONFIG_MASK (0xf00cd3d7UL)
#define TSM_INT_STAT (0xa4611a70UL)
#define TSM_INT_STAT_CAUSE (0x315168cfUL)
#define TSM_INT_STAT_ENABLE (0x980a12d1UL)
#define TSM_LED (0x6ae05f87UL)
#define TSM_LED_LED0_BG_COLOR (0x897cf9eeUL)
#define TSM_LED_LED0_COLOR (0x6d7ada39UL)
#define TSM_LED_LED0_MODE (0x6087b644UL)
#define TSM_LED_LED0_SRC (0x4fe29639UL)
#define TSM_LED_LED1_BG_COLOR (0x66be92d0UL)
#define TSM_LED_LED1_COLOR (0xcb0dd18dUL)
#define TSM_LED_LED1_MODE (0xabdb65e1UL)
#define TSM_LED_LED1_SRC (0x7282bf89UL)
#define TSM_LED_LED2_BG_COLOR (0x8d8929d3UL)
#define TSM_LED_LED2_COLOR (0xfae5cb10UL)
#define TSM_LED_LED2_MODE (0x2d4f174fUL)
#define TSM_LED_LED2_SRC (0x3522c559UL)
#define TSM_NTTS_CONFIG (0x8bc38bdeUL)
#define TSM_NTTS_CONFIG_AUTO_HARDSET (0xd75be25dUL)
#define TSM_NTTS_CONFIG_EXT_CLK_ADJ (0x700425b6UL)
#define TSM_NTTS_CONFIG_HIGH_SAMPLE (0x37135b7eUL)
#define TSM_NTTS_CONFIG_TS_SRC_FORMAT (0x6e6e707UL)
#define TSM_NTTS_EXT_STAT (0x2b0315b7UL)
#define TSM_NTTS_EXT_STAT_MASTER_ID (0xf263315eUL)
#define TSM_NTTS_EXT_STAT_MASTER_REV (0xd543795eUL)
#define TSM_NTTS_EXT_STAT_MASTER_STAT (0x92d96f5eUL)
#define TSM_NTTS_LIMIT_HI (0x1ddaa85fUL)
#define TSM_NTTS_LIMIT_HI_SEC (0x315c6ef2UL)
#define TSM_NTTS_LIMIT_LO (0x90d5c86eUL)
#define TSM_NTTS_LIMIT_LO_NS (0xe6d94d9aUL)
#define TSM_NTTS_OFFSET (0x6436e72UL)
#define TSM_NTTS_OFFSET_NS (0x12d43a06UL)
#define TSM_NTTS_SAMPLE_HI (0xcdc8aa3eUL)
#define TSM_NTTS_SAMPLE_HI_SEC (0x4f6588fdUL)
#define TSM_NTTS_SAMPLE_LO (0x40c7ca0fUL)
#define TSM_NTTS_SAMPLE_LO_NS (0x6e43ff97UL)
#define TSM_NTTS_STAT (0x6502b820UL)
#define TSM_NTTS_STAT_NTTS_VALID (0x3e184471UL)
#define TSM_NTTS_STAT_SIGNAL_LOST (0x178bedfdUL)
#define TSM_NTTS_STAT_SYNC_LOST (0xe4cd53dfUL)
#define TSM_NTTS_TS_T0_HI (0x1300d1b6UL)
#define TSM_NTTS_TS_T0_HI_TIME (0xa016ae4fUL)
#define TSM_NTTS_TS_T0_LO (0x9e0fb187UL)
#define TSM_NTTS_TS_T0_LO_TIME (0x82006941UL)
#define TSM_NTTS_TS_T0_OFFSET (0xbf70ce4fUL)
#define TSM_NTTS_TS_T0_OFFSET_COUNT (0x35dd4398UL)
#define TSM_PB_CTRL (0x7a8b60faUL)
#define TSM_PB_CTRL_INSTMEM_WR (0xf96e2cbcUL)
#define TSM_PB_CTRL_RESET (0xa38ade8bUL)
#define TSM_PB_CTRL_RST (0x3aaa82f4UL)
#define TSM_PB_INSTMEM (0xb54aeecUL)
#define TSM_PB_INSTMEM_MEM_ADDR (0x9ac79b6eUL)
#define TSM_PB_INSTMEM_MEM_DATA (0x65aefa38UL)
#define TSM_PI_CTRL_I (0x8d71a4e2UL)
#define TSM_PI_CTRL_I_VAL (0x98baedc9UL)
#define TSM_PI_CTRL_KI (0xa1bd86cbUL)
#define TSM_PI_CTRL_KI_GAIN (0x53faa916UL)
#define TSM_PI_CTRL_KP (0xc5d62e0bUL)
#define TSM_PI_CTRL_KP_GAIN (0x7723fa45UL)
#define TSM_PI_CTRL_SHL (0xaa518701UL)
#define TSM_PI_CTRL_SHL_VAL (0x56f56a6fUL)
#define TSM_STAT (0xa55bf677UL)
#define TSM_STAT_HARD_SYNC (0x7fff20fdUL)
#define TSM_STAT_LINK_CON0 (0x216086f0UL)
#define TSM_STAT_LINK_CON1 (0x5667b666UL)
#define TSM_STAT_LINK_CON2 (0xcf6ee7dcUL)
#define TSM_STAT_LINK_CON3 (0xb869d74aUL)
#define TSM_STAT_LINK_CON4 (0x260d42e9UL)
#define TSM_STAT_LINK_CON5 (0x510a727fUL)
#define TSM_STAT_NTTS_INSYNC (0xb593a245UL)
#define TSM_STAT_PTP_MI_PRESENT (0x43131eb0UL)
#define TSM_TIMER_CTRL (0x648da051UL)
#define TSM_TIMER_CTRL_TIMER_EN_T0 (0x17cee154UL)
#define TSM_TIMER_CTRL_TIMER_EN_T1 (0x60c9d1c2UL)
#define TSM_TIMER_T0 (0x417217a5UL)
#define TSM_TIMER_T0_MAX_COUNT (0xaa601706UL)
#define TSM_TIMER_T1 (0x36752733UL)
#define TSM_TIMER_T1_MAX_COUNT (0x6beec8c6UL)
#define TSM_TIME_HARDSET_HI (0xf28bdb46UL)
#define TSM_TIME_HARDSET_HI_TIME (0x2d9a28baUL)
#define TSM_TIME_HARDSET_LO (0x7f84bb77UL)
#define TSM_TIME_HARDSET_LO_TIME (0xf8cefb4UL)
#define TSM_TIME_HI (0x175acea1UL)
#define TSM_TIME_HI_SEC (0xc0e9c9a1UL)
#define TSM_TIME_LO (0x9a55ae90UL)
#define TSM_TIME_LO_NS (0x879c5c4bUL)
#define TSM_TIME_RATE_ADJ (0xb1cc4bb1UL)
#define TSM_TIME_RATE_ADJ_FRACTION (0xb7ab96UL)
#define TSM_TS_HI (0xccfe9e5eUL)
#define TSM_TS_HI_TIME (0xc23fed30UL)
#define TSM_TS_LO (0x41f1fe6fUL)
#define TSM_TS_LO_TIME (0xe0292a3eUL)
#define TSM_TS_OFFSET (0x4b2e6e13UL)
#define TSM_TS_OFFSET_NS (0x68c286b9UL)
#define TSM_TS_STAT (0x64d41b8cUL)
#define TSM_TS_STAT_OVERRUN (0xad9db92aUL)
#define TSM_TS_STAT_SAMPLES (0xb6350e0bUL)
#define TSM_TS_STAT_HI_OFFSET (0x1aa2ddf2UL)
#define TSM_TS_STAT_HI_OFFSET_NS (0xeb040e0fUL)
#define TSM_TS_STAT_LO_OFFSET (0x81218579UL)
#define TSM_TS_STAT_LO_OFFSET_NS (0xb7ff33UL)
#define TSM_TS_STAT_TAR_HI (0x65af24b6UL)
#define TSM_TS_STAT_TAR_HI_SEC (0x7e92f619UL)
#define TSM_TS_STAT_TAR_LO (0xe8a04487UL)
#define TSM_TS_STAT_TAR_LO_NS (0xf7b3f439UL)
#define TSM_TS_STAT_X (0x419f0ddUL)
#define TSM_TS_STAT_X_NS (0xa48c3f27UL)
#define TSM_TS_STAT_X2_HI (0xd6b1c517UL)
#define TSM_TS_STAT_X2_HI_NS (0x4288c50fUL)
#define TSM_TS_STAT_X2_LO (0x5bbea526UL)
#define TSM_TS_STAT_X2_LO_NS (0x92633c13UL)
#define TSM_UTC_OFFSET (0xf622a13aUL)
#define TSM_UTC_OFFSET_SEC (0xd9c80209UL)

#endif	/* _NTHW_FPGA_REG_DEFS_TSM_ */
