// This file is automatically generated by rmconfig - DO NOT EDIT!
//
// Private HAL support for RPC.
//
// Profile:  shipping-gpus-openrm
// Haldef:   rpc.def
// Template: templates/gt_eng_private.h
//

#ifndef _G_RPC_PRIVATE_H_
#define _G_RPC_PRIVATE_H_

#include "g_rpc_hal.h"


                                               // RPC:VGPU_PF_REG_READ32
RpcVgpuPfRegRead32                 rpcVgpuPfRegRead32_v15_00;
RpcVgpuPfRegRead32                 rpcVgpuPfRegRead32_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:DUMP_PROTOBUF_COMPONENT
RpcDumpProtobufComponent           rpcDumpProtobufComponent_v18_12;
RpcDumpProtobufComponent           rpcDumpProtobufComponent_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:ALLOC_MEMORY
RpcAllocMemory                     rpcAllocMemory_v13_01;
RpcAllocMemory                     rpcAllocMemory_STUB;      // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:GPU_EXEC_REG_OPS
RpcGpuExecRegOps                   rpcGpuExecRegOps_v12_01;
RpcGpuExecRegOps                   rpcGpuExecRegOps_STUB;    // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:RMFS_INIT
RpcRmfsInit                        rpcRmfsInit_v15_00;
RpcRmfsInit                        rpcRmfsInit_STUB;         // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:UNSET_PAGE_DIRECTORY
RpcUnsetPageDirectory              rpcUnsetPageDirectory_v03_00;
RpcUnsetPageDirectory              rpcUnsetPageDirectory_v1E_05;
RpcUnsetPageDirectory              rpcUnsetPageDirectory_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:GET_GSP_STATIC_INFO
RpcGetGspStaticInfo                rpcGetGspStaticInfo_v14_00;
RpcGetGspStaticInfo                rpcGetGspStaticInfo_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:GSP_SET_SYSTEM_INFO
RpcGspSetSystemInfo                rpcGspSetSystemInfo_v17_00;
RpcGspSetSystemInfo                rpcGspSetSystemInfo_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:RMFS_CLEANUP
RpcRmfsCleanup                     rpcRmfsCleanup_v15_00;
RpcRmfsCleanup                     rpcRmfsCleanup_STUB;      // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:SET_PAGE_DIRECTORY
RpcSetPageDirectory                rpcSetPageDirectory_v03_00;
RpcSetPageDirectory                rpcSetPageDirectory_v1E_05;
RpcSetPageDirectory                rpcSetPageDirectory_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:UNLOADING_GUEST_DRIVER
RpcUnloadingGuestDriver            rpcUnloadingGuestDriver_v03_00;
RpcUnloadingGuestDriver            rpcUnloadingGuestDriver_v1F_07;
RpcUnloadingGuestDriver            rpcUnloadingGuestDriver_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:SET_REGISTRY
RpcSetRegistry                     rpcSetRegistry_v17_00;
RpcSetRegistry                     rpcSetRegistry_STUB;      // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:RMFS_CLOSE_QUEUE
RpcRmfsCloseQueue                  rpcRmfsCloseQueue_v15_00;
RpcRmfsCloseQueue                  rpcRmfsCloseQueue_STUB;   // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:GET_STATIC_INFO
RpcGetStaticInfo                   rpcGetStaticInfo_v17_05;
RpcGetStaticInfo                   rpcGetStaticInfo_v18_03;
RpcGetStaticInfo                   rpcGetStaticInfo_v18_04;
RpcGetStaticInfo                   rpcGetStaticInfo_v18_0E;
RpcGetStaticInfo                   rpcGetStaticInfo_v18_10;
RpcGetStaticInfo                   rpcGetStaticInfo_v18_11;
RpcGetStaticInfo                   rpcGetStaticInfo_v18_13;
RpcGetStaticInfo                   rpcGetStaticInfo_v18_16;
RpcGetStaticInfo                   rpcGetStaticInfo_v19_00;
RpcGetStaticInfo                   rpcGetStaticInfo_v1A_00;
RpcGetStaticInfo                   rpcGetStaticInfo_v1A_05;
RpcGetStaticInfo                   rpcGetStaticInfo_v20_01;
RpcGetStaticInfo                   rpcGetStaticInfo_STUB;    // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:IDLE_CHANNELS
RpcIdleChannels                    rpcIdleChannels_v03_00;
RpcIdleChannels                    rpcIdleChannels_STUB;     // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:UPDATE_BAR_PDE
RpcUpdateBarPde                    rpcUpdateBarPde_v15_00;
RpcUpdateBarPde                    rpcUpdateBarPde_STUB;     // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:MAP_MEMORY_DMA
RpcMapMemoryDma                    rpcMapMemoryDma_v03_00;
RpcMapMemoryDma                    rpcMapMemoryDma_STUB;     // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:UNMAP_MEMORY_DMA
RpcUnmapMemoryDma                  rpcUnmapMemoryDma_v03_00;
RpcUnmapMemoryDma                  rpcUnmapMemoryDma_STUB;   // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X

                                               // RPC:RMFS_TEST
RpcRmfsTest                        rpcRmfsTest_v15_00;
RpcRmfsTest                        rpcRmfsTest_STUB;         // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X






//
// RPC's object-level *non-static* interface functions (static ones are below)
//
RpcConstruct                       rpcConstruct_IMPL;
RpcDestroy                         rpcDestroy_IMPL;
RpcSendMessage                     rpcSendMessage_IMPL;
RpcRecvPoll                        rpcRecvPoll_IMPL;



#if defined(RMCFG_ENGINE_SETUP)    // for use by hal init only





// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v03_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v04_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v05_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v06_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v07_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v07_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v08_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v09_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v09_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v09_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v12_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v13_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v14_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v14_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v14_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v15_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v15_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v17_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v17_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v17_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_0F(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_10(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_11(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_12(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_13(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_14(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_15(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v18_16(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v19_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v19_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_0F(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_10(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_12(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_13(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_14(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_15(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_16(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_17(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_18(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_1A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_1B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_1C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_1D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_1E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_1F(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_20(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_21(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_22(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_23(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1A_24(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1B_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1B_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1C_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1C_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1C_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1C_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1C_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1C_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1C_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1C_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1C_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1D_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1D_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1D_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1E_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1E_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1E_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1E_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1E_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1E_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1E_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1E_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1E_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1E_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1E_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1F_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1F_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1F_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1F_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1F_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1F_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1F_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1F_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1F_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1F_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1F_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v1F_0F(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v20_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v20_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v20_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v20_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v21_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v21_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v21_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v21_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v21_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v21_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v21_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v21_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v21_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpc_iGrp_ipVersions_Install_v21_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcHal += 0;


#endif // 
}




// the "_UNASSIGNED" function for all IP_VERSIONS dynamic interfaces
NV_STATUS iGrp_ipVersions_UNASSIGNED(void);


static NV_STATUS rpc_iGrp_ipVersions_Wrapup(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
    OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic;
    RPC_HAL_IFACES *pRpcHal = &pRpc->_hal;

    // avoid possible unused warnings
    pRpcHal += 0;

    // fixup per-interface overrides?
    if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF))
       pRpcHal->rpcVgpuPfRegRead32 = rpcVgpuPfRegRead32_v15_00;
    if (IsIPVersionInRange(pRpc, 0x18120000, 0xFFFFFFFF))
       pRpcHal->rpcDumpProtobufComponent = rpcDumpProtobufComponent_v18_12;
    if (IsIPVersionInRange(pRpc, 0x13010000, 0xFFFFFFFF))
       pRpcHal->rpcAllocMemory = rpcAllocMemory_v13_01;
    if (IsIPVersionInRange(pRpc, 0x12010000, 0xFFFFFFFF))
       pRpcHal->rpcGpuExecRegOps = rpcGpuExecRegOps_v12_01;
    if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF))
       pRpcHal->rpcRmfsInit = rpcRmfsInit_v15_00;
    if (IsIPVersionInRange(pRpc, 0x03000000, 0x1E04FFFF))
       pRpcHal->rpcUnsetPageDirectory = rpcUnsetPageDirectory_v03_00;
    if (IsIPVersionInRange(pRpc, 0x1E050000, 0xFFFFFFFF))
       pRpcHal->rpcUnsetPageDirectory = rpcUnsetPageDirectory_v1E_05;
    if (IsIPVersionInRange(pRpc, 0x14000000, 0xFFFFFFFF))
       pRpcHal->rpcGetGspStaticInfo = rpcGetGspStaticInfo_v14_00;
    if (IsIPVersionInRange(pRpc, 0x17000000, 0xFFFFFFFF))
       pRpcHal->rpcGspSetSystemInfo = rpcGspSetSystemInfo_v17_00;
    if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF))
       pRpcHal->rpcRmfsCleanup = rpcRmfsCleanup_v15_00;
    if (IsIPVersionInRange(pRpc, 0x03000000, 0x1E04FFFF))
       pRpcHal->rpcSetPageDirectory = rpcSetPageDirectory_v03_00;
    if (IsIPVersionInRange(pRpc, 0x1E050000, 0xFFFFFFFF))
       pRpcHal->rpcSetPageDirectory = rpcSetPageDirectory_v1E_05;
    if (IsIPVersionInRange(pRpc, 0x03000000, 0x1F06FFFF))
       pRpcHal->rpcUnloadingGuestDriver = rpcUnloadingGuestDriver_v03_00;
    if (IsIPVersionInRange(pRpc, 0x1F070000, 0xFFFFFFFF))
       pRpcHal->rpcUnloadingGuestDriver = rpcUnloadingGuestDriver_v1F_07;
    if (IsIPVersionInRange(pRpc, 0x17000000, 0xFFFFFFFF))
       pRpcHal->rpcSetRegistry = rpcSetRegistry_v17_00;
    if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF))
       pRpcHal->rpcRmfsCloseQueue = rpcRmfsCloseQueue_v15_00;
    if (IsIPVersionInRange(pRpc, 0x17050000, 0x1802FFFF))
       pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v17_05;
    if (IsIPVersionInRange(pRpc, 0x18030000, 0x1803FFFF))
       pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_03;
    if (IsIPVersionInRange(pRpc, 0x18040000, 0x180DFFFF))
       pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_04;
    if (IsIPVersionInRange(pRpc, 0x180E0000, 0x180FFFFF))
       pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_0E;
    if (IsIPVersionInRange(pRpc, 0x18100000, 0x1810FFFF))
       pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_10;
    if (IsIPVersionInRange(pRpc, 0x18110000, 0x1812FFFF))
       pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_11;
    if (IsIPVersionInRange(pRpc, 0x18130000, 0x1815FFFF))
       pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_13;
    if (IsIPVersionInRange(pRpc, 0x18160000, 0x18FFFFFF))
       pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_16;
    if (IsIPVersionInRange(pRpc, 0x19000000, 0x19FFFFFF))
       pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v19_00;
    if (IsIPVersionInRange(pRpc, 0x1A000000, 0x1A04FFFF))
       pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v1A_00;
    if (IsIPVersionInRange(pRpc, 0x1A050000, 0x2000FFFF))
       pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v1A_05;
    if (IsIPVersionInRange(pRpc, 0x20010000, 0xFFFFFFFF))
       pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v20_01;
    if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF))
       pRpcHal->rpcIdleChannels = rpcIdleChannels_v03_00;
    if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF))
       pRpcHal->rpcUpdateBarPde = rpcUpdateBarPde_v15_00;
    if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF))
       pRpcHal->rpcMapMemoryDma = rpcMapMemoryDma_v03_00;
    if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF))
       pRpcHal->rpcUnmapMemoryDma = rpcUnmapMemoryDma_v03_00;
    if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF))
       pRpcHal->rpcRmfsTest = rpcRmfsTest_v15_00;

    // Verify each 'dynamically set' interface was actually set

#define _RPC_HAL_VERIFY_INTERFACE(_pHalFn) \
           NV_ASSERT_OR_RETURN_PRECOMP(_pHalFn != (void *) iGrp_ipVersions_UNASSIGNED, NV_ERR_NOT_SUPPORTED)

    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcVgpuPfRegRead32);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcDumpProtobufComponent);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcAllocMemory);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGpuExecRegOps);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcRmfsInit);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcUnsetPageDirectory);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGetGspStaticInfo);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGspSetSystemInfo);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcRmfsCleanup);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcSetPageDirectory);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcUnloadingGuestDriver);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcSetRegistry);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcRmfsCloseQueue);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGetStaticInfo);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcIdleChannels);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcUpdateBarPde);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcMapMemoryDma);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcUnmapMemoryDma);
    _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcRmfsTest);

#undef _RPC_HAL_VERIFY_INTERFACE

    return NV_OK;
}


static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v03_00[] = {
        { 0x03000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v04_00[] = {
        { 0x04000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v05_00[] = {
        { 0x05000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v06_00[] = {
        { 0x06000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v07_00[] = {
        { 0x07000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v07_07[] = {
        { 0x07070000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v08_01[] = {
        { 0x08010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v09_08[] = {
        { 0x09080000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v09_0B[] = {
        { 0x090B0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v09_0C[] = {
        { 0x090C0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v12_01[] = {
        { 0x12010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v13_01[] = {
        { 0x13010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v14_00[] = {
        { 0x14000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v14_01[] = {
        { 0x14010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v14_02[] = {
        { 0x14020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v15_00[] = {
        { 0x15000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v15_02[] = {
        { 0x15020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v17_00[] = {
        { 0x17000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v17_04[] = {
        { 0x17040000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v17_05[] = {
        { 0x17050000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_00[] = {
        { 0x18000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_01[] = {
        { 0x18010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_02[] = {
        { 0x18020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_03[] = {
        { 0x18030000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_04[] = {
        { 0x18040000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_05[] = {
        { 0x18050000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_06[] = {
        { 0x18060000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_07[] = {
        { 0x18070000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_08[] = {
        { 0x18080000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_09[] = {
        { 0x18090000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_0A[] = {
        { 0x180A0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_0B[] = {
        { 0x180B0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_0C[] = {
        { 0x180C0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_0D[] = {
        { 0x180D0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_0E[] = {
        { 0x180E0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_0F[] = {
        { 0x180F0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_10[] = {
        { 0x18100000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_11[] = {
        { 0x18110000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_12[] = {
        { 0x18120000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_13[] = {
        { 0x18130000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_14[] = {
        { 0x18140000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_15[] = {
        { 0x18150000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v18_16[] = {
        { 0x18160000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v19_00[] = {
        { 0x19000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v19_01[] = {
        { 0x19010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_00[] = {
        { 0x1A000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_01[] = {
        { 0x1A010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_02[] = {
        { 0x1A020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_03[] = {
        { 0x1A030000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_04[] = {
        { 0x1A040000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_05[] = {
        { 0x1A050000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_06[] = {
        { 0x1A060000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_07[] = {
        { 0x1A070000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_08[] = {
        { 0x1A080000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_09[] = {
        { 0x1A090000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_0A[] = {
        { 0x1A0A0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_0B[] = {
        { 0x1A0B0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_0C[] = {
        { 0x1A0C0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_0D[] = {
        { 0x1A0D0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_0E[] = {
        { 0x1A0E0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_0F[] = {
        { 0x1A0F0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_10[] = {
        { 0x1A100000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_12[] = {
        { 0x1A120000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_13[] = {
        { 0x1A130000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_14[] = {
        { 0x1A140000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_15[] = {
        { 0x1A150000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_16[] = {
        { 0x1A160000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_17[] = {
        { 0x1A170000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_18[] = {
        { 0x1A180000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_1A[] = {
        { 0x1A1A0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_1B[] = {
        { 0x1A1B0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_1C[] = {
        { 0x1A1C0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_1D[] = {
        { 0x1A1D0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_1E[] = {
        { 0x1A1E0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_1F[] = {
        { 0x1A1F0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_20[] = {
        { 0x1A200000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_21[] = {
        { 0x1A210000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_22[] = {
        { 0x1A220000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_23[] = {
        { 0x1A230000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1A_24[] = {
        { 0x1A240000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1B_02[] = {
        { 0x1B020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1B_04[] = {
        { 0x1B040000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1C_02[] = {
        { 0x1C020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1C_04[] = {
        { 0x1C040000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1C_05[] = {
        { 0x1C050000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1C_07[] = {
        { 0x1C070000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1C_08[] = {
        { 0x1C080000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1C_09[] = {
        { 0x1C090000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1C_0A[] = {
        { 0x1C0A0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1C_0B[] = {
        { 0x1C0B0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1C_0C[] = {
        { 0x1C0C0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1D_02[] = {
        { 0x1D020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1D_05[] = {
        { 0x1D050000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1D_06[] = {
        { 0x1D060000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1E_01[] = {
        { 0x1E010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1E_04[] = {
        { 0x1E040000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1E_05[] = {
        { 0x1E050000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1E_06[] = {
        { 0x1E060000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1E_07[] = {
        { 0x1E070000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1E_08[] = {
        { 0x1E080000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1E_0A[] = {
        { 0x1E0A0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1E_0B[] = {
        { 0x1E0B0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1E_0C[] = {
        { 0x1E0C0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1E_0D[] = {
        { 0x1E0D0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1E_0E[] = {
        { 0x1E0E0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1F_00[] = {
        { 0x1F000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1F_03[] = {
        { 0x1F030000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1F_04[] = {
        { 0x1F040000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1F_05[] = {
        { 0x1F050000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1F_07[] = {
        { 0x1F070000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1F_08[] = {
        { 0x1F080000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1F_0A[] = {
        { 0x1F0A0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1F_0B[] = {
        { 0x1F0B0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1F_0C[] = {
        { 0x1F0C0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1F_0D[] = {
        { 0x1F0D0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1F_0E[] = {
        { 0x1F0E0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v1F_0F[] = {
        { 0x1F0F0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v20_00[] = {
        { 0x20000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v20_01[] = {
        { 0x20010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v20_02[] = {
        { 0x20020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v20_03[] = {
        { 0x20030000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v21_02[] = {
        { 0x21020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v21_03[] = {
        { 0x21030000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v21_04[] = {
        { 0x21040000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v21_05[] = {
        { 0x21050000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v21_06[] = {
        { 0x21060000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v21_07[] = {
        { 0x21070000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v21_08[] = {
        { 0x21080000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v21_09[] = {
        { 0x21090000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v21_0A[] = {
        { 0x210A0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPC_IGRP_IP_VERSIONS_RANGES_v21_0B[] = {
        { 0x210B0000, 0xFFFFFFFF, },          // 
    };

#define _RPC_HAL_IGRP_ENTRY_INIT(v) \
    { RPC_IGRP_IP_VERSIONS_RANGES_##v, NV_ARRAY_ELEMENTS(RPC_IGRP_IP_VERSIONS_RANGES_##v), rpc_iGrp_ipVersions_Install_##v, }

    static const IGRP_IP_VERSIONS_ENTRY rpc_iGrp_ipVersions_table[] = {
        _RPC_HAL_IGRP_ENTRY_INIT(v03_00),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v04_00),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v05_00),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v06_00),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v07_00),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v07_07),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v08_01),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v09_08),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v09_0B),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v09_0C),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v12_01),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v13_01),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v14_00),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v14_01),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v14_02),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v15_00),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v15_02),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v17_00),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v17_04),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v17_05),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_00),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_01),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_02),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_03),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_04),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_05),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_06),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_07),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_08),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_09),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_0A),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_0B),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_0C),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_0D),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_0E),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_0F),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_10),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_11),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_12),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_13),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_14),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_15),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v18_16),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v19_00),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v19_01),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_00),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_01),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_02),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_03),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_04),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_05),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_06),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_07),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_08),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_09),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_0A),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_0B),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_0C),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_0D),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_0E),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_0F),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_10),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_12),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_13),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_14),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_15),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_16),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_17),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_18),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_1A),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_1B),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_1C),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_1D),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_1E),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_1F),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_20),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_21),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_22),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_23),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1A_24),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1B_02),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1B_04),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1C_02),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1C_04),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1C_05),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1C_07),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1C_08),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1C_09),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1C_0A),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1C_0B),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1C_0C),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1D_02),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1D_05),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1D_06),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1E_01),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1E_04),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1E_05),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1E_06),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1E_07),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1E_08),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1E_0A),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1E_0B),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1E_0C),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1E_0D),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1E_0E),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1F_00),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1F_03),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1F_04),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1F_05),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1F_07),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1F_08),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1F_0A),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1F_0B),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1F_0C),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1F_0D),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1F_0E),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v1F_0F),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v20_00),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v20_01),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v20_02),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v20_03),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v21_02),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v21_03),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v21_04),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v21_05),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v21_06),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v21_07),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v21_08),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v21_09),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v21_0A),               // 
        _RPC_HAL_IGRP_ENTRY_INIT(v21_0B),               // 
    };

#undef _RPC_HAL_IGRP_ENTRY_INIT

    pInfo->pTable         = rpc_iGrp_ipVersions_table;
    pInfo->numEntries     = NV_ARRAY_ELEMENTS(rpc_iGrp_ipVersions_table);
    pInfo->ifacesWrapupFn = rpc_iGrp_ipVersions_Wrapup;

    return NV_OK;
}


//
// Setup RPC's hal interface function pointers
//

#if defined(RMCFG_HAL_SETUP_TU102)

static void rpcHalIfacesSetup_TU102(RPC_HAL_IFACES *pRpcHal)
{

    // TU102's RPC hal interface function pointer block
    static const RPC_HAL_IFACES rpcHalIfacesInitStruct_TU102 =
    {
        rpcVgpuPfRegRead32_STUB,                 // rpcVgpuPfRegRead32
        rpcDumpProtobufComponent_STUB,           // rpcDumpProtobufComponent
        rpcAllocMemory_STUB,                     // rpcAllocMemory
        rpcGpuExecRegOps_STUB,                   // rpcGpuExecRegOps
        rpcRmfsInit_STUB,                        // rpcRmfsInit
        rpcUnsetPageDirectory_STUB,              // rpcUnsetPageDirectory
        rpcGetGspStaticInfo_STUB,                // rpcGetGspStaticInfo
        rpcGspSetSystemInfo_STUB,                // rpcGspSetSystemInfo
        rpcRmfsCleanup_STUB,                     // rpcRmfsCleanup
        rpcSetPageDirectory_STUB,                // rpcSetPageDirectory
        rpcUnloadingGuestDriver_STUB,            // rpcUnloadingGuestDriver
        rpcSetRegistry_STUB,                     // rpcSetRegistry
        rpcRmfsCloseQueue_STUB,                  // rpcRmfsCloseQueue
        rpcGetStaticInfo_STUB,                   // rpcGetStaticInfo
        rpcIdleChannels_STUB,                    // rpcIdleChannels
        rpcUpdateBarPde_STUB,                    // rpcUpdateBarPde
        rpcMapMemoryDma_STUB,                    // rpcMapMemoryDma
        rpcUnmapMemoryDma_STUB,                  // rpcUnmapMemoryDma
        rpcRmfsTest_STUB,                        // rpcRmfsTest
        rpc_iGrp_ipVersions_getInfo,             // rpc_iGrp_ipVersions_getInfo

    };  // rpcHalIfacesInitStruct_TU102

    // init TU102's RPC function ptrs using the init struct above
    *pRpcHal = rpcHalIfacesInitStruct_TU102;
}

#endif  // TU10X or TU102

#if defined(RMCFG_HAL_SETUP_TU104)

static void rpcHalIfacesSetup_TU104(RPC_HAL_IFACES *pRpcHal)
{
    rpcHalIfacesSetup_TU102(pRpcHal);   // TU104 interfaces identical to TU102
}

#endif  // TU10X or TU104

#if defined(RMCFG_HAL_SETUP_TU106)

static void rpcHalIfacesSetup_TU106(RPC_HAL_IFACES *pRpcHal)
{
    rpcHalIfacesSetup_TU102(pRpcHal);   // TU106 interfaces identical to TU102
}

#endif  // TU10X or TU106

#if defined(RMCFG_HAL_SETUP_TU116)

static void rpcHalIfacesSetup_TU116(RPC_HAL_IFACES *pRpcHal)
{
    rpcHalIfacesSetup_TU102(pRpcHal);   // TU116 interfaces identical to TU102
}

#endif  // TU10X or TU116

#if defined(RMCFG_HAL_SETUP_TU117)

static void rpcHalIfacesSetup_TU117(RPC_HAL_IFACES *pRpcHal)
{
    rpcHalIfacesSetup_TU102(pRpcHal);   // TU117 interfaces identical to TU102
}

#endif  // TU10X or TU117

#if defined(RMCFG_HAL_SETUP_GA100)

static void rpcHalIfacesSetup_GA100(RPC_HAL_IFACES *pRpcHal)
{

    // GA100's RPC hal interface function pointer block
    static const RPC_HAL_IFACES rpcHalIfacesInitStruct_GA100 =
    {
        rpcVgpuPfRegRead32_STUB,                 // rpcVgpuPfRegRead32
        rpcDumpProtobufComponent_STUB,           // rpcDumpProtobufComponent
        rpcAllocMemory_STUB,                     // rpcAllocMemory
        rpcGpuExecRegOps_STUB,                   // rpcGpuExecRegOps
        rpcRmfsInit_STUB,                        // rpcRmfsInit
        rpcUnsetPageDirectory_STUB,              // rpcUnsetPageDirectory
        rpcGetGspStaticInfo_STUB,                // rpcGetGspStaticInfo
        rpcGspSetSystemInfo_STUB,                // rpcGspSetSystemInfo
        rpcRmfsCleanup_STUB,                     // rpcRmfsCleanup
        rpcSetPageDirectory_STUB,                // rpcSetPageDirectory
        rpcUnloadingGuestDriver_STUB,            // rpcUnloadingGuestDriver
        rpcSetRegistry_STUB,                     // rpcSetRegistry
        rpcRmfsCloseQueue_STUB,                  // rpcRmfsCloseQueue
        rpcGetStaticInfo_STUB,                   // rpcGetStaticInfo
        rpcIdleChannels_STUB,                    // rpcIdleChannels
        rpcUpdateBarPde_STUB,                    // rpcUpdateBarPde
        rpcMapMemoryDma_STUB,                    // rpcMapMemoryDma
        rpcUnmapMemoryDma_STUB,                  // rpcUnmapMemoryDma
        rpcRmfsTest_STUB,                        // rpcRmfsTest
        rpc_iGrp_ipVersions_getInfo,             // rpc_iGrp_ipVersions_getInfo

    };  // rpcHalIfacesInitStruct_GA100

    // init GA100's RPC function ptrs using the init struct above
    *pRpcHal = rpcHalIfacesInitStruct_GA100;
}

#endif  // GA10X or GA100

#if defined(RMCFG_HAL_SETUP_GA102)

static void rpcHalIfacesSetup_GA102(RPC_HAL_IFACES *pRpcHal)
{
    rpcHalIfacesSetup_GA100(pRpcHal);   // GA102 interfaces almost identical to GA100

}

#endif  // GA10X or GA102

#if defined(RMCFG_HAL_SETUP_GA103)

static void rpcHalIfacesSetup_GA103(RPC_HAL_IFACES *pRpcHal)
{
    rpcHalIfacesSetup_GA102(pRpcHal);   // GA103 interfaces identical to GA102
}

#endif  // GA10X or GA103

#if defined(RMCFG_HAL_SETUP_GA104)

static void rpcHalIfacesSetup_GA104(RPC_HAL_IFACES *pRpcHal)
{
    rpcHalIfacesSetup_GA102(pRpcHal);   // GA104 interfaces identical to GA102
}

#endif  // GA10X or GA104

#if defined(RMCFG_HAL_SETUP_GA106)

static void rpcHalIfacesSetup_GA106(RPC_HAL_IFACES *pRpcHal)
{
    rpcHalIfacesSetup_GA102(pRpcHal);   // GA106 interfaces identical to GA102
}

#endif  // GA10X or GA106

#if defined(RMCFG_HAL_SETUP_GA107)

static void rpcHalIfacesSetup_GA107(RPC_HAL_IFACES *pRpcHal)
{
    rpcHalIfacesSetup_GA102(pRpcHal);   // GA107 interfaces identical to GA102
}

#endif  // GA10X or GA107

#if defined(RMCFG_HAL_SETUP_AD102)

static void rpcHalIfacesSetup_AD102(RPC_HAL_IFACES *pRpcHal)
{

    // AD102's RPC hal interface function pointer block
    static const RPC_HAL_IFACES rpcHalIfacesInitStruct_AD102 =
    {
        rpcVgpuPfRegRead32_STUB,                 // rpcVgpuPfRegRead32
        rpcDumpProtobufComponent_STUB,           // rpcDumpProtobufComponent
        rpcAllocMemory_STUB,                     // rpcAllocMemory
        rpcGpuExecRegOps_STUB,                   // rpcGpuExecRegOps
        rpcRmfsInit_STUB,                        // rpcRmfsInit
        rpcUnsetPageDirectory_STUB,              // rpcUnsetPageDirectory
        rpcGetGspStaticInfo_STUB,                // rpcGetGspStaticInfo
        rpcGspSetSystemInfo_STUB,                // rpcGspSetSystemInfo
        rpcRmfsCleanup_STUB,                     // rpcRmfsCleanup
        rpcSetPageDirectory_STUB,                // rpcSetPageDirectory
        rpcUnloadingGuestDriver_STUB,            // rpcUnloadingGuestDriver
        rpcSetRegistry_STUB,                     // rpcSetRegistry
        rpcRmfsCloseQueue_STUB,                  // rpcRmfsCloseQueue
        rpcGetStaticInfo_STUB,                   // rpcGetStaticInfo
        rpcIdleChannels_STUB,                    // rpcIdleChannels
        rpcUpdateBarPde_STUB,                    // rpcUpdateBarPde
        rpcMapMemoryDma_STUB,                    // rpcMapMemoryDma
        rpcUnmapMemoryDma_STUB,                  // rpcUnmapMemoryDma
        rpcRmfsTest_STUB,                        // rpcRmfsTest
        rpc_iGrp_ipVersions_getInfo,             // rpc_iGrp_ipVersions_getInfo

    };  // rpcHalIfacesInitStruct_AD102

    // init AD102's RPC function ptrs using the init struct above
    *pRpcHal = rpcHalIfacesInitStruct_AD102;
}

#endif  // AD10X or AD102

#if defined(RMCFG_HAL_SETUP_AD103)

static void rpcHalIfacesSetup_AD103(RPC_HAL_IFACES *pRpcHal)
{
    rpcHalIfacesSetup_AD102(pRpcHal);   // AD103 interfaces identical to AD102
}

#endif  // AD10X or AD103

#if defined(RMCFG_HAL_SETUP_AD104)

static void rpcHalIfacesSetup_AD104(RPC_HAL_IFACES *pRpcHal)
{
    rpcHalIfacesSetup_AD102(pRpcHal);   // AD104 interfaces identical to AD102
}

#endif  // AD10X or AD104

#if defined(RMCFG_HAL_SETUP_AD106)

static void rpcHalIfacesSetup_AD106(RPC_HAL_IFACES *pRpcHal)
{
    rpcHalIfacesSetup_AD102(pRpcHal);   // AD106 interfaces identical to AD102
}

#endif  // AD10X or AD106

#if defined(RMCFG_HAL_SETUP_AD107)

static void rpcHalIfacesSetup_AD107(RPC_HAL_IFACES *pRpcHal)
{
    rpcHalIfacesSetup_AD102(pRpcHal);   // AD107 interfaces identical to AD102
}

#endif  // AD10X or AD107

#if defined(RMCFG_HAL_SETUP_GH100)

static void rpcHalIfacesSetup_GH100(RPC_HAL_IFACES *pRpcHal)
{

    // GH100's RPC hal interface function pointer block
    static const RPC_HAL_IFACES rpcHalIfacesInitStruct_GH100 =
    {
        rpcVgpuPfRegRead32_STUB,                 // rpcVgpuPfRegRead32
        rpcDumpProtobufComponent_STUB,           // rpcDumpProtobufComponent
        rpcAllocMemory_STUB,                     // rpcAllocMemory
        rpcGpuExecRegOps_STUB,                   // rpcGpuExecRegOps
        rpcRmfsInit_STUB,                        // rpcRmfsInit
        rpcUnsetPageDirectory_STUB,              // rpcUnsetPageDirectory
        rpcGetGspStaticInfo_STUB,                // rpcGetGspStaticInfo
        rpcGspSetSystemInfo_STUB,                // rpcGspSetSystemInfo
        rpcRmfsCleanup_STUB,                     // rpcRmfsCleanup
        rpcSetPageDirectory_STUB,                // rpcSetPageDirectory
        rpcUnloadingGuestDriver_STUB,            // rpcUnloadingGuestDriver
        rpcSetRegistry_STUB,                     // rpcSetRegistry
        rpcRmfsCloseQueue_STUB,                  // rpcRmfsCloseQueue
        rpcGetStaticInfo_STUB,                   // rpcGetStaticInfo
        rpcIdleChannels_STUB,                    // rpcIdleChannels
        rpcUpdateBarPde_STUB,                    // rpcUpdateBarPde
        rpcMapMemoryDma_STUB,                    // rpcMapMemoryDma
        rpcUnmapMemoryDma_STUB,                  // rpcUnmapMemoryDma
        rpcRmfsTest_STUB,                        // rpcRmfsTest
        rpc_iGrp_ipVersions_getInfo,             // rpc_iGrp_ipVersions_getInfo

    };  // rpcHalIfacesInitStruct_GH100

    // init GH100's RPC function ptrs using the init struct above
    *pRpcHal = rpcHalIfacesInitStruct_GH100;
}

#endif  // GH10X or GH100





#endif  // RMCFG_ENGINE_SETUP



// Were any _MOCK interfaces generated into g_rpc_private.h ?
#define RPC_MOCK_FUNCTIONS_GENERATED       0


#endif  // _G_RPC_PRIVATE_H_
