// This file is automatically generated by rmconfig - DO NOT EDIT!
//
// HAL stubs, generated by rmconfig.
//
// Profile:  shipping-gpus-openrm
// Template: templates/gt_hal_stubs.h
//
// Chips:    TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
//

#ifndef _G_RMCFG_HAL_STUBS_H_
#define _G_RMCFG_HAL_STUBS_H_

// pull in private headers for each engine
#include "g_rpc_private.h"


#include "g_hal.h"

// HACK: a global var unique to the ipVersions _UNASSIGNED routines to ensure this function
//       is not aliased by link-time-optimizations with a _STUB fn that might actually
//       be assigned to a hal method as that would break the <ENG>_HAL_VERIFY_INTERFACE
//       test.
NV_STATUS iGrp_ipVersions_UNIQUIFIER;

// the "_UNASSIGNED" function for all IP_VERSIONS dynamic interfaces
NV_STATUS iGrp_ipVersions_UNASSIGNED(void)
{
    NV_ASSERT_PRECOMP(0 && "iGrp_ipVersions_UNASSIGNED");
    return NV_ERR_NOT_SUPPORTED +
           iGrp_ipVersions_UNIQUIFIER;    // will be 0
}

//
// generated _STUB functions
//

// DISP:hal:IGRP_IP_VERSIONS_GET_INFO  -  DISP disabled
NV_STATUS disp_iGrp_ipVersions_getInfo_STUB(
    IGRP_IP_VERSIONS_TABLE_INFO *pArg1
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// DPU:hal:IGRP_IP_VERSIONS_GET_INFO  -  DPU disabled
NV_STATUS dpu_iGrp_ipVersions_getInfo_STUB(
    IGRP_IP_VERSIONS_TABLE_INFO *pArg1
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:GET_SWAP_READY_FUNC_FOR_PINSET  -  GPIO disabled
NvU32 gpioGetSwapReadyFuncForPinset_STUB(
    NvU32         pinset
)
{
    NV_ASSERT_PRECOMP(0 && "gpioGetSwapReadyFuncForPinset_STUB()    GPIO: HAL_INTERFACES: GET_SWAP_READY_FUNC_FOR_PINSET");
    return (NvU32) 0;
}

// GPIO:hal:GET_FEATURE_STATE_HAL  -  GPIO disabled
NV_STATUS gpioGetFeatureStateHal_STUB(
    POBJGPIO      pGpio,
    NvU32         function,
    NvU32         feature,
    NvBool       *bState
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:SET_FEATURE_STATE_HAL  -  GPIO disabled
NV_STATUS gpioSetFeatureStateHal_STUB(
    POBJGPIO      pGpio,
    NvU32         function,
    NvU32         feature,
    NvBool        bState
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:INTERRUPT_PENDING  -  GPIO disabled
NvBool gpioInterruptPending_STUB(
    POBJGPIO      pGpio
)
{
    return NV_FALSE;
}

// GPIO:hal:DISABLE_INTERRUPTS  -  GPIO disabled
void gpioDisableInterrupts_STUB(
    POBJGPIO      pGpio
)
{
}

// GPIO:hal:CLEAR_INTERRUPTS  -  GPIO disabled
void gpioClearInterrupts_STUB(
    POBJGPIO      pGpio
)
{
}

// GPIO:hal:READ_INTERRUPT_STATUS  -  GPIO disabled
void gpioReadInterruptStatus_STUB(
    POBJGPIO      pGpio,
    NvU64        *intrStatus
)
{
}

// GPIO:hal:SERVICE_EVENT  -  GPIO disabled
NV_STATUS gpioServiceEvent_STUB(
    POBJGPIO      pGpio,
    NvU64        *intrStatus
)
{
    return NV_OK;
}

// GPIO:hal:GET_INTERRUPT_HAL  -  GPIO disabled
NvBool gpioGetInterruptHal_STUB(
    POBJGPIO      pGpio,
    NvU32         gpioFunc,
    NvU32         direction
)
{
    return NV_FALSE;
}

// GPIO:hal:SET_INTERRUPT_HAL  -  GPIO disabled
NV_STATUS gpioSetInterruptHal_STUB(
    POBJGPIO      pGpio,
    NvU32         gpioFunc,
    NvU32         direction,
    NvU32         enable
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:GET_INTERRUPT_ENABLE_HAL  -  GPIO disabled
NvBool gpioGetInterruptEnableHal_STUB(
    POBJGPIO      pGpio,
    NvU32         gpioFunc,
    NvU32         direction
)
{
    return NV_FALSE;
}

// GPIO:hal:INIT_HW  -  GPIO disabled
NV_STATUS gpioInitHw_STUB(
    POBJGPIO      pGpio
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:DESTROY_HW  -  GPIO disabled
NV_STATUS gpioDestroyHw_STUB(
    POBJGPIO      pGpio
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:UPDATE_AND_PROGRAM_LCD_GPIO_ENTRIES  -  GPIO disabled
void gpioUpdateAndProgramLcdGpioEntries_STUB(
    POBJGPIO      pGpio,
    NvU32         displayId,
    NvBool        bWriteHw
)
{
}

// GPIO:hal:GET_REGISTER_FOR_FUNCTION_HAL  -  GPIO disabled
void gpioGetRegisterForFunctionHal_STUB(
    POBJGPIO      pGpio,
    NvU32         func,
    NvU32        *reg,
    NvU32        *oldValue,
    NvU32        *value_1,
    NvU32        *value_0
)
{
}

// GPIO:hal:WRITE_HW_ENUM_HAL  -  GPIO disabled
NV_STATUS gpioWriteHwEnumHal_STUB(
    POBJGPIO      pGpio,
    NvU32         function,
    NvU8          outHwEnum
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:GET_EXCEPTION_DATA  -  GPIO disabled
NV_STATUS gpioGetExceptionData_STUB(
    POBJGPIO      pGpio
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:GET_REGISTER_AND_MASK_HAL  -  GPIO disabled
NV_STATUS gpioGetRegisterAndMaskHal_STUB(
    POBJGPIO      pGpio,
    NvU32         Function,
    NvU32         State,
    NvU32        *Register,
    NvU32        *Mask,
    NvU32        *Value
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:GET_TRIGGER_REGISTER_AND_MASK_HAL  -  GPIO disabled
NV_STATUS gpioGetTriggerRegisterAndMaskHal_STUB(
    POBJGPIO      pGpio,
    NvU32        *pRegAddr,
    NvU32        *pAndMask,
    NvU32        *pOrMask,
    NvBool        bDone
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:GET_PIN_COUNT  -  GPIO disabled
NvU32 gpioGetPinCount_STUB(
    POBJGPIO      pGpio
)
{
    return (NvU32) 0;
}

// GPIO:hal:DUMP_RC_ERROR_REGS  -  GPIO disabled
NV_STATUS gpioDumpRCErrorRegs_STUB(
    POBJGPU       pGpu,
    POBJGPIO      pGpio,
    PRB_ENCODER  *pArg3
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:INSERT_FRAME_LOCK_HEADER_LOCK_PIN_ENTRY  -  GPIO disabled
NV_STATUS gpioInsertFrameLockHeaderLockPinEntry_STUB(
    POBJGPIO      pGpio,
    NvU32         function,
    NvBool        bIsFrameLockHeaderLockPin
)
{
    return NV_OK;
}

// GPIO:hal:GET_FRAME_LOCK_HEADER_LOCK_PINS  -  GPIO disabled
NV_STATUS gpioGetFrameLockHeaderLockPins_STUB(
    POBJGPIO      pGpio,
    NvU32        *pFrameLockPin,
    NvU32        *pRasterLockPin,
    NvU32        *pFlipLockPin
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:PIN_WRITE_FUNCTION_STATUS  -  GPIO disabled
NV_STATUS gpioPinWriteFunctionStatus_STUB(
    POBJGPIO      pGpio,
    NvU32         gpioFunc,
    NvU32         pin,
    NvBool        bEnabled
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:ACTIVATE_HW_FUNCTION_HAL  -  GPIO disabled
NV_STATUS gpioActivateHwFunctionHal_STUB(
    POBJGPIO      pGpio,
    NvU32         gpioFunc,
    NvU32         pin
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:DEACTIVATE_HW_FUNCTION_HAL  -  GPIO disabled
NV_STATUS gpioDeactivateHwFunctionHal_STUB(
    POBJGPIO      pGpio,
    NvU32         gpioFunc,
    NvU32         pin
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:INIT_PIN_FEATURE_FLAG  -  GPIO disabled
NV_STATUS gpioInitPinFeatureFlag_STUB(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvU8          outHwEnum,
    NvU8          inHwEnum
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:PROGRAM_PIN  -  GPIO disabled
NV_STATUS gpioProgramPin_STUB(
    POBJGPIO      pGpio,
    NvU32         gpioPinDCB,
    NvU32         halIndex,
    NvBool        bTrigger
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:RM_PMU_SYNC_STATE_INIT_HAL  -  GPIO disabled
NV_STATUS gpioRmPmuSyncStateInitHal_STUB(
    POBJGPIO      pGpio
)
{
    return NV_OK;
}

// GPIO:hal:FUNC_TO_SOR_IDX_HAL  -  GPIO disabled
NvU32 gpioFuncToSorIdxHal_STUB(
    POBJGPIO      pGpio,
    POBJGPU       pGpu,
    NvU32         gpioFunc
)
{
    return NV_U32_MAX;
}

// GPIO:hal:OVERRIDE_GPIO_WAR_FOR_BUG_1795624  -  GPIO disabled
void gpioOverrideGpioWarForBug1795624_STUB(
    POBJGPIO      pGpio
)
{
}

// GPIO:hal:SET_SWAPRDY_FOR_BUG_200374184  -  GPIO disabled
NV_STATUS gpioSetSwaprdyForBug200374184_STUB(
    POBJGPU       pGpu,
    NvU32         swaprdyOutPin,
    NvBool        bEnable
)
{
    return NV_OK;
}

// GPIO:hal:OUTPUT_TRIGGER_UPDATE_UC  -  GPIO disabled
NV_STATUS gpioOutputTriggerUpdateUC_STUB(
    POBJGPU       pGpu,
    POBJGPIO      pGpio
)
{
    return NV_OK;
}

// GPIO:hal:OVERRIDE_GPIO_WAR_FOR_BUG_2701109  -  GPIO disabled
void gpioOverrideGpioWarForBug2701109_STUB(
    POBJGPU       pGpu,
    POBJGPIO      pGpio
)
{
}

// GPIO:hal:INIT_SW  -  GPIO disabled
NV_STATUS gpioInitSw_STUB(
    POBJGPIO      pGpio
)
{
    return NV_OK;
}

// GPIO:hal:DESTROY_SW  -  GPIO disabled
void gpioDestroySw_STUB(
    POBJGPIO      pGpio
)
{
}

// GPIO:hal:INIT_AND_GET_PIN_NUM  -  GPIO disabled
NvU32 gpioInitAndGetPinNum_STUB(
    POBJGPIO      pGpio,
    NvU32         arg2,
    NvU32        *pArg3
)
{
    return (NvU32) 0;
}

// GPIO:hal:OVERRIDE_GPIO_WAR_FOR_BUG_2561134  -  GPIO disabled
void gpioOverrideGpioWarForBug2561134_STUB(
    POBJGPU       pGpu,
    POBJGPIO      pGpio
)
{
}

// GPIO:hal:SET_PROPERTIES_LIST  -  GPIO disabled
void gpioSetPropertiesList_STUB(
    POBJGPU       pGpu,
    POBJGPIO      pGpio
)
{
}

// GPIO:hal:READ_INPUT  -  GPIO disabled
NV_STATUS gpioReadInput_MISSING(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvU32         halIndex,
    NvU32        *pValue
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:PROGRAM_OUTPUT  -  GPIO disabled
void gpioProgramOutput_MISSING(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvU32         value,
    NvU32         halIndex
)
{
}

// GPIO:hal:READ_OUTPUT  -  GPIO disabled
NvBool gpioReadOutput_MISSING(
    POBJGPIO      pGpio,
    NvU32         gpioPin
)
{
    return NV_FALSE;
}

// GPIO:hal:PROGRAM_DIRECTION  -  GPIO disabled
void gpioProgramDirection_MISSING(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvBool        input,
    NvU32         halIndex
)
{
}

// GPIO:hal:READ_DIRECTION  -  GPIO disabled
NvBool gpioReadDirection_MISSING(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvU32         halIndex
)
{
    return NV_FALSE;
}

// GPIO:hal:INIT_DEFAULT_ENTRIES  -  GPIO disabled
void gpioInitDefaultEntries_MISSING(
    POBJGPIO      pGpio
)
{
}

// GPIO:hal:SET_STATE_LIST_HAL  -  GPIO disabled
void gpioSetStateListHal_MISSING(
    POBJGPIO      pGpio,
    PGPIO_FUNC_LIST_ITEM  pList,
    NvU32         count
)
{
}

// GPIO:hal:IS_FEATURE_AVAILABLE_HAL  -  GPIO disabled
NvBool gpioIsFeatureAvailableHal_MISSING(
    POBJGPIO      pGpio,
    NvU32         function,
    NvU32         feature
)
{
    return NV_FALSE;
}

// GPIO:hal:GET_PWM_CONTROL_HAL  -  GPIO disabled
NV_STATUS gpioGetPwmControlHal_MISSING(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvU32        *pFlags,
    NvU32        *pPeriod,
    NvU32        *pDutyCycle,
    NvU32         halIndex
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:SET_PWM_CONTROL_HAL  -  GPIO disabled
NV_STATUS gpioSetPwmControlHal_MISSING(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvU32        *pFlags,
    NvU32        *pPeriod,
    NvU32        *pDutyCycle,
    NvU32         halIndex,
    NvBool        bSkipPinInit
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:GET_PWM_PARAMETERS_HAL  -  GPIO disabled
NV_STATUS gpioGetPwmParametersHal_MISSING(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvU32        *pMaxPeriod,
    NvU32         halIndex
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:GET_FUNC_PWM_SENSE  -  GPIO disabled
NvU32 gpioGetFuncPwmSense_MISSING(
    POBJGPIO      pGpio,
    NvU32         func
)
{
    return (NvU32) 0;
}

// GPIO:hal:WRITE_PIN_HW_ENUM  -  GPIO disabled
NV_STATUS gpioWritePinHwEnum_MISSING(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvU8          outHwEnum
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:CHECK_PROTECTION  -  GPIO disabled
NV_STATUS gpioCheckProtection_MISSING(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvBool       *pbIsProtected
)
{
    return NV_ERR_NOT_SUPPORTED;
}

// GPIO:hal:READ_INPUT  -  GPIO disabled
NV_STATUS gpioReadInput_FWCLIENT(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvU32         halIndex,
    NvU32        *pValue
)
{
    return NV_OK;
}

// GPIO:hal:PROGRAM_OUTPUT  -  GPIO disabled
void gpioProgramOutput_FWCLIENT(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvU32         value,
    NvU32         halIndex
)
{
}

// GPIO:hal:READ_OUTPUT  -  GPIO disabled
NvBool gpioReadOutput_FWCLIENT(
    POBJGPIO      pGpio,
    NvU32         gpioPin
)
{
    return NV_FALSE;
}

// GPIO:hal:PROGRAM_DIRECTION  -  GPIO disabled
void gpioProgramDirection_FWCLIENT(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvBool        input,
    NvU32         halIndex
)
{
}

// GPIO:hal:READ_DIRECTION  -  GPIO disabled
NvBool gpioReadDirection_FWCLIENT(
    POBJGPIO      pGpio,
    NvU32         gpioPin,
    NvU32         halIndex
)
{
    return NV_FALSE;
}

// GPIO:hal:GET_INTERRUPT_HAL  -  GPIO disabled
NvBool gpioGetInterruptHal_FWCLIENT(
    POBJGPIO      pGpio,
    NvU32         gpioFunc,
    NvU32         direction
)
{
    return NV_FALSE;
}

// GPIO:hal:SET_INTERRUPT_HAL  -  GPIO disabled
NV_STATUS gpioSetInterruptHal_FWCLIENT(
    POBJGPIO      pGpio,
    NvU32         gpioFunc,
    NvU32         direction,
    NvU32         enable
)
{
    return NV_OK;
}

// GPIO:hal:GET_EXCEPTION_DATA  -  GPIO disabled
NV_STATUS gpioGetExceptionData_FWCLIENT(
    POBJGPIO      pGpio
)
{
    return NV_OK;
}

// GPIO:hal:INIT_SW  -  GPIO disabled
NV_STATUS gpioInitSw_FWCLIENT(
    POBJGPIO      pGpio
)
{
    return NV_OK;
}

// GPIO:hal:DESTROY_SW  -  GPIO disabled
void gpioDestroySw_FWCLIENT(
    POBJGPIO      pGpio
)
{
}

// GPIO:hal:INIT_AND_GET_PIN_NUM  -  GPIO disabled
NvU32 gpioInitAndGetPinNum_FWCLIENT(
    POBJGPIO      pGpio,
    NvU32         arg2,
    NvU32        *pArg3
)
{
    return (NvU32) 0;
}

// RPC:hal:VGPU_PF_REG_READ32  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcVgpuPfRegRead32_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc,
    NvU64         arg3,
    NvU32        *pArg4,
    NvU32         arg5
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:DUMP_PROTOBUF_COMPONENT  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcDumpProtobufComponent_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc,
    PRB_ENCODER  *pPrbEnc,
    NVD_STATE    *pNvDumpState,
    NVDUMP_COMPONENT  component
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:ALLOC_MEMORY  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcAllocMemory_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc,
    NvHandle      arg3,
    NvHandle      arg4,
    NvHandle      arg5,
    NvU32         arg6,
    NvU32         arg7,
    MEMORY_DESCRIPTOR *pArg8
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:GPU_EXEC_REG_OPS  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcGpuExecRegOps_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc,
    NvHandle      arg3,
    NvHandle      arg4,
    NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS *pArg5,
    NV2080_CTRL_GPU_REG_OP *pArg6
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:RMFS_INIT  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcRmfsInit_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc,
    PMEMORY_DESCRIPTOR  arg3
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:UNSET_PAGE_DIRECTORY  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcUnsetPageDirectory_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc,
    NvHandle      arg3,
    NvHandle      arg4,
    NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS *pArg5
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:GET_GSP_STATIC_INFO  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcGetGspStaticInfo_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:GSP_SET_SYSTEM_INFO  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcGspSetSystemInfo_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:RMFS_CLEANUP  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcRmfsCleanup_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:SET_PAGE_DIRECTORY  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcSetPageDirectory_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc,
    NvHandle      arg3,
    NvHandle      arg4,
    NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS *pArg5
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:UNLOADING_GUEST_DRIVER  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcUnloadingGuestDriver_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc,
    NvBool        arg3,
    NvBool        arg4,
    NvU32         arg5
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:SET_REGISTRY  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcSetRegistry_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:RMFS_CLOSE_QUEUE  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcRmfsCloseQueue_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:GET_STATIC_INFO  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcGetStaticInfo_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:IDLE_CHANNELS  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcIdleChannels_STUB(
    OBJGPU       *pArg1,
    POBJRPC       pRpc,
    NvHandle     *phclients,
    NvHandle     *phdevices,
    NvHandle     *phchannels,
    NvU32         nentries,
    NvU32         flags,
    NvU32         timeout
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:UPDATE_BAR_PDE  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcUpdateBarPde_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc,
    NV_RPC_UPDATE_PDE_BAR_TYPE  arg3,
    NvU64         arg4,
    NvU64         arg5
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:MAP_MEMORY_DMA  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcMapMemoryDma_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc,
    NvHandle      arg3,
    NvHandle      arg4,
    NvHandle      arg5,
    NvHandle      arg6,
    NvU64         arg7,
    NvU64         arg8,
    NvU32         arg9,
    NvU64        *pArg10
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:UNMAP_MEMORY_DMA  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcUnmapMemoryDma_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc,
    NvHandle      arg3,
    NvHandle      arg4,
    NvHandle      arg5,
    NvHandle      arg6,
    NvU32         arg7,
    NvU64         arg8
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPC:hal:RMFS_TEST  -  TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X
NV_STATUS rpcRmfsTest_STUB(
    POBJGPU       pGpu,
    POBJRPC       pRpc,
    NvU32         arg3,
    NvU32         arg4,
    NvU32         arg5,
    NvU32         arg6
)
{
    return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;
}

// RPCSTRUCTURECOPY:hal:NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS  -  RPCSTRUCTURECOPY disabled
NV_STATUS deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB(
    NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *data,
    NvU8         *stream,
    NvU32         streamSize,
    NvU32        *offset
)
{
    return NV_OK;
}

// RPCSTRUCTURECOPY:hal:IGRP_IP_VERSIONS_GET_INFO  -  RPCSTRUCTURECOPY disabled
NV_STATUS rpcstructurecopy_iGrp_ipVersions_getInfo_STUB(
    IGRP_IP_VERSIONS_TABLE_INFO *pArg1
)
{
    return NV_ERR_NOT_SUPPORTED;
}




//
// "missing engine" setup sequences, if any
//

// Install the _MISSING overrides for GPIO: HAL_INTERFACES
void gpioHalIfacesSetup_MISSING(GPIO_HAL_IFACES *pGpioHal)
{
    // GPIO disabled by rmconfig; no additional MISSING support needed
}






#endif  // _G_RMCFG_HAL_STUBS_H_
